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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x5C byte (0x0)
mem_usage : registers
protection :

Registers

WKUP_CTRL_REG

WKUP_SELECT_P0_REG

WKUP_SELECT_P1_REG

WKUP_POL_P0_REG

WKUP_POL_P1_REG

WKUP_STATUS_P0_REG

WKUP_STATUS_P1_REG

WKUP_CLEAR_P0_REG

WKUP_CLEAR_P1_REG

WKUP_SEL_GPIO_P0_REG

WKUP_SEL_GPIO_P1_REG

WKUP_RESET_IRQ_REG


WKUP_CTRL_REG

Control register for the wakeup counter
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKUP_CTRL_REG WKUP_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKUP_DEB_VALUE WKUP_SFT_KEYHIT WKUP_ENABLE_IRQ

WKUP_DEB_VALUE : Wakeup debounce time. If set to 0, no debouncing will be done. Debounce time: N*1 ms. N =1..63
bits : 0 - 5 (6 bit)
access : read-write

WKUP_SFT_KEYHIT : 0 = no effect 1 = emulate key hit. First make this bit 0 before any new key hit can be sensed.
bits : 6 - 12 (7 bit)
access : read-write

WKUP_ENABLE_IRQ : 0: no interrupt will be enabled 1: if you have an event an IRQ will be generated
bits : 7 - 14 (8 bit)
access : read-write


WKUP_SELECT_P0_REG

select which inputs from P0 port can trigger wkup counter
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKUP_SELECT_P0_REG WKUP_SELECT_P0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKUP_SELECT_P0

WKUP_SELECT_P0 : 0: input P0_xx is not enabled for wakeup event 1: input P0_xx is enabled for wakeup event
bits : 0 - 31 (32 bit)
access : read-write


WKUP_SELECT_P1_REG

select which inputs from P1 port can trigger wkup counter
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKUP_SELECT_P1_REG WKUP_SELECT_P1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKUP_SELECT_P1

WKUP_SELECT_P1 : 0: input P1_xx is not enabled for wakeup event 1: input P1_xx is enabled for wakeup event
bits : 0 - 22 (23 bit)
access : read-write


WKUP_POL_P0_REG

select the sesitivity polarity for each P0 input
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKUP_POL_P0_REG WKUP_POL_P0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKUP_POL_P0

WKUP_POL_P0 : 0: enabled input P0_xx will give an event if that input goes high 1: enabled input P0_xx will give an event if that input goes low
bits : 0 - 31 (32 bit)
access : read-write


WKUP_POL_P1_REG

select the sesitivity polarity for each P1 input
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKUP_POL_P1_REG WKUP_POL_P1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKUP_POL_P1

WKUP_POL_P1 : 0: enabled input P1_xx will give an event if that input goes high 1: enabled input P1_xx will give an event if that input goes low
bits : 0 - 22 (23 bit)
access : read-write


WKUP_STATUS_P0_REG

Event status register for P0
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKUP_STATUS_P0_REG WKUP_STATUS_P0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKUP_STAT_P0

WKUP_STAT_P0 : Contains the latched value of any toggle of the GPIOs Port P0. WKUP_STAT_P0[0] -> P0_00.
bits : 0 - 31 (32 bit)
access : read-only


WKUP_STATUS_P1_REG

Event status register for P1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKUP_STATUS_P1_REG WKUP_STATUS_P1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKUP_STAT_P1

WKUP_STAT_P1 : Contains the latched value of any toggle of the GPIOs Port P1 WKUP_STATUS_1[0] -> P1_00.
bits : 0 - 22 (23 bit)
access : read-only


WKUP_CLEAR_P0_REG

Clear event register for P0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKUP_CLEAR_P0_REG WKUP_CLEAR_P0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKUP_CLEAR_P0

WKUP_CLEAR_P0 : Clear latched value of the GPIOs P0 when corresponding bit is 1
bits : 0 - 31 (32 bit)
access : write-only


WKUP_CLEAR_P1_REG

Clear event register for P1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKUP_CLEAR_P1_REG WKUP_CLEAR_P1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKUP_CLEAR_P1

WKUP_CLEAR_P1 : Clear latched value of the GPIOs P1 when corresponding bit is 1
bits : 0 - 22 (23 bit)
access : write-only


WKUP_SEL_GPIO_P0_REG

select which inputs from P0 port can trigger interrupt
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKUP_SEL_GPIO_P0_REG WKUP_SEL_GPIO_P0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKUP_SEL_GPIO_P0

WKUP_SEL_GPIO_P0 : 0: input P0_xx is not enabled for GPIO interrupt 1: input P0_xx is enabled for GPIO interrupt
bits : 0 - 31 (32 bit)
access : read-write


WKUP_SEL_GPIO_P1_REG

select which inputs from P1 port can trigger interrupt
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKUP_SEL_GPIO_P1_REG WKUP_SEL_GPIO_P1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKUP_SEL_GPIO_P1

WKUP_SEL_GPIO_P1 : 0: input P1_xx is not enabled for GPIO interrupt 1: input P1_xx is enabled for GPIO interrupt
bits : 0 - 22 (23 bit)
access : read-write


WKUP_RESET_IRQ_REG

Reset wakeup interrupt
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKUP_RESET_IRQ_REG WKUP_RESET_IRQ_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKUP_IRQ_RST

WKUP_IRQ_RST : writing any value to this register will reset the interrupt. reading always returns 0.
bits : 0 - 15 (16 bit)
access : write-only



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