Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IPVERSION
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LOAD : Load command
bits : 0 - 0 (1 bit)
access : write-only
CLEAR : Clear command
bits : 1 - 1 (1 bit)
access : write-only
No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX : Mux Configuration
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : STATIC
Static
1 : DUPLEX
Duplex
2 : TRIPLEX
Triplex
3 : QUADRUPLEX
Quadruplex
End of enumeration elements list.
WAVE : Waveform Selection
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : TYPEB
Type B waveform
1 : TYPEA
Type A waveform
End of enumeration elements list.
CHGRDST : Charge Redistribution Cycles
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable charge redistribution.
1 : ONE
Use 1 prescaled low frequency clock cycle for charge redistribution.
2 : TWO
Use 2 prescaled low frequency clock cycles for charge redistribution.
3 : THREE
Use 3 prescaled low frequency clock cycles for charge redistribution.
4 : FOUR
Use 4 prescaled low frequency clock cycles for charge redistribution.
End of enumeration elements list.
BIAS : Bias Configuration
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : STATIC
Static
1 : ONEHALF
1/2 Bias
2 : ONETHIRD
1/3 Bias
3 : ONEFOURTH
1/4 Bias
End of enumeration elements list.
No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ASTATETOP : ASTATE top cnt
bits : 0 - 2 (3 bit)
access : read-write
FCPRESC : Frame Counter Prescaler
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : DIV1
every frame clock
1 : DIV2
every 2nd frame clock
2 : DIV4
every 4th frame clock
3 : DIV8
every 8th frame clock
End of enumeration elements list.
FCTOP : Frame Counter Top
bits : 18 - 23 (6 bit)
access : read-write
No Description
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLINKEN : Blink Enable
bits : 0 - 0 (1 bit)
access : read-write
BLANK : Blank Display
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Display is not blanked
1 : ENABLE
Display is blanked
End of enumeration elements list.
AEN : Animation Enable
bits : 2 - 2 (1 bit)
access : read-write
AREGASC : Animate Register A Shift Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : NOSHIFT
No Shift operation on Animation Register A
1 : SHIFTLEFT
Animation Register A is shifted left
2 : SHIFTRIGHT
Animation Register A is shifted right
End of enumeration elements list.
AREGBSC : Animate Register B Shift Control
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : NOSHIFT
No Shift operation on Animation Register B
1 : SHIFTLEFT
Animation Register B is shifted left
2 : SHIFTRIGHT
Animation Register B is shifted right
End of enumeration elements list.
ALOGSEL : Animate Logic Function Select
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : AND
AREGA and AREGB AND'ed
1 : OR
AREGA and AREGB OR'ed
End of enumeration elements list.
FCEN : Frame Counter Enable
bits : 8 - 8 (1 bit)
access : read-write
DISPLAYCNTEN : Display Counter Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable the display counter
1 : ENABLE
Enable the display counter
End of enumeration elements list.
ALOC : Animation Location
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SEG0TO7
Animation appears on segments 0 to 7
1 : SEG8TO15
Animation appears on segments 8 to 15
End of enumeration elements list.
No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ASTATE : Current Animation State
bits : 0 - 3 (4 bit)
access : read-only
BLINK : Blink State
bits : 8 - 8 (1 bit)
access : read-only
LOADBUSY : Load Synchronization is busy
bits : 11 - 11 (1 bit)
access : read-only
No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AREGA : Animation Register A Data
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AREGB : Animation Register B Data
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FC : Frame Counter
bits : 0 - 0 (1 bit)
access : read-write
DISPLAY : Display Update Event
bits : 1 - 1 (1 bit)
access : read-write
SYNCBUSYDONE : Synchronization is Done
bits : 2 - 2 (1 bit)
access : read-write
No Description
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FC : Frame Counter
bits : 0 - 0 (1 bit)
access : read-write
DISPLAY : Display Update Event
bits : 1 - 1 (1 bit)
access : read-write
SYNCBUSYDONE : Sync Busy Done
bits : 2 - 2 (1 bit)
access : read-write
No Description
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESISTOR : Resistor strength
bits : 0 - 3 (4 bit)
access : read-write
BUFDRV : Buffer Drive Strength
bits : 4 - 6 (3 bit)
access : read-write
BUFBIAS : Buffer Bias Setting
bits : 8 - 9 (2 bit)
access : read-write
MODE : Mode Setting
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : STEPDOWN
Use step down control with VLCD less than VDDX. Use VLCD[4:0] to control VLCD level, and use SPEED to adjust VLCD drive strength.
1 : CHARGEPUMP
Use the charge pump to pump VLCD above VDDX.
End of enumeration elements list.
VLCD : VLCD voltage level
bits : 16 - 20 (5 bit)
access : read-write
VDDXSEL : VDDX select
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DVDD
Connect charge pump to digital DVDD supply
1 : AVDD
Connect charge pump to analog AVDD supply
End of enumeration elements list.
LCDGATE : LCD Gate
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : UNGATE
LCD BIAS voltages driven onto pins.
1 : GATE
LCD BIAS MUX tristated at the pins.
End of enumeration elements list.
DMAMODE : DMA Mode
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : DMADISABLE
No DMA requests are generated
1 : DMAFC
DMA request on frame counter event. This will also start a DMA transfer during EM23.
2 : DMADISPLAY
DMA request on display counter event. This will also start a DMA transfer during EM23.
End of enumeration elements list.
No Description
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISPLAYDIV : Display Divider
bits : 0 - 9 (10 bit)
access : read-write
No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
1 : ENABLE
Enable
End of enumeration elements list.
DISABLING : Disablement busy status
bits : 1 - 1 (1 bit)
access : read-only
No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEGD0 : COM0 Segment Data Low
bits : 0 - 19 (20 bit)
access : read-write
No Description
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEGD1 : COM1 Segment Data Low
bits : 0 - 19 (20 bit)
access : read-write
No Description
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEGD2 : COM2 Segment Data Low
bits : 0 - 19 (20 bit)
access : read-write
No Description
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEGD3 : COM3 Segment Data Low
bits : 0 - 19 (20 bit)
access : read-write
No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software reset command
bits : 0 - 0 (1 bit)
access : write-only
RESETTING : Software reset busy status
bits : 1 - 1 (1 bit)
access : read-only
No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDCTRL : Update Data Control
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : REGULAR
The data transfer is controlled by SW. Transfer is performed as soon as possible on the next CTRL.PRESCALE clock
1 : FRAMESTART
Data is loaded continuously at every frame start
2 : FCEVENT
The data transfer is done at the next Frame Counter event
3 : DISPLAYEVENT
The data transfer is done at the next Display Counter event
End of enumeration elements list.
DSC : Direct Segment Control
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
DSC disable
1 : ENABLE
DSC enable
End of enumeration elements list.
WARMUPDLY : Warmup Delay
bits : 18 - 20 (3 bit)
access : read-write
Enumeration:
0 : WARMUP1
1mswarm up
1 : WARMUP31
31ms warm up
2 : WARMUP63
62ms warm up
3 : WARMUP125
125ms warm up
4 : WARMUP250
250ms warm up
5 : WARMUP500
500ms warm up
6 : WARMUP1000
1000ms warm up
7 : WARMUP2000
2000ms warm up
End of enumeration elements list.
PRESCALE : Presclae
bits : 24 - 30 (7 bit)
access : read-write
No Description
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTOLOAD : Auto Load
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : MANUAL
CLK_BUS register to CLK_PER register loads must be done manually with a write to CMD.LOAD.
1 : AUTO
CLK_BUS register to CLK_PER register loads will be started automatically after a write to the register in UPDATECTRL.LOADADDR is detected.
End of enumeration elements list.
LOADADDR : Load Address
bits : 13 - 16 (4 bit)
access : read-write
Enumeration:
0 : BACTRLWR
Starts synchronizing registers from CLK_BUS to CLK_PER after a write to BACTRL. Use with UPDATECTRL.AUTOLOAD
1 : AREGAWR
Starts synchronizing registers from CLK_BUS to CLK_PER after a write to AREGA. Use with UPDATECTRL.AUTOLOAD
2 : AREGBWR
Starts synchronizing registers from CLK_BUS to CLK_PER after a write to AREGB. Use with UPDATECTRL.AUTOLOAD
3 : SEGD0WR
Starts synchronizing registers from CLK_BUS to CLK_PER after a write to SEGD0. Use with UPDATECTRL.AUTOLOAD
4 : SEGD1WR
Starts synchronizing registers from CLK_BUS to CLK_PER after a write to SEGD1. Use with UPDATECTRL.AUTOLOAD
5 : SEGD2WR
Starts synchronizing registers from CLK_BUS to CLK_PER after a write to SEGD2. Use with UPDATECTRL.AUTOLOAD
6 : SEGD3WR
Starts synchronizing registers from CLK_BUS to CLK_PER after a write to SEGD3. Use with UPDATECTRL.AUTOLOAD
End of enumeration elements list.
No Description
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRDIV : Frame Rate Divider
bits : 0 - 8 (9 bit)
access : read-write
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