Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC0C byte (0x0)
mem_usage : registers
protection :
Module Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXMB : Number Of The Last Message Buffer
bits : 0 - 6 (7 bit)
access : read-write
IDAM : ID Acceptance Mode
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
Format A: One full ID (standard and extended) per ID Filter Table element.
#01 : 01
Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element.
#10 : 10
Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
#11 : 11
Format D: All frames rejected.
End of enumeration elements list.
FDEN : CAN FD operation enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#1 : 1
CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
#0 : 0
CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
End of enumeration elements list.
AEN : Abort Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Abort disabled.
#1 : 1
Abort enabled.
End of enumeration elements list.
LPRIOEN : Local Priority Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Local Priority disabled.
#1 : 1
Local Priority enabled.
End of enumeration elements list.
PNET_EN : Pretended Networking Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pretended Networking mode is disabled.
#1 : 1
Pretended Networking mode is enabled.
End of enumeration elements list.
DMA : DMA Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA feature for RX FIFO disabled.
#1 : 1
DMA feature for RX FIFO enabled.
End of enumeration elements list.
IRMQ : Individual Rx Masking And Queue Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY.
#1 : 1
Individual Rx masking and queue feature are enabled.
End of enumeration elements list.
SRXDIS : Self Reception Disable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Self reception enabled.
#1 : 1
Self reception disabled.
End of enumeration elements list.
LPMACK : Low-Power Mode Acknowledge
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
FlexCAN is not in a low-power mode.
#1 : 1
FlexCAN is in a low-power mode.
End of enumeration elements list.
WRNEN : Warning Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
#1 : 1
TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
End of enumeration elements list.
SUPV : Supervisor Mode
bits : 23 - 23 (1 bit)
access : read-write
FRZACK : Freeze Mode Acknowledge
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
FlexCAN not in Freeze mode, prescaler running.
#1 : 1
FlexCAN in Freeze mode, prescaler stopped.
End of enumeration elements list.
SOFTRST : Soft Reset
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset request.
#1 : 1
Resets the registers affected by soft reset.
End of enumeration elements list.
NOTRDY : FlexCAN Not Ready
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode.
End of enumeration elements list.
HALT : Halt FlexCAN
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Freeze mode request.
#1 : 1
Enters Freeze mode if the FRZ bit is asserted.
End of enumeration elements list.
RFEN : Rx FIFO Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rx FIFO not enabled.
#1 : 1
Rx FIFO enabled.
End of enumeration elements list.
FRZ : Freeze Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not enabled to enter Freeze mode.
#1 : 1
Enabled to enter Freeze mode.
End of enumeration elements list.
MDIS : Module Disable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable the FlexCAN module.
#1 : 1
Disable the FlexCAN module.
End of enumeration elements list.
Rx Mailboxes Global Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MG : Rx Mailboxes Global Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Embedded RAM
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Rx 14 Mask register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX14M : Rx Buffer 14 Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Embedded RAM
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Rx 15 Mask register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX15M : Rx Buffer 15 Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Embedded RAM
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Error Counter
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXERRCNT : Transmit Error Counter
bits : 0 - 7 (8 bit)
access : read-write
RXERRCNT : Receive Error Counter
bits : 8 - 15 (8 bit)
access : read-write
TXERRCNT_FAST : Transmit Error Counter for fast bits
bits : 16 - 23 (8 bit)
access : read-write
RXERRCNT_FAST : Receive Error Counter for fast bits
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Error and Status 1 register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERRINT : Error Interrupt
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
Indicates setting of any Error Bit in the Error and Status Register.
End of enumeration elements list.
BOFFINT : Bus Off Interrupt
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
FlexCAN module entered Bus Off state.
End of enumeration elements list.
RX : FlexCAN In Reception
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
FlexCAN is not receiving a message.
#1 : 1
FlexCAN is receiving a message.
End of enumeration elements list.
FLTCONF : Fault Confinement State
bits : 4 - 5 (2 bit)
access : read-only
Enumeration:
#00 : 00
Error Active
#01 : 01
Error Passive
#1x : 1x
Bus Off
End of enumeration elements list.
TX : FlexCAN In Transmission
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
FlexCAN is not transmitting a message.
#1 : 1
FlexCAN is transmitting a message.
End of enumeration elements list.
IDLE : IDLE
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
CAN bus is now IDLE.
End of enumeration elements list.
RXWRN : Rx Error Warning
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
RXERRCNT is greater than or equal to 96.
End of enumeration elements list.
TXWRN : TX Error Warning
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
TXERRCNT is greater than or equal to 96.
End of enumeration elements list.
STFERR : Stuffing Error
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
A Stuffing Error occurred since last read of this register.
End of enumeration elements list.
FRMERR : Form Error
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
A Form Error occurred since last read of this register.
End of enumeration elements list.
CRCERR : Cyclic Redundancy Check Error
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
A CRC error occurred since last read of this register.
End of enumeration elements list.
ACKERR : Acknowledge Error
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
An ACK error occurred since last read of this register.
End of enumeration elements list.
BIT0ERR : Bit0 Error
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
At least one bit sent as dominant is received as recessive.
End of enumeration elements list.
BIT1ERR : Bit1 Error
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
At least one bit sent as recessive is received as dominant.
End of enumeration elements list.
RWRNINT : Rx Warning Interrupt Flag
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
The Rx error counter transitioned from less than 96 to greater than or equal to 96.
End of enumeration elements list.
TWRNINT : Tx Warning Interrupt Flag
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
The Tx error counter transitioned from less than 96 to greater than or equal to 96.
End of enumeration elements list.
SYNCH : CAN Synchronization Status
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
FlexCAN is not synchronized to the CAN bus.
#1 : 1
FlexCAN is synchronized to the CAN bus.
End of enumeration elements list.
BOFFDONEINT : Bus Off Done Interrupt
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
FlexCAN module has completed Bus Off process.
End of enumeration elements list.
ERRINT_FAST : Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set.
End of enumeration elements list.
ERROVR : Error Overrun bit
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Overrun has not occurred.
#1 : 1
Overrun has occurred.
End of enumeration elements list.
STFERR_FAST : Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
A Stuffing Error occurred since last read of this register.
End of enumeration elements list.
FRMERR_FAST : Form Error in the Data Phase of CAN FD frames with the BRS bit set
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
A Form Error occurred since last read of this register.
End of enumeration elements list.
CRCERR_FAST : Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
A CRC error occurred since last read of this register.
End of enumeration elements list.
BIT0ERR_FAST : Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
At least one bit sent as dominant is received as recessive.
End of enumeration elements list.
BIT1ERR_FAST : Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
No such occurrence.
#1 : 1
At least one bit sent as recessive is received as dominant.
End of enumeration elements list.
Embedded RAM
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Masks 1 register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUF31TO0M : Buffer MB i Mask
bits : 0 - 31 (32 bit)
access : read-write
Interrupt Flags 1 register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUF0I : Buffer MB0 Interrupt Or Clear FIFO bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
#1 : 1
The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
End of enumeration elements list.
BUF4TO1I : Buffer MB i Interrupt Or reserved
bits : 1 - 4 (4 bit)
access : read-write
BUF5I : Buffer MB5 Interrupt Or Frames available in Rx FIFO
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
#1 : 1
MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.
End of enumeration elements list.
BUF6I : Buffer MB6 Interrupt Or Rx FIFO Warning
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
#1 : 1
MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
End of enumeration elements list.
BUF7I : Buffer MB7 Interrupt Or Rx FIFO Overflow
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
#1 : 1
MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
End of enumeration elements list.
BUF31TO8I : Buffer MBi Interrupt
bits : 8 - 31 (24 bit)
access : read-write
Control 2 register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDFLTDIS : Edge Filter Disable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge Filter is enabled.
#1 : 1
Edge Filter is disabled.
End of enumeration elements list.
ISOCANFDEN : ISO CAN FD Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
FlexCAN operates using the non-ISO CAN FD protocol.
#1 : 1
FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).
End of enumeration elements list.
PREXCEN : Protocol Exception Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Protocol Exception is disabled.
#1 : 1
Protocol Exception is enabled.
End of enumeration elements list.
TIMER_SRC : Timer Source
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Free Running Timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus.
#1 : 1
The Free Running Timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus, or a different value as required. See the device specific section for details about the external time tick.
End of enumeration elements list.
EACEN : Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
#1 : 1
Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply.
End of enumeration elements list.
RRS : Remote Request Storing
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Remote Response Frame is generated.
#1 : 1
Remote Request Frame is stored.
End of enumeration elements list.
MRP : Mailboxes Reception Priority
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Matching starts from Rx FIFO and continues on Mailboxes.
#1 : 1
Matching starts from Mailboxes and continues on Rx FIFO.
End of enumeration elements list.
TASD : Tx Arbitration Start Delay
bits : 19 - 23 (5 bit)
access : read-write
RFFN : Number Of Rx FIFO Filters
bits : 24 - 27 (4 bit)
access : read-write
BOFFDONEMSK : Bus Off Done Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus Off Done interrupt disabled.
#1 : 1
Bus Off Done interrupt enabled.
End of enumeration elements list.
ERRMSK_FAST : Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ERRINT_FAST Error interrupt disabled.
#1 : 1
ERRINT_FAST Error interrupt enabled.
End of enumeration elements list.
Error and Status 2 register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMB : Inactive Mailbox
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
#1 : 1
If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.
End of enumeration elements list.
VPS : Valid Priority Status
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
Contents of IMB and LPTM are invalid.
#1 : 1
Contents of IMB and LPTM are valid.
End of enumeration elements list.
LPTM : Lowest Priority Tx Mailbox
bits : 16 - 22 (7 bit)
access : read-only
Control 1 register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROPSEG : Propagation Segment
bits : 0 - 2 (3 bit)
access : read-write
LOM : Listen-Only Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Listen-Only mode is deactivated.
#1 : 1
FlexCAN module operates in Listen-Only mode.
End of enumeration elements list.
LBUF : Lowest Buffer Transmitted First
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Buffer with highest priority is transmitted first.
#1 : 1
Lowest number buffer is transmitted first.
End of enumeration elements list.
TSYN : Timer Sync
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer Sync feature disabled
#1 : 1
Timer Sync feature enabled
End of enumeration elements list.
BOFFREC : Bus Off Recovery
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Automatic recovering from Bus Off state enabled.
#1 : 1
Automatic recovering from Bus Off state disabled.
End of enumeration elements list.
SMP : CAN Bit Sampling
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Just one sample is used to determine the bit value.
#1 : 1
Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples a majority rule is used.
End of enumeration elements list.
RWRNMSK : Rx Warning Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rx Warning Interrupt disabled.
#1 : 1
Rx Warning Interrupt enabled.
End of enumeration elements list.
TWRNMSK : Tx Warning Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx Warning Interrupt disabled.
#1 : 1
Tx Warning Interrupt enabled.
End of enumeration elements list.
LPB : Loop Back Mode
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Loop Back disabled.
#1 : 1
Loop Back enabled.
End of enumeration elements list.
CLKSRC : CAN Engine Clock Source
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
#1 : 1
The CAN engine clock source is the peripheral clock.
End of enumeration elements list.
ERRMSK : Error Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Error interrupt disabled.
#1 : 1
Error interrupt enabled.
End of enumeration elements list.
BOFFMSK : Bus Off Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus Off interrupt disabled.
#1 : 1
Bus Off interrupt enabled.
End of enumeration elements list.
PSEG2 : Phase Segment 2
bits : 16 - 18 (3 bit)
access : read-write
PSEG1 : Phase Segment 1
bits : 19 - 21 (3 bit)
access : read-write
RJW : Resync Jump Width
bits : 22 - 23 (2 bit)
access : read-write
PRESDIV : Prescaler Division Factor
bits : 24 - 31 (8 bit)
access : read-write
CRC Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXCRC : Transmitted CRC value
bits : 0 - 14 (15 bit)
access : read-only
MBCRC : CRC Mailbox
bits : 16 - 22 (7 bit)
access : read-only
Rx FIFO Global Mask register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGM : Rx FIFO Global Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx FIFO Information Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IDHIT : Identifier Acceptance Filter Hit Indicator
bits : 0 - 8 (9 bit)
access : read-only
CAN Bit Timing Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPSEG2 : Extended Phase Segment 2
bits : 0 - 4 (5 bit)
access : read-write
EPSEG1 : Extended Phase Segment 1
bits : 5 - 9 (5 bit)
access : read-write
EPROPSEG : Extended Propagation Segment
bits : 10 - 15 (6 bit)
access : read-write
ERJW : Extended Resync Jump Width
bits : 16 - 20 (5 bit)
access : read-write
EPRESDIV : Extended Prescaler Division Factor
bits : 21 - 30 (10 bit)
access : read-write
BTF : Bit Timing Format Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Extended bit time definitions disabled.
#1 : 1
Extended bit time definitions enabled.
End of enumeration elements list.
Free Running Timer
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER : Timer Value
bits : 0 - 15 (16 bit)
access : read-write
Embedded RAM
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x88C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x89C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Embedded RAM
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Rx Individual Mask Registers
address_offset : 0x8FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MI : Individual Mask Bits
bits : 0 - 31 (32 bit)
access : read-write
Embedded RAM
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Pretended Networking Control 1 Register
address_offset : 0xB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCS : Filtering Combination Selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Message ID filtering only
#01 : 01
Message ID filtering and payload filtering
#10 : 10
Message ID filtering occurring a specified number of times.
#11 : 11
Message ID filtering and payload filtering a specified number of times
End of enumeration elements list.
IDFS : ID Filtering Selection
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Match upon a ID contents against an exact target value
#01 : 01
Match upon a ID value greater than or equal to a specified target value
#10 : 10
Match upon a ID value smaller than or equal to a specified target value
#11 : 11
Match upon a ID value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit
End of enumeration elements list.
PLFS : Payload Filtering Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Match upon a payload contents against an exact target value
#01 : 01
Match upon a payload value greater than or equal to a specified target value
#10 : 10
Match upon a payload value smaller than or equal to a specified target value
#11 : 11
Match upon a payload value inside a range, greater than or equal to a specified lower limit and smaller than or equal a specified upper limit
End of enumeration elements list.
NMATCH : Number of Messages Matching the Same Filtering Criteria
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
#1 : 00000001
Received message must match the predefined filtering criteria for ID and/or PL once before generating a wake up event.
#10 : 00000010
Received message must match the predefined filtering criteria for ID and/or PL twice before generating a wake up event.
#11111111 : 11111111
Received message must match the predefined filtering criteria for ID and/or PL 255 times before generating a wake up event.
End of enumeration elements list.
WUMF_MSK : Wake Up by Match Flag Mask Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake up match event is disabled
#1 : 1
Wake up match event is enabled
End of enumeration elements list.
WTOF_MSK : Wake Up by Timeout Flag Mask Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timeout wake up event is disabled
#1 : 1
Timeout wake up event is enabled
End of enumeration elements list.
Pretended Networking Control 2 Register
address_offset : 0xB04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHTO : Timeout for No Message Matching the Filtering Criteria
bits : 0 - 15 (16 bit)
access : read-write
Pretended Networking Wake Up Match Register
address_offset : 0xB08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCOUNTER : Number of Matches while in Pretended Networking
bits : 8 - 15 (8 bit)
access : read-only
WUMF : Wake Up by Match Flag Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No wake up by match event detected
#1 : 1
Wake up by match event detected
End of enumeration elements list.
WTOF : Wake Up by Timeout Flag Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No wake up by timeout event detected
#1 : 1
Wake up by timeout event detected
End of enumeration elements list.
Pretended Networking ID Filter 1 Register
address_offset : 0xB0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLT_ID1 : ID Filter 1 for Pretended Networking filtering
bits : 0 - 28 (29 bit)
access : read-write
FLT_RTR : Remote Transmission Request Filter
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reject remote frame (accept data frame)
#1 : 1
Accept remote frame
End of enumeration elements list.
FLT_IDE : ID Extended Filter
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Accept standard frame format
#1 : 1
Accept extended frame format
End of enumeration elements list.
Pretended Networking DLC Filter Register
address_offset : 0xB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLT_DLC_HI : Upper Limit for Length of Data Bytes Filter
bits : 0 - 3 (4 bit)
access : read-write
FLT_DLC_LO : Lower Limit for Length of Data Bytes Filter
bits : 16 - 19 (4 bit)
access : read-write
Pretended Networking Payload Low Filter 1 Register
address_offset : 0xB14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data_byte_3 : Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 3.
bits : 0 - 7 (8 bit)
access : read-write
Data_byte_2 : Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 2.
bits : 8 - 15 (8 bit)
access : read-write
Data_byte_1 : Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 1.
bits : 16 - 23 (8 bit)
access : read-write
Data_byte_0 : Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 0.
bits : 24 - 31 (8 bit)
access : read-write
Pretended Networking Payload High Filter 1 Register
address_offset : 0xB18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data_byte_7 : Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 7.
bits : 0 - 7 (8 bit)
access : read-write
Data_byte_6 : Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 6.
bits : 8 - 15 (8 bit)
access : read-write
Data_byte_5 : Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 5.
bits : 16 - 23 (8 bit)
access : read-write
Data_byte_4 : Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 4.
bits : 24 - 31 (8 bit)
access : read-write
Pretended Networking ID Filter 2 Register / ID Mask Register
address_offset : 0xB1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLT_ID2_IDMASK : ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering
bits : 0 - 28 (29 bit)
access : read-write
RTR_MSK : Remote Transmission Request Mask Bit
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding bit in the filter is don't care
#1 : 1
The corresponding bit in the filter is checked
End of enumeration elements list.
IDE_MSK : ID Extended Mask Bit
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding bit in the filter is don't care
#1 : 1
The corresponding bit in the filter is checked
End of enumeration elements list.
Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data_byte_3 : Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 3.
bits : 0 - 7 (8 bit)
access : read-write
Data_byte_2 : Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 2.
bits : 8 - 15 (8 bit)
access : read-write
Data_byte_1 : Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 1.
bits : 16 - 23 (8 bit)
access : read-write
Data_byte_0 : Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 0.
bits : 24 - 31 (8 bit)
access : read-write
Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register
address_offset : 0xB24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data_byte_7 : Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 7.
bits : 0 - 7 (8 bit)
access : read-write
Data_byte_6 : Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 6.
bits : 8 - 15 (8 bit)
access : read-write
Data_byte_5 : Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 5.
bits : 16 - 23 (8 bit)
access : read-write
Data_byte_4 : Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 4.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Wake Up Message Buffer Register for C/S
address_offset : 0xB40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DLC : Length of Data in Bytes
bits : 16 - 19 (4 bit)
access : read-only
RTR : Remote Transmission Request Bit
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
Frame is data one (not remote)
#1 : 1
Frame is a remote one
End of enumeration elements list.
IDE : ID Extended Bit
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
#0 : 0
Frame format is standard
#1 : 1
Frame format is extended
End of enumeration elements list.
SRR : Substitute Remote Request
bits : 22 - 22 (1 bit)
access : read-only
Wake Up Message Buffer Register for ID
address_offset : 0xB44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : Received ID under Pretended Networking mode
bits : 0 - 28 (29 bit)
access : read-only
Wake Up Message Buffer Register for Data 0-3
address_offset : 0xB48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Data_byte_3 : Received payload corresponding to the data byte 3 under Pretended Networking mode
bits : 0 - 7 (8 bit)
access : read-only
Data_byte_2 : Received payload corresponding to the data byte 2 under Pretended Networking mode
bits : 8 - 15 (8 bit)
access : read-only
Data_byte_1 : Received payload corresponding to the data byte 1 under Pretended Networking mode
bits : 16 - 23 (8 bit)
access : read-only
Data_byte_0 : Received payload corresponding to the data byte 0 under Pretended Networking mode
bits : 24 - 31 (8 bit)
access : read-only
Wake Up Message Buffer Register Data 4-7
address_offset : 0xB4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Data_byte_7 : Received payload corresponding to the data byte 7 under Pretended Networking mode
bits : 0 - 7 (8 bit)
access : read-only
Data_byte_6 : Received payload corresponding to the data byte 6 under Pretended Networking mode
bits : 8 - 15 (8 bit)
access : read-only
Data_byte_5 : Received payload corresponding to the data byte 5 under Pretended Networking mode
bits : 16 - 23 (8 bit)
access : read-only
Data_byte_4 : Received payload corresponding to the data byte 4 under Pretended Networking mode
bits : 24 - 31 (8 bit)
access : read-only
Wake Up Message Buffer Register for C/S
address_offset : 0xB50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DLC : Length of Data in Bytes
bits : 16 - 19 (4 bit)
access : read-only
RTR : Remote Transmission Request Bit
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
Frame is data one (not remote)
#1 : 1
Frame is a remote one
End of enumeration elements list.
IDE : ID Extended Bit
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
#0 : 0
Frame format is standard
#1 : 1
Frame format is extended
End of enumeration elements list.
SRR : Substitute Remote Request
bits : 22 - 22 (1 bit)
access : read-only
Wake Up Message Buffer Register for ID
address_offset : 0xB54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : Received ID under Pretended Networking mode
bits : 0 - 28 (29 bit)
access : read-only
Wake Up Message Buffer Register for Data 0-3
address_offset : 0xB58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Data_byte_3 : Received payload corresponding to the data byte 3 under Pretended Networking mode
bits : 0 - 7 (8 bit)
access : read-only
Data_byte_2 : Received payload corresponding to the data byte 2 under Pretended Networking mode
bits : 8 - 15 (8 bit)
access : read-only
Data_byte_1 : Received payload corresponding to the data byte 1 under Pretended Networking mode
bits : 16 - 23 (8 bit)
access : read-only
Data_byte_0 : Received payload corresponding to the data byte 0 under Pretended Networking mode
bits : 24 - 31 (8 bit)
access : read-only
Wake Up Message Buffer Register Data 4-7
address_offset : 0xB5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Data_byte_7 : Received payload corresponding to the data byte 7 under Pretended Networking mode
bits : 0 - 7 (8 bit)
access : read-only
Data_byte_6 : Received payload corresponding to the data byte 6 under Pretended Networking mode
bits : 8 - 15 (8 bit)
access : read-only
Data_byte_5 : Received payload corresponding to the data byte 5 under Pretended Networking mode
bits : 16 - 23 (8 bit)
access : read-only
Data_byte_4 : Received payload corresponding to the data byte 4 under Pretended Networking mode
bits : 24 - 31 (8 bit)
access : read-only
Wake Up Message Buffer Register for C/S
address_offset : 0xB60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DLC : Length of Data in Bytes
bits : 16 - 19 (4 bit)
access : read-only
RTR : Remote Transmission Request Bit
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
Frame is data one (not remote)
#1 : 1
Frame is a remote one
End of enumeration elements list.
IDE : ID Extended Bit
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
#0 : 0
Frame format is standard
#1 : 1
Frame format is extended
End of enumeration elements list.
SRR : Substitute Remote Request
bits : 22 - 22 (1 bit)
access : read-only
Wake Up Message Buffer Register for ID
address_offset : 0xB64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : Received ID under Pretended Networking mode
bits : 0 - 28 (29 bit)
access : read-only
Wake Up Message Buffer Register for Data 0-3
address_offset : 0xB68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Data_byte_3 : Received payload corresponding to the data byte 3 under Pretended Networking mode
bits : 0 - 7 (8 bit)
access : read-only
Data_byte_2 : Received payload corresponding to the data byte 2 under Pretended Networking mode
bits : 8 - 15 (8 bit)
access : read-only
Data_byte_1 : Received payload corresponding to the data byte 1 under Pretended Networking mode
bits : 16 - 23 (8 bit)
access : read-only
Data_byte_0 : Received payload corresponding to the data byte 0 under Pretended Networking mode
bits : 24 - 31 (8 bit)
access : read-only
Wake Up Message Buffer Register Data 4-7
address_offset : 0xB6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Data_byte_7 : Received payload corresponding to the data byte 7 under Pretended Networking mode
bits : 0 - 7 (8 bit)
access : read-only
Data_byte_6 : Received payload corresponding to the data byte 6 under Pretended Networking mode
bits : 8 - 15 (8 bit)
access : read-only
Data_byte_5 : Received payload corresponding to the data byte 5 under Pretended Networking mode
bits : 16 - 23 (8 bit)
access : read-only
Data_byte_4 : Received payload corresponding to the data byte 4 under Pretended Networking mode
bits : 24 - 31 (8 bit)
access : read-only
Wake Up Message Buffer Register for C/S
address_offset : 0xB70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DLC : Length of Data in Bytes
bits : 16 - 19 (4 bit)
access : read-only
RTR : Remote Transmission Request Bit
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
Frame is data one (not remote)
#1 : 1
Frame is a remote one
End of enumeration elements list.
IDE : ID Extended Bit
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
#0 : 0
Frame format is standard
#1 : 1
Frame format is extended
End of enumeration elements list.
SRR : Substitute Remote Request
bits : 22 - 22 (1 bit)
access : read-only
Wake Up Message Buffer Register for ID
address_offset : 0xB74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : Received ID under Pretended Networking mode
bits : 0 - 28 (29 bit)
access : read-only
Wake Up Message Buffer Register for Data 0-3
address_offset : 0xB78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Data_byte_3 : Received payload corresponding to the data byte 3 under Pretended Networking mode
bits : 0 - 7 (8 bit)
access : read-only
Data_byte_2 : Received payload corresponding to the data byte 2 under Pretended Networking mode
bits : 8 - 15 (8 bit)
access : read-only
Data_byte_1 : Received payload corresponding to the data byte 1 under Pretended Networking mode
bits : 16 - 23 (8 bit)
access : read-only
Data_byte_0 : Received payload corresponding to the data byte 0 under Pretended Networking mode
bits : 24 - 31 (8 bit)
access : read-only
Wake Up Message Buffer Register Data 4-7
address_offset : 0xB7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Data_byte_7 : Received payload corresponding to the data byte 7 under Pretended Networking mode
bits : 0 - 7 (8 bit)
access : read-only
Data_byte_6 : Received payload corresponding to the data byte 6 under Pretended Networking mode
bits : 8 - 15 (8 bit)
access : read-only
Data_byte_5 : Received payload corresponding to the data byte 5 under Pretended Networking mode
bits : 16 - 23 (8 bit)
access : read-only
Data_byte_4 : Received payload corresponding to the data byte 4 under Pretended Networking mode
bits : 24 - 31 (8 bit)
access : read-only
Embedded RAM
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
CAN FD Control Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDCVAL : Transceiver Delay Compensation Value
bits : 0 - 5 (6 bit)
access : read-only
TDCOFF : Transceiver Delay Compensation Offset
bits : 8 - 12 (5 bit)
access : read-write
TDCFAIL : Transceiver Delay Compensation Fail
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Measured loop delay is in range.
#1 : 1
Measured loop delay is out of range.
End of enumeration elements list.
TDCEN : Transceiver Delay Compensation Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDC is disabled
#1 : 1
TDC is enabled
End of enumeration elements list.
MBDSR0 : Message Buffer Data Size for Region 0
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
Selects 8 bytes per Message Buffer.
#01 : 01
Selects 16 bytes per Message Buffer.
#10 : 10
Selects 32 bytes per Message Buffer.
#11 : 11
Selects 64 bytes per Message Buffer.
End of enumeration elements list.
FDRATE : Bit Rate Switch Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
#1 : 1
Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
End of enumeration elements list.
CAN FD Bit Timing Register
address_offset : 0xC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPSEG2 : Fast Phase Segment 2
bits : 0 - 2 (3 bit)
access : read-write
FPSEG1 : Fast Phase Segment 1
bits : 5 - 7 (3 bit)
access : read-write
FPROPSEG : Fast Propagation Segment
bits : 10 - 14 (5 bit)
access : read-write
FRJW : Fast Resync Jump Width
bits : 16 - 18 (3 bit)
access : read-write
FPRESDIV : Fast Prescaler Division Factor
bits : 20 - 29 (10 bit)
access : read-write
CAN FD CRC Register
address_offset : 0xC08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FD_TXCRC : Extended Transmitted CRC value
bits : 0 - 20 (21 bit)
access : read-only
FD_MBCRC : CRC Mailbox Number for FD_TXCRC
bits : 24 - 30 (7 bit)
access : read-only
Embedded RAM
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
Embedded RAM
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE_3 : Data byte 3 of Rx/Tx frame.
bits : 0 - 7 (8 bit)
access : read-write
DATA_BYTE_2 : Data byte 2 of Rx/Tx frame.
bits : 8 - 15 (8 bit)
access : read-write
DATA_BYTE_1 : Data byte 1 of Rx/Tx frame.
bits : 16 - 23 (8 bit)
access : read-write
DATA_BYTE_0 : Data byte 0 of Rx/Tx frame.
bits : 24 - 31 (8 bit)
access : read-write
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