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SYSCFG_S

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

CHIPREVHW

CHIPREV

CTRL

DMEM0RETNCTRL

CFGSYSTIC

RAMBIASCONF

IPVERSION

ICACHERAMRETNCTRL

DMEM0PORTMAPSEL

ROOTDATA0

ROOTDATA1

ROOTLOCKSTATUS

ROOTSESWVERSION

IF

IEN


CHIPREVHW

Read to get the hard-wired chip revision.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIPREVHW CHIPREVHW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAJOR FAMILY MINOR

MAJOR : Hardwired Chip Revision Major value
bits : 0 - 5 (6 bit)
access : read-write

FAMILY : Hardwired Chip Family value
bits : 6 - 11 (6 bit)
access : read-write

MINOR : Hardwired Chip Revision Minor value
bits : 12 - 19 (8 bit)
access : read-write


CHIPREV

Read to get the chip revision programmed by feature configuration.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIPREV CHIPREV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAJOR FAMILY MINOR

MAJOR : Chip Revision Major value
bits : 0 - 5 (6 bit)
access : read-write

FAMILY : Chip Family value
bits : 6 - 11 (6 bit)
access : read-write

MINOR : Chip Revision Minor value
bits : 12 - 19 (8 bit)
access : read-write


CTRL

Configure to provide general RAM configuration.
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRFAULTEN CLKDISFAULTEN RAMECCERRFAULTEN

ADDRFAULTEN : Invalid Address Bus Fault Response Enabl
bits : 0 - 0 (1 bit)
access : read-write

CLKDISFAULTEN : Disabled Clkbus Bus Fault Enable
bits : 1 - 1 (1 bit)
access : read-write

RAMECCERRFAULTEN : Two bit ECC error bus fault response ena
bits : 5 - 5 (1 bit)
access : read-write


DMEM0RETNCTRL

Configure to provide general RAM retention configuration.
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMEM0RETNCTRL DMEM0RETNCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMRETNCTRL

RAMRETNCTRL : DMEM0 blockset retention control
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : ALLON

None of the RAM blocks powered down

4 : BLK3

Power down RAM block 3 (address range 0x2000C000-0x20010000)

6 : BLK2TO3

Power down RAM blocks 3 and above (address range 0x20008000-0x20010000)

7 : BLK1TO3

Power down RAM blocks 1 and above (address range 0x20004000-0x20010000)

End of enumeration elements list.


CFGSYSTIC

Configure the source of the system tick for the M33.
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGSYSTIC CFGSYSTIC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSTICEXTCLKEN

SYSTICEXTCLKEN : SysTick External Clock Enable
bits : 0 - 0 (1 bit)
access : read-write


RAMBIASCONF

Configure RAM bias configure bits.
address_offset : 0x30C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAMBIASCONF RAMBIASCONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMBIASCTRL

RAMBIASCTRL : RAM Bias Control
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : No

None

1 : VSB100

Voltage Source Bias 100mV

2 : VSB200

Voltage Source Bias 200mV

4 : VSB300

Voltage Source Bias 300mV

8 : VSB400

Voltage Source Bias 400mV

End of enumeration elements list.


IPVERSION

No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : New BitField
bits : 0 - 31 (32 bit)
access : read-only


ICACHERAMRETNCTRL

Configure Host ICACHERAM retention configuration.
address_offset : 0x418 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACHERAMRETNCTRL ICACHERAMRETNCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMRETNCTRL

RAMRETNCTRL : ICACHERAM Retention control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : ALLON

None of the Host ICACHE RAM blocks powered down

1 : ALLOFF

Power down all Host ICACHE RAM blocks

End of enumeration elements list.


DMEM0PORTMAPSEL

Configure DMEM0 port remap selection.
address_offset : 0x41C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMEM0PORTMAPSEL DMEM0PORTMAPSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDMAPORTSEL SRWAESPORTSEL AHBSRWPORTSEL SRWECA0PORTSEL SRWECA1PORTSEL

LDMAPORTSEL : LDMA portmap selection
bits : 0 - 0 (1 bit)
access : read-write

SRWAESPORTSEL : SRWAES portmap selection
bits : 1 - 1 (1 bit)
access : read-write

AHBSRWPORTSEL : AHBSRW portmap selection
bits : 2 - 2 (1 bit)
access : read-write

SRWECA0PORTSEL : SRWECA0 portmap selection
bits : 3 - 3 (1 bit)
access : read-write

SRWECA1PORTSEL : SRWECA1 portmap selection
bits : 4 - 4 (1 bit)
access : read-write


ROOTDATA0

Generic data space for user to pass to root, e.g., address of struct in mem
address_offset : 0x600 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROOTDATA0 ROOTDATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 31 (32 bit)
access : read-write


ROOTDATA1

Generic data space for user to pass to root, e.g., address of struct in mem
address_offset : 0x604 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROOTDATA1 ROOTDATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 31 (32 bit)
access : read-write


ROOTLOCKSTATUS

This register returns the status of the SE managed locks.
address_offset : 0x608 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ROOTLOCKSTATUS ROOTLOCKSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSLOCK REGLOCK MFRLOCK ROOTDBGLOCK USERDBGAPLOCK USERDBGLOCK USERNIDLOCK USERSPIDLOCK USERSPNIDLOCK EFUSEUNLOCKED

BUSLOCK : Bus Lock
bits : 0 - 0 (1 bit)
access : read-only

REGLOCK : Register Lock
bits : 1 - 1 (1 bit)
access : read-only

MFRLOCK : Manufacture Lock
bits : 2 - 2 (1 bit)
access : read-only

ROOTDBGLOCK : Root Debug Lock
bits : 8 - 8 (1 bit)
access : read-only

USERDBGAPLOCK : User Debug Access Port Lock
bits : 16 - 16 (1 bit)
access : read-only

USERDBGLOCK : User Invasive Debug Lock
bits : 17 - 17 (1 bit)
access : read-only

USERNIDLOCK : User Non-invasive Debug Lock
bits : 18 - 18 (1 bit)
access : read-only

USERSPIDLOCK : User Secure Invasive Debug Lock
bits : 19 - 19 (1 bit)
access : read-only

USERSPNIDLOCK : User Secure Non-invasive Debug Lock
bits : 20 - 20 (1 bit)
access : read-only

EFUSEUNLOCKED : E-Fuse Unlocked
bits : 31 - 31 (1 bit)
access : read-only


ROOTSESWVERSION

SE Software version
address_offset : 0x60C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROOTSESWVERSION ROOTSESWVERSION read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWVERSION

SWVERSION : SW Version
bits : 0 - 31 (32 bit)
access : read-write


IF

Read to get system status.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW0 SW1 SW2 SW3 FPIOC FPDZC FPUFC FPOFC FPIDC FPIXC SEQRAMERR1B SEQRAMERR2B FRCRAMERR1B FRCRAMERR2B

SW0 : Software Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

SW1 : Software Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write

SW2 : Software Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write

SW3 : Software Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write

FPIOC : FPU Invalid Operation interrupt flag
bits : 8 - 8 (1 bit)
access : read-write

FPDZC : FPU Divide by zero interrupt flag
bits : 9 - 9 (1 bit)
access : read-write

FPUFC : FPU Underflow interrupt flag
bits : 10 - 10 (1 bit)
access : read-write

FPOFC : FPU Overflow interrupt flag
bits : 11 - 11 (1 bit)
access : read-write

FPIDC : FPU Input denormal interrupt flag
bits : 12 - 12 (1 bit)
access : read-write

FPIXC : FPU Inexact interrupt flag
bits : 13 - 13 (1 bit)
access : read-write

SEQRAMERR1B : SEQRAM Error 1-bit Interrupt Flag
bits : 24 - 24 (1 bit)
access : read-write

SEQRAMERR2B : SEQRAM Error 2-bit Interrupt Flag
bits : 25 - 25 (1 bit)
access : read-write

FRCRAMERR1B : FRCRAM Error 1-bit Interrupt Flag
bits : 28 - 28 (1 bit)
access : read-write

FRCRAMERR2B : FRCRAM Error 2-bit Interrupt Flag
bits : 29 - 29 (1 bit)
access : read-write


IEN

Write to enable interrupts.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW0 SW1 SW2 SW3 FPIOC FPDZC FPUFC FPOFC FPIDC FPIXC SEQRAMERR1B SEQRAMERR2B FRCRAMERR1B FRCRAMERR2B

SW0 : Software Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

SW1 : Software Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

SW2 : Software Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

SW3 : Software Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

FPIOC : FPU Invalid Operation Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

FPDZC : FPU Divide by zero Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

FPUFC : FPU Underflow Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

FPOFC : FPU Overflow Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

FPIDC : FPU Input denormal Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

FPIXC : FPU Inexact Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write

SEQRAMERR1B : SEQRAM Error 1-bit Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write

SEQRAMERR2B : SEQRAM Error 2-bit Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-write

FRCRAMERR1B : FRCRAM Error 1-bit Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-write

FRCRAMERR2B : FRCRAM Error 2-bit Interrupt Enable
bits : 29 - 29 (1 bit)
access : read-write



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