Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP VERSION
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACT : PDM is active
bits : 0 - 0 (1 bit)
access : read-only
FULL : FIFO FULL Status
bits : 4 - 4 (1 bit)
access : read-only
EMPTY : FIFO EMPTY Status
bits : 5 - 5 (1 bit)
access : read-only
FIFOCNT : FIFO CNT
bits : 8 - 10 (3 bit)
access : read-only
No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORDER : Filter order
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SECOND
Second order filter.
1 : THIRD
Third order filter.
2 : FOURTH
Fourth order filter.
3 : FIFTH
Fifth order filter.
End of enumeration elements list.
NUMCH : Number of Channels
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ONE
One channel.
1 : TWO
Two channels.
End of enumeration elements list.
DATAFORMAT : Filter output format
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : RIGHT16
Right aligned 16-bit, left bits are sign extended.
1 : DOUBLE16
Pack two 16-bit samples into one 32-bit word.
2 : RIGHT24
Right aligned 24bit, left bits are sign extended.
3 : FULL32BIT
32 bit data.
4 : LEFT16
Left aligned 16-bit, right bits are zeros.
5 : LEFT24
Left aligned 24-bit, right bits are zeros.
6 : RAW32BIT
RAW 32 bit data from Integrator.
End of enumeration elements list.
FIFODVL : Data Valid level in FIFO
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ONE
Atleast one word.
1 : TWO
Two words.
2 : THREE
Three words.
3 : FOUR
Four words.
End of enumeration elements list.
STEREOMODECH01 : Stereo mode CH01
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
No Stereo mode.
1 : CH01ENABLE
CH0 and CH1 in Stereo mode.
End of enumeration elements list.
CH0CLKPOL : CH0 CLK Polarity
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Input data clocked on rising clock edge.
1 : INVERT
Input data clocked on falling clock edge.
End of enumeration elements list.
CH1CLKPOL : CH1 CLK Polarity
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Input data clocked on rising clock edge.
1 : INVERT
Input data clocked on falling clock edge.
End of enumeration elements list.
No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : Prescalar Setting for PDM sample
bits : 0 - 9 (10 bit)
access : read-write
DLYMUXSEL : Data delay buffer mux selection
bits : 24 - 25 (2 bit)
access : read-write
No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : PDM received data
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : PDM enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable module
1 : ENABLE
Enable module
End of enumeration elements list.
No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DV : Data Valid Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
DVL : Data Valid Level Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write
OF : FIFO Overflow Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write
UF : FIFO Undeflow Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write
No Description
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DV : Data Valid Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
DVL : Data Valid Level Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
OF : FIFO Overflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
UF : FIFO Undeflow Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
No Description
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYNCBUSY : sync busy
bits : 0 - 0 (1 bit)
access : read-only
FIFOFLBUSY : FIFO Flush Sync busy
bits : 3 - 3 (1 bit)
access : read-only
No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAIN : Selects Gain factor of DCF
bits : 0 - 4 (5 bit)
access : read-write
DSR : Down sampling rate of Decimation filter
bits : 8 - 19 (12 bit)
access : read-write
No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
START : Start DCF
bits : 0 - 0 (1 bit)
access : write-only
STOP : Stop DCF
bits : 4 - 4 (1 bit)
access : write-only
CLEAR : Clear DCF
bits : 8 - 8 (1 bit)
access : write-only
FIFOFL : FIFO Flush
bits : 16 - 16 (1 bit)
access : write-only
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