\n

USB_OTG_HS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

OTG_HS_HCFG

OTG_HS_HPTXSTS

OTG_HS_HCCHAR0

OTG_HS_HCSPLT0

OTG_HS_HCINT0

OTG_HS_HCINTMSK0

OTG_HS_HCTSIZ0

OTG_HS_HCDMA0

OTG_HS_HCCHAR1

OTG_HS_HCSPLT1

OTG_HS_HCINT1

OTG_HS_HCINTMSK1

OTG_HS_HCTSIZ1

OTG_HS_HCDMA1

OTG_HS_HAINT

OTG_HS_HCCHAR2

OTG_HS_HCSPLT2

OTG_HS_HCINT2

OTG_HS_HCINTMSK2

OTG_HS_HCTSIZ2

OTG_HS_HCDMA2

OTG_HS_HCCHAR3

OTG_HS_HCSPLT3

OTG_HS_HCINT3

OTG_HS_HCINTMSK3

OTG_HS_HCTSIZ3

OTG_HS_HCDMA3

OTG_HS_HAINTMSK

OTG_HS_HCCHAR4

OTG_HS_HCSPLT4

OTG_HS_HCINT4

OTG_HS_HCINTMSK4

OTG_HS_HCTSIZ4

OTG_HS_HCDMA4

OTG_HS_HCCHAR5

OTG_HS_HCSPLT5

OTG_HS_HCINT5

OTG_HS_HCINTMSK5

OTG_HS_HCTSIZ5

OTG_HS_HCDMA5

OTG_HS_HCCHAR6

OTG_HS_HCSPLT6

OTG_HS_HCINT6

OTG_HS_HCINTMSK6

OTG_HS_HCTSIZ6

OTG_HS_HCDMA6

OTG_HS_HCCHAR7

OTG_HS_HCSPLT7

OTG_HS_HCINT7

OTG_HS_HCINTMSK7

OTG_HS_HCTSIZ7

OTG_HS_HCDMA7

OTG_HS_HCCHAR8

OTG_HS_HCSPLT8

OTG_HS_HCINT8

OTG_HS_HCINTMSK8

OTG_HS_HCTSIZ8

OTG_HS_HCDMA8

OTG_HS_HCCHAR9

OTG_HS_HCSPLT9

OTG_HS_HCINT9

OTG_HS_HCINTMSK9

OTG_HS_HCTSIZ9

OTG_HS_HCDMA9

OTG_HS_HCCHAR10

OTG_HS_HCSPLT10

OTG_HS_HCINT10

OTG_HS_HCINTMSK10

OTG_HS_HCTSIZ10

OTG_HS_HCDMA10

OTG_HS_HCCHAR11

OTG_HS_HCSPLT11

OTG_HS_HCINT11

OTG_HS_HCINTMSK11

OTG_HS_HCTSIZ11

OTG_HS_HCDMA11

OTG_HS_HFIR

OTG_HS_HPRT

OTG_HS_HFNUM


OTG_HS_HCFG

OTG_HS host configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCFG OTG_HS_HCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSLSPCS FSLSS

FSLSPCS : FS/LS PHY clock select
bits : 0 - 1 (2 bit)
access : read-write

FSLSS : FS- and LS-only support
bits : 2 - 2 (1 bit)
access : read-only


OTG_HS_HPTXSTS

OTG_HS_Host periodic transmit FIFO/queue status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HPTXSTS OTG_HS_HPTXSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTXFSAVL PTXQSAV PTXQTOP

PTXFSAVL : Periodic transmit data FIFO space available
bits : 0 - 15 (16 bit)
access : read-write

PTXQSAV : Periodic transmit request queue space available
bits : 16 - 23 (8 bit)
access : read-only

PTXQTOP : Top of the periodic transmit request queue
bits : 24 - 31 (8 bit)
access : read-only


OTG_HS_HCCHAR0

OTG_HS host channel-0 characteristics register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCCHAR0 OTG_HS_HCCHAR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MC DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


OTG_HS_HCSPLT0

OTG_HS host channel-0 split control register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCSPLT0 OTG_HS_HCSPLT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPLSPLT SPLITEN

PRTADDR : Port address
bits : 0 - 6 (7 bit)

HUBADDR : Hub address
bits : 7 - 13 (7 bit)

XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)

COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)

SPLITEN : Split enable
bits : 31 - 31 (1 bit)


OTG_HS_HCINT0

OTG_HS host channel-11 interrupt register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINT0 OTG_HS_HCINT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH AHBERR STALL NAK ACK NYET TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : Response received interrupt
bits : 6 - 6 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


OTG_HS_HCINTMSK0

OTG_HS host channel-11 interrupt mask register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINTMSK0 OTG_HS_HCINTMSK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM AHBERR STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


OTG_HS_HCTSIZ0

OTG_HS host channel-11 transfer size register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCTSIZ0 OTG_HS_HCTSIZ0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


OTG_HS_HCDMA0

OTG_HS host channel-0 DMA address register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCDMA0 OTG_HS_HCDMA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_HCCHAR1

OTG_HS host channel-1 characteristics register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCCHAR1 OTG_HS_HCCHAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MC DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


OTG_HS_HCSPLT1

OTG_HS host channel-1 split control register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCSPLT1 OTG_HS_HCSPLT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPLSPLT SPLITEN

PRTADDR : Port address
bits : 0 - 6 (7 bit)

HUBADDR : Hub address
bits : 7 - 13 (7 bit)

XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)

COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)

SPLITEN : Split enable
bits : 31 - 31 (1 bit)


OTG_HS_HCINT1

OTG_HS host channel-1 interrupt register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINT1 OTG_HS_HCINT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH AHBERR STALL NAK ACK NYET TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : Response received interrupt
bits : 6 - 6 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


OTG_HS_HCINTMSK1

OTG_HS host channel-1 interrupt mask register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINTMSK1 OTG_HS_HCINTMSK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM AHBERR STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


OTG_HS_HCTSIZ1

OTG_HS host channel-1 transfer size register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCTSIZ1 OTG_HS_HCTSIZ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


OTG_HS_HCDMA1

OTG_HS host channel-1 DMA address register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCDMA1 OTG_HS_HCDMA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_HAINT

OTG_HS Host all channels interrupt register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HAINT OTG_HS_HAINT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAINT

HAINT : Channel interrupts
bits : 0 - 15 (16 bit)


OTG_HS_HCCHAR2

OTG_HS host channel-2 characteristics register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCCHAR2 OTG_HS_HCCHAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MC DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


OTG_HS_HCSPLT2

OTG_HS host channel-2 split control register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCSPLT2 OTG_HS_HCSPLT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPLSPLT SPLITEN

PRTADDR : Port address
bits : 0 - 6 (7 bit)

HUBADDR : Hub address
bits : 7 - 13 (7 bit)

XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)

COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)

SPLITEN : Split enable
bits : 31 - 31 (1 bit)


OTG_HS_HCINT2

OTG_HS host channel-2 interrupt register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINT2 OTG_HS_HCINT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH AHBERR STALL NAK ACK NYET TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : Response received interrupt
bits : 6 - 6 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


OTG_HS_HCINTMSK2

OTG_HS host channel-2 interrupt mask register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINTMSK2 OTG_HS_HCINTMSK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM AHBERR STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


OTG_HS_HCTSIZ2

OTG_HS host channel-2 transfer size register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCTSIZ2 OTG_HS_HCTSIZ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


OTG_HS_HCDMA2

OTG_HS host channel-2 DMA address register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCDMA2 OTG_HS_HCDMA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_HCCHAR3

OTG_HS host channel-3 characteristics register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCCHAR3 OTG_HS_HCCHAR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MC DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


OTG_HS_HCSPLT3

OTG_HS host channel-3 split control register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCSPLT3 OTG_HS_HCSPLT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPLSPLT SPLITEN

PRTADDR : Port address
bits : 0 - 6 (7 bit)

HUBADDR : Hub address
bits : 7 - 13 (7 bit)

XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)

COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)

SPLITEN : Split enable
bits : 31 - 31 (1 bit)


OTG_HS_HCINT3

OTG_HS host channel-3 interrupt register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINT3 OTG_HS_HCINT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH AHBERR STALL NAK ACK NYET TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : Response received interrupt
bits : 6 - 6 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


OTG_HS_HCINTMSK3

OTG_HS host channel-3 interrupt mask register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINTMSK3 OTG_HS_HCINTMSK3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM AHBERR STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


OTG_HS_HCTSIZ3

OTG_HS host channel-3 transfer size register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCTSIZ3 OTG_HS_HCTSIZ3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


OTG_HS_HCDMA3

OTG_HS host channel-3 DMA address register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCDMA3 OTG_HS_HCDMA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_HAINTMSK

OTG_HS host all channels interrupt mask register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HAINTMSK OTG_HS_HAINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAINTM

HAINTM : Channel interrupt mask
bits : 0 - 15 (16 bit)


OTG_HS_HCCHAR4

OTG_HS host channel-4 characteristics register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCCHAR4 OTG_HS_HCCHAR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MC DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


OTG_HS_HCSPLT4

OTG_HS host channel-4 split control register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCSPLT4 OTG_HS_HCSPLT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPLSPLT SPLITEN

PRTADDR : Port address
bits : 0 - 6 (7 bit)

HUBADDR : Hub address
bits : 7 - 13 (7 bit)

XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)

COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)

SPLITEN : Split enable
bits : 31 - 31 (1 bit)


OTG_HS_HCINT4

OTG_HS host channel-4 interrupt register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINT4 OTG_HS_HCINT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH AHBERR STALL NAK ACK NYET TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : Response received interrupt
bits : 6 - 6 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


OTG_HS_HCINTMSK4

OTG_HS host channel-4 interrupt mask register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINTMSK4 OTG_HS_HCINTMSK4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM AHBERR STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


OTG_HS_HCTSIZ4

OTG_HS host channel-4 transfer size register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCTSIZ4 OTG_HS_HCTSIZ4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


OTG_HS_HCDMA4

OTG_HS host channel-4 DMA address register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCDMA4 OTG_HS_HCDMA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_HCCHAR5

OTG_HS host channel-5 characteristics register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCCHAR5 OTG_HS_HCCHAR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MC DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


OTG_HS_HCSPLT5

OTG_HS host channel-5 split control register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCSPLT5 OTG_HS_HCSPLT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPLSPLT SPLITEN

PRTADDR : Port address
bits : 0 - 6 (7 bit)

HUBADDR : Hub address
bits : 7 - 13 (7 bit)

XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)

COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)

SPLITEN : Split enable
bits : 31 - 31 (1 bit)


OTG_HS_HCINT5

OTG_HS host channel-5 interrupt register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINT5 OTG_HS_HCINT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH AHBERR STALL NAK ACK NYET TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : Response received interrupt
bits : 6 - 6 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


OTG_HS_HCINTMSK5

OTG_HS host channel-5 interrupt mask register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINTMSK5 OTG_HS_HCINTMSK5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM AHBERR STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


OTG_HS_HCTSIZ5

OTG_HS host channel-5 transfer size register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCTSIZ5 OTG_HS_HCTSIZ5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


OTG_HS_HCDMA5

OTG_HS host channel-5 DMA address register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCDMA5 OTG_HS_HCDMA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_HCCHAR6

OTG_HS host channel-6 characteristics register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCCHAR6 OTG_HS_HCCHAR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MC DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


OTG_HS_HCSPLT6

OTG_HS host channel-6 split control register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCSPLT6 OTG_HS_HCSPLT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPLSPLT SPLITEN

PRTADDR : Port address
bits : 0 - 6 (7 bit)

HUBADDR : Hub address
bits : 7 - 13 (7 bit)

XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)

COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)

SPLITEN : Split enable
bits : 31 - 31 (1 bit)


OTG_HS_HCINT6

OTG_HS host channel-6 interrupt register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINT6 OTG_HS_HCINT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH AHBERR STALL NAK ACK NYET TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : Response received interrupt
bits : 6 - 6 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


OTG_HS_HCINTMSK6

OTG_HS host channel-6 interrupt mask register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINTMSK6 OTG_HS_HCINTMSK6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM AHBERR STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


OTG_HS_HCTSIZ6

OTG_HS host channel-6 transfer size register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCTSIZ6 OTG_HS_HCTSIZ6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


OTG_HS_HCDMA6

OTG_HS host channel-6 DMA address register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCDMA6 OTG_HS_HCDMA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_HCCHAR7

OTG_HS host channel-7 characteristics register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCCHAR7 OTG_HS_HCCHAR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MC DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


OTG_HS_HCSPLT7

OTG_HS host channel-7 split control register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCSPLT7 OTG_HS_HCSPLT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPLSPLT SPLITEN

PRTADDR : Port address
bits : 0 - 6 (7 bit)

HUBADDR : Hub address
bits : 7 - 13 (7 bit)

XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)

COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)

SPLITEN : Split enable
bits : 31 - 31 (1 bit)


OTG_HS_HCINT7

OTG_HS host channel-7 interrupt register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINT7 OTG_HS_HCINT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH AHBERR STALL NAK ACK NYET TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : Response received interrupt
bits : 6 - 6 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


OTG_HS_HCINTMSK7

OTG_HS host channel-7 interrupt mask register
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINTMSK7 OTG_HS_HCINTMSK7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM AHBERR STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


OTG_HS_HCTSIZ7

OTG_HS host channel-7 transfer size register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCTSIZ7 OTG_HS_HCTSIZ7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


OTG_HS_HCDMA7

OTG_HS host channel-7 DMA address register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCDMA7 OTG_HS_HCDMA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_HCCHAR8

OTG_HS host channel-8 characteristics register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCCHAR8 OTG_HS_HCCHAR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MC DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


OTG_HS_HCSPLT8

OTG_HS host channel-8 split control register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCSPLT8 OTG_HS_HCSPLT8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPLSPLT SPLITEN

PRTADDR : Port address
bits : 0 - 6 (7 bit)

HUBADDR : Hub address
bits : 7 - 13 (7 bit)

XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)

COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)

SPLITEN : Split enable
bits : 31 - 31 (1 bit)


OTG_HS_HCINT8

OTG_HS host channel-8 interrupt register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINT8 OTG_HS_HCINT8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH AHBERR STALL NAK ACK NYET TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : Response received interrupt
bits : 6 - 6 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


OTG_HS_HCINTMSK8

OTG_HS host channel-8 interrupt mask register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINTMSK8 OTG_HS_HCINTMSK8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM AHBERR STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


OTG_HS_HCTSIZ8

OTG_HS host channel-8 transfer size register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCTSIZ8 OTG_HS_HCTSIZ8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


OTG_HS_HCDMA8

OTG_HS host channel-8 DMA address register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCDMA8 OTG_HS_HCDMA8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_HCCHAR9

OTG_HS host channel-9 characteristics register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCCHAR9 OTG_HS_HCCHAR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MC DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


OTG_HS_HCSPLT9

OTG_HS host channel-9 split control register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCSPLT9 OTG_HS_HCSPLT9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPLSPLT SPLITEN

PRTADDR : Port address
bits : 0 - 6 (7 bit)

HUBADDR : Hub address
bits : 7 - 13 (7 bit)

XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)

COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)

SPLITEN : Split enable
bits : 31 - 31 (1 bit)


OTG_HS_HCINT9

OTG_HS host channel-9 interrupt register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINT9 OTG_HS_HCINT9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH AHBERR STALL NAK ACK NYET TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : Response received interrupt
bits : 6 - 6 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


OTG_HS_HCINTMSK9

OTG_HS host channel-9 interrupt mask register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINTMSK9 OTG_HS_HCINTMSK9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM AHBERR STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


OTG_HS_HCTSIZ9

OTG_HS host channel-9 transfer size register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCTSIZ9 OTG_HS_HCTSIZ9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


OTG_HS_HCDMA9

OTG_HS host channel-9 DMA address register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCDMA9 OTG_HS_HCDMA9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_HCCHAR10

OTG_HS host channel-10 characteristics register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCCHAR10 OTG_HS_HCCHAR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MC DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


OTG_HS_HCSPLT10

OTG_HS host channel-10 split control register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCSPLT10 OTG_HS_HCSPLT10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPLSPLT SPLITEN

PRTADDR : Port address
bits : 0 - 6 (7 bit)

HUBADDR : Hub address
bits : 7 - 13 (7 bit)

XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)

COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)

SPLITEN : Split enable
bits : 31 - 31 (1 bit)


OTG_HS_HCINT10

OTG_HS host channel-10 interrupt register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINT10 OTG_HS_HCINT10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH AHBERR STALL NAK ACK NYET TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : Response received interrupt
bits : 6 - 6 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


OTG_HS_HCINTMSK10

OTG_HS host channel-10 interrupt mask register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINTMSK10 OTG_HS_HCINTMSK10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM AHBERR STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


OTG_HS_HCTSIZ10

OTG_HS host channel-10 transfer size register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCTSIZ10 OTG_HS_HCTSIZ10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


OTG_HS_HCDMA10

OTG_HS host channel-10 DMA address register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCDMA10 OTG_HS_HCDMA10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_HCCHAR11

OTG_HS host channel-11 characteristics register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCCHAR11 OTG_HS_HCCHAR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MC DAD ODDFRM CHDIS CHENA

MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSDEV : Low-speed device
bits : 17 - 17 (1 bit)

EPTYP : Endpoint type
bits : 18 - 19 (2 bit)

MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)

DAD : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CHDIS : Channel disable
bits : 30 - 30 (1 bit)

CHENA : Channel enable
bits : 31 - 31 (1 bit)


OTG_HS_HCSPLT11

OTG_HS host channel-11 split control register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCSPLT11 OTG_HS_HCSPLT11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRTADDR HUBADDR XACTPOS COMPLSPLT SPLITEN

PRTADDR : Port address
bits : 0 - 6 (7 bit)

HUBADDR : Hub address
bits : 7 - 13 (7 bit)

XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)

COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)

SPLITEN : Split enable
bits : 31 - 31 (1 bit)


OTG_HS_HCINT11

OTG_HS host channel-11 interrupt register
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINT11 OTG_HS_HCINT11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH AHBERR STALL NAK ACK NYET TXERR BBERR FRMOR DTERR

XFRC : Transfer completed
bits : 0 - 0 (1 bit)

CHH : Channel halted
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : Response received interrupt
bits : 6 - 6 (1 bit)

TXERR : Transaction error
bits : 7 - 7 (1 bit)

BBERR : Babble error
bits : 8 - 8 (1 bit)

FRMOR : Frame overrun
bits : 9 - 9 (1 bit)

DTERR : Data toggle error
bits : 10 - 10 (1 bit)


OTG_HS_HCINTMSK11

OTG_HS host channel-11 interrupt mask register
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCINTMSK11 OTG_HS_HCINTMSK11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM AHBERR STALLM NAKM ACKM NYET TXERRM BBERRM FRMORM DTERRM

XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)

CHHM : Channel halted mask
bits : 1 - 1 (1 bit)

AHBERR : AHB error
bits : 2 - 2 (1 bit)

STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)

NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)

ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)

NYET : response received interrupt mask
bits : 6 - 6 (1 bit)

TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)

BBERRM : Babble error mask
bits : 8 - 8 (1 bit)

FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)

DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)


OTG_HS_HCTSIZ11

OTG_HS host channel-11 transfer size register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCTSIZ11 OTG_HS_HCTSIZ11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID

XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)

PKTCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)


OTG_HS_HCDMA11

OTG_HS host channel-11 DMA address register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HCDMA11 OTG_HS_HCDMA11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


OTG_HS_HFIR

OTG_HS Host frame interval register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HFIR OTG_HS_HFIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRIVL

FRIVL : Frame interval
bits : 0 - 15 (16 bit)


OTG_HS_HPRT

OTG_HS host port control and status register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HPRT OTG_HS_HPRT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCSTS PCDET PENA PENCHNG POCA POCCHNG PRES PSUSP PRST PLSTS PPWR PTCTL PSPD

PCSTS : Port connect status
bits : 0 - 0 (1 bit)
access : read-only

PCDET : Port connect detected
bits : 1 - 1 (1 bit)
access : read-write

PENA : Port enable
bits : 2 - 2 (1 bit)
access : read-write

PENCHNG : Port enable/disable change
bits : 3 - 3 (1 bit)
access : read-write

POCA : Port overcurrent active
bits : 4 - 4 (1 bit)
access : read-only

POCCHNG : Port overcurrent change
bits : 5 - 5 (1 bit)
access : read-write

PRES : Port resume
bits : 6 - 6 (1 bit)
access : read-write

PSUSP : Port suspend
bits : 7 - 7 (1 bit)
access : read-write

PRST : Port reset
bits : 8 - 8 (1 bit)
access : read-write

PLSTS : Port line status
bits : 10 - 11 (2 bit)
access : read-only

PPWR : Port power
bits : 12 - 12 (1 bit)
access : read-write

PTCTL : Port test control
bits : 13 - 16 (4 bit)
access : read-write

PSPD : Port speed
bits : 17 - 18 (2 bit)
access : read-only


OTG_HS_HFNUM

OTG_HS host frame number/frame time remaining register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OTG_HS_HFNUM OTG_HS_HFNUM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRNUM FTREM

FRNUM : Frame number
bits : 0 - 15 (16 bit)

FTREM : Frame time remaining
bits : 16 - 31 (16 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.