Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : TRNG Module Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Module disabled
1 : ENABLED
Module enabled
End of enumeration elements list.
TESTEN : Test Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOISE
Non-determinsitc random number generation
1 : TESTDATA
Pseudo-random number generation
End of enumeration elements list.
CONDBYPASS : Conditioning Bypass
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
The conditionig function is used
1 : BYPASS
The conditioning function is bypassed
End of enumeration elements list.
REPCOUNTIEN : IRQ enable for Repetition Count Test
bits : 4 - 4 (1 bit)
access : read-write
APT64IEN : IRQ enable for APT64IF
bits : 5 - 5 (1 bit)
access : read-write
APT4096IEN : IRQ enable for APT4096IF
bits : 6 - 6 (1 bit)
access : read-write
FULLIEN : IRQ enable for FIFO full
bits : 7 - 7 (1 bit)
access : read-write
SOFTRESET : Software Reset
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Module not in reset
1 : RESET
The continuous test, the conditioning function and the FIFO are reset
End of enumeration elements list.
PREIEN : IRQ enable for AIS31 prelim. noise alarm
bits : 9 - 9 (1 bit)
access : read-write
ALMIEN : IRQ enable for AIS31 noise alarm
bits : 10 - 10 (1 bit)
access : read-write
FORCERUN : Oscillator Force Run
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Oscillators will shut down when FIFO is full
1 : RUN
Oscillators will continue to run even after FIFO is full
End of enumeration elements list.
BYPNIST : NIST Start-up Test Bypass.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
NIST-800-90B startup test is applied. No data will be written to the FIFO until the test passes.
1 : BYPASS
NIST-800-90B startup test is bypassed.
End of enumeration elements list.
BYPAIS31 : AIS31 Start-up Test Bypass.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
AIS31 startup test is applied. No data will be written to the FIFO until the test passes.
1 : BYPASS
AIS31 startup test is bypassed.
End of enumeration elements list.
HEALTHTESTSEL : Health test input select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : BEFORE
Before conditioning
1 : AFTER
After conditioning
End of enumeration elements list.
AIS31TESTSEL : AIS31 test input select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : BEFORE
Before conditioning
1 : AFTER
After conditioning
End of enumeration elements list.
NB128BITBLOCKS : Number of 128b blocks in AES-CBCMAC
bits : 16 - 19 (4 bit)
access : read-write
FIFOWRSTARTUP : Fifo Write Start Up
bits : 20 - 20 (1 bit)
access : read-write
This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011...
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : Key
bits : 0 - 31 (32 bit)
access : read-write
This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011...
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : Key
bits : 0 - 31 (32 bit)
access : read-write
This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011...
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : Key
bits : 0 - 31 (32 bit)
access : read-write
This set of registers bits form the 128-bit AES key used for conditioning function. The first byte (MSB of 128-bit word) is at address 0x0010, the second byte at address 0x0011...
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : Key
bits : 0 - 31 (32 bit)
access : read-write
This register is used to feed known data to the conditioning function or to the continuous tests. See manual
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
VALUE : Test data input to conditioning tests
bits : 0 - 31 (32 bit)
access : write-only
No Description
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TESTDATABUSY : Test Data Busy
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : IDLE
TESTDATA write is finished processing or no test in progress.
1 : BUSY
TESTDATA write is still being processed.
End of enumeration elements list.
STATE : State of the control FSM
bits : 1 - 3 (3 bit)
access : read-only
Enumeration:
0 : RESET
RESET State
1 : STARTUP
STARTUP State
2 : FIFOFULLON
FIFOFULLON State
3 : FIFOFULLOFF
FIFOFULLOFF State
4 : RUNNING
RUNNING State
5 : ERROR
ERROR State
6 : UNUSED_6
UNUSED
7 : UNUSED_7
UNUSED
End of enumeration elements list.
REPCOUNTIF : Repetition Count Test interrupt status
bits : 4 - 4 (1 bit)
access : read-only
APT64IF : 64-sample window Adaptive Proportion IF
bits : 5 - 5 (1 bit)
access : read-only
APT4096IF : 4096-sample window Adaptive Prop. IF
bits : 6 - 6 (1 bit)
access : read-only
FULLIF : FIFO full interrupt status
bits : 7 - 7 (1 bit)
access : read-only
PREIF : AIS31 Preliminary Noise Alarm IF
bits : 8 - 8 (1 bit)
access : read-write
ALMIF : AIS31 Noise Alarm interrupt status
bits : 9 - 9 (1 bit)
access : read-only
No Description
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INITWAITVAL : Wait counter value
bits : 0 - 15 (16 bit)
access : read-write
Number of 32 bits words of random available in the FIFO. Writing to this register clears the FIFO full interrupt
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FIFOLEVEL : FIFO Level
bits : 0 - 31 (32 bit)
access : read-only
Number of clk cycles to wait before stopping the rings after the FIFO is full
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWOFFTMRVAL : Switch Off Timer Value
bits : 0 - 15 (16 bit)
access : read-write
Sample clock divider. The frequency at which the outputs of the rings are sampled is given by Fs = Fpclk/(ClkDiv + 1)
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Sample clock divider
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTUPTHRES : Start-up Threshold
bits : 0 - 14 (15 bit)
access : read-write
ONLINETHRESH : Online Threshold
bits : 16 - 30 (15 bit)
access : read-write
No Description
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HEXPECTEDVALUE : Expected History Value
bits : 0 - 14 (15 bit)
access : read-write
ONLINEREPTHRESH : Online Repeat Threshold
bits : 16 - 30 (15 bit)
access : read-write
No Description
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HMIN : Minimum Allowed History Value
bits : 0 - 14 (15 bit)
access : read-write
HMAX : Maximum Allowed History Value
bits : 16 - 30 (15 bit)
access : read-write
This register is used to obtain diagnostic information about the AIS31 start-up and online tests when g_AIS31=True. Writing to this register clears all fields
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUMPRELIMALARMS : Number of preliminary alarms
bits : 0 - 15 (16 bit)
access : read-write
PRELIMNOISEALARMRNG : Preliminary noise alarm RNG
bits : 16 - 16 (1 bit)
access : read-write
PRELIMNOISEALARMREP : Preliminary noise alarm Rep
bits : 17 - 17 (1 bit)
access : read-write
FIFO level at which the rings are restarted when in the FIFOFull_Off state, expressed in number of 128bit blocks
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FIFOTHRESH : FIFO threshold level
bits : 0 - 31 (32 bit)
access : read-only
Maximum number of 32 bits words that can be stored in the FIFO: 2^g_fifodepth
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FIFODEPTH : FIFO Depth.
bits : 0 - 31 (32 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.