\n

FSMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

BCR1

BCR3

BWTR1

BWTR3

BWTR2

BWTR4

BTR3

SDCR1

SDCR2

SDTR1

SDTR2

SDCMR

SDRTR

SDSR

BCR4

BTR4

BTR1

PCR2

SR2

PMEM2

PATT2

ECCR2

BCR2

PCR3

SR3

PMEM3

PATT3

ECCR3

PCR4

SR4

PMEM4

PATT4

PIO4

BTR2


BCR1

SRAM/NOR-Flash chip-select control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR1 BCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBKEN MUXEN MTYP MWID FACCEN BURSTEN WAITPOL WRAPMOD WAITCFG WREN WAITEN EXTMOD ASYNCWAIT CPSIZE CBURSTRW CCLKEN

MBKEN : MBKEN
bits : 0 - 0 (1 bit)

MUXEN : MUXEN
bits : 1 - 1 (1 bit)

MTYP : MTYP
bits : 2 - 3 (2 bit)

MWID : MWID
bits : 4 - 5 (2 bit)

FACCEN : FACCEN
bits : 6 - 6 (1 bit)

BURSTEN : BURSTEN
bits : 8 - 8 (1 bit)

WAITPOL : WAITPOL
bits : 9 - 9 (1 bit)

WRAPMOD : WRAPMOD
bits : 10 - 10 (1 bit)

WAITCFG : WAITCFG
bits : 11 - 11 (1 bit)

WREN : WREN
bits : 12 - 12 (1 bit)

WAITEN : WAITEN
bits : 13 - 13 (1 bit)

EXTMOD : EXTMOD
bits : 14 - 14 (1 bit)

ASYNCWAIT : ASYNCWAIT
bits : 15 - 15 (1 bit)

CPSIZE : CPSIZE
bits : 16 - 18 (3 bit)

CBURSTRW : CBURSTRW
bits : 19 - 19 (1 bit)

CCLKEN : CCLKEN
bits : 20 - 20 (1 bit)


BCR3

SRAM/NOR-Flash chip-select control register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR3 BCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBKEN MUXEN MTYP MWID FACCEN BURSTEN WAITPOL WRAPMOD WAITCFG WREN WAITEN EXTMOD ASYNCWAIT CPSIZE CBURSTRW

MBKEN : MBKEN
bits : 0 - 0 (1 bit)

MUXEN : MUXEN
bits : 1 - 1 (1 bit)

MTYP : MTYP
bits : 2 - 3 (2 bit)

MWID : MWID
bits : 4 - 5 (2 bit)

FACCEN : FACCEN
bits : 6 - 6 (1 bit)

BURSTEN : BURSTEN
bits : 8 - 8 (1 bit)

WAITPOL : WAITPOL
bits : 9 - 9 (1 bit)

WRAPMOD : WRAPMOD
bits : 10 - 10 (1 bit)

WAITCFG : WAITCFG
bits : 11 - 11 (1 bit)

WREN : WREN
bits : 12 - 12 (1 bit)

WAITEN : WAITEN
bits : 13 - 13 (1 bit)

EXTMOD : EXTMOD
bits : 14 - 14 (1 bit)

ASYNCWAIT : ASYNCWAIT
bits : 15 - 15 (1 bit)

CPSIZE : CPSIZE
bits : 16 - 18 (3 bit)

CBURSTRW : CBURSTRW
bits : 19 - 19 (1 bit)


BWTR1

SRAM/NOR-Flash write timing registers 1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BWTR1 BWTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD BUSTURN ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

BUSTURN : BUSTURN
bits : 16 - 19 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BWTR3

SRAM/NOR-Flash write timing registers 3
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : BWTR1
reset_Mask : 0x0

BWTR3 BWTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD BUSTURN ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

BUSTURN : BUSTURN
bits : 16 - 19 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BWTR2

SRAM/NOR-Flash write timing registers 2
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BWTR2 BWTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD BUSTURN ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

BUSTURN : BUSTURN
bits : 16 - 19 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BWTR4

SRAM/NOR-Flash write timing registers 4
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : BWTR2
reset_Mask : 0x0

BWTR4 BWTR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD BUSTURN ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

BUSTURN : BUSTURN
bits : 16 - 19 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BTR3

SRAM/NOR-Flash chip-select timing register 3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR3 BTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

BUSTURN : BUSTURN
bits : 16 - 19 (4 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


SDCR1

SDRAM Control Register 1
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDCR1 SDCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NC NR MWID NB CAS WP SDCLK RBURST RPIPE

NC : Number of column address bits
bits : 0 - 1 (2 bit)

NR : Number of row address bits
bits : 2 - 3 (2 bit)

MWID : Memory data bus width
bits : 4 - 5 (2 bit)

NB : Number of internal banks
bits : 6 - 6 (1 bit)

CAS : CAS latency
bits : 7 - 8 (2 bit)

WP : Write protection
bits : 9 - 9 (1 bit)

SDCLK : SDRAM clock configuration
bits : 10 - 11 (2 bit)

RBURST : Burst read
bits : 12 - 12 (1 bit)

RPIPE : Read pipe
bits : 13 - 14 (2 bit)


SDCR2

SDRAM Control Register 2
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDCR2 SDCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NC NR MWID NB CAS WP SDCLK

NC : Number of column address bits
bits : 0 - 1 (2 bit)

NR : Number of row address bits
bits : 2 - 3 (2 bit)

MWID : Memory data bus width
bits : 4 - 5 (2 bit)

NB : Number of internal banks
bits : 6 - 6 (1 bit)

CAS : CAS latency
bits : 7 - 8 (2 bit)

WP : Write protection
bits : 9 - 9 (1 bit)

SDCLK : SDRAM clock configuration
bits : 10 - 11 (2 bit)


SDTR1

SDRAM Timing register 1
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDTR1 SDTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRD TXSR TRAS TRC TWR TRP TRCD

TMRD : Load Mode Register to Active
bits : 0 - 3 (4 bit)

TXSR : Exit self-refresh delay
bits : 4 - 7 (4 bit)

TRAS : Self refresh time
bits : 8 - 11 (4 bit)

TRC : Row cycle delay
bits : 12 - 15 (4 bit)

TWR : Recovery delay
bits : 16 - 19 (4 bit)

TRP : Row precharge delay
bits : 20 - 23 (4 bit)

TRCD : Row to column delay
bits : 24 - 27 (4 bit)


SDTR2

SDRAM Timing register 2
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDTR2 SDTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRD TXSR TRAS TRC TWR TRP TRCD

TMRD : Load Mode Register to Active
bits : 0 - 3 (4 bit)

TXSR : Exit self-refresh delay
bits : 4 - 7 (4 bit)

TRAS : Self refresh time
bits : 8 - 11 (4 bit)

TRC : Row cycle delay
bits : 12 - 15 (4 bit)

TWR : Recovery delay
bits : 16 - 19 (4 bit)

TRP : Row precharge delay
bits : 20 - 23 (4 bit)

TRCD : Row to column delay
bits : 24 - 27 (4 bit)


SDCMR

SDRAM Command Mode register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDCMR SDCMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE CTB2 CTB1 NRFS MRD

MODE : Command mode
bits : 0 - 2 (3 bit)
access : write-only

CTB2 : Command target bank 2
bits : 3 - 3 (1 bit)
access : write-only

CTB1 : Command target bank 1
bits : 4 - 4 (1 bit)
access : write-only

NRFS : Number of Auto-refresh
bits : 5 - 8 (4 bit)
access : read-write

MRD : Mode Register definition
bits : 9 - 21 (13 bit)
access : read-write


SDRTR

SDRAM Refresh Timer register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRTR SDRTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRE COUNT REIE

CRE : Clear Refresh error flag
bits : 0 - 0 (1 bit)
access : write-only

COUNT : Refresh Timer Count
bits : 1 - 13 (13 bit)
access : read-write

REIE : RES Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write


SDSR

SDRAM Status register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SDSR SDSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RE MODES1 MODES2 BUSY

RE : Refresh error flag
bits : 0 - 0 (1 bit)

MODES1 : Status Mode for Bank 1
bits : 1 - 2 (2 bit)

MODES2 : Status Mode for Bank 2
bits : 3 - 4 (2 bit)

BUSY : Busy status
bits : 5 - 5 (1 bit)


BCR4

SRAM/NOR-Flash chip-select control register 4
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR4 BCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBKEN MUXEN MTYP MWID FACCEN BURSTEN WAITPOL WRAPMOD WAITCFG WREN WAITEN EXTMOD ASYNCWAIT CPSIZE CBURSTRW

MBKEN : MBKEN
bits : 0 - 0 (1 bit)

MUXEN : MUXEN
bits : 1 - 1 (1 bit)

MTYP : MTYP
bits : 2 - 3 (2 bit)

MWID : MWID
bits : 4 - 5 (2 bit)

FACCEN : FACCEN
bits : 6 - 6 (1 bit)

BURSTEN : BURSTEN
bits : 8 - 8 (1 bit)

WAITPOL : WAITPOL
bits : 9 - 9 (1 bit)

WRAPMOD : WRAPMOD
bits : 10 - 10 (1 bit)

WAITCFG : WAITCFG
bits : 11 - 11 (1 bit)

WREN : WREN
bits : 12 - 12 (1 bit)

WAITEN : WAITEN
bits : 13 - 13 (1 bit)

EXTMOD : EXTMOD
bits : 14 - 14 (1 bit)

ASYNCWAIT : ASYNCWAIT
bits : 15 - 15 (1 bit)

CPSIZE : CPSIZE
bits : 16 - 18 (3 bit)

CBURSTRW : CBURSTRW
bits : 19 - 19 (1 bit)


BTR4

SRAM/NOR-Flash chip-select timing register 4
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR4 BTR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

BUSTURN : BUSTURN
bits : 16 - 19 (4 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BTR1

SRAM/NOR-Flash chip-select timing register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR1 BTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

BUSTURN : BUSTURN
bits : 16 - 19 (4 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


PCR2

PC Card/NAND Flash control register 2
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR2 PCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWAITEN PBKEN PTYP PWID ECCEN TCLR TAR ECCPS

PWAITEN : PWAITEN
bits : 1 - 1 (1 bit)

PBKEN : PBKEN
bits : 2 - 2 (1 bit)

PTYP : PTYP
bits : 3 - 3 (1 bit)

PWID : PWID
bits : 4 - 5 (2 bit)

ECCEN : ECCEN
bits : 6 - 6 (1 bit)

TCLR : TCLR
bits : 9 - 12 (4 bit)

TAR : TAR
bits : 13 - 16 (4 bit)

ECCPS : ECCPS
bits : 17 - 19 (3 bit)


SR2

FIFO status and interrupt register 2
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR2 SR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRS ILS IFS IREN ILEN IFEN FEMPT

IRS : IRS
bits : 0 - 0 (1 bit)
access : read-write

ILS : ILS
bits : 1 - 1 (1 bit)
access : read-write

IFS : IFS
bits : 2 - 2 (1 bit)
access : read-write

IREN : IREN
bits : 3 - 3 (1 bit)
access : read-write

ILEN : ILEN
bits : 4 - 4 (1 bit)
access : read-write

IFEN : IFEN
bits : 5 - 5 (1 bit)
access : read-write

FEMPT : FEMPT
bits : 6 - 6 (1 bit)
access : read-only


PMEM2

Common memory space timing register 2
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMEM2 PMEM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMSETx MEMWAITx MEMHOLDx MEMHIZx

MEMSETx : MEMSETx
bits : 0 - 7 (8 bit)

MEMWAITx : MEMWAITx
bits : 8 - 15 (8 bit)

MEMHOLDx : MEMHOLDx
bits : 16 - 23 (8 bit)

MEMHIZx : MEMHIZx
bits : 24 - 31 (8 bit)


PATT2

Attribute memory space timing register 2
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATT2 PATT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATTSETx ATTWAITx ATTHOLDx ATTHIZx

ATTSETx : ATTSETx
bits : 0 - 7 (8 bit)

ATTWAITx : ATTWAITx
bits : 8 - 15 (8 bit)

ATTHOLDx : ATTHOLDx
bits : 16 - 23 (8 bit)

ATTHIZx : ATTHIZx
bits : 24 - 31 (8 bit)


ECCR2

ECC result register 2
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECCR2 ECCR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCx

ECCx : ECCx
bits : 0 - 31 (32 bit)


BCR2

SRAM/NOR-Flash chip-select control register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR2 BCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBKEN MUXEN MTYP MWID FACCEN BURSTEN WAITPOL WRAPMOD WAITCFG WREN WAITEN EXTMOD ASYNCWAIT CPSIZE CBURSTRW

MBKEN : MBKEN
bits : 0 - 0 (1 bit)

MUXEN : MUXEN
bits : 1 - 1 (1 bit)

MTYP : MTYP
bits : 2 - 3 (2 bit)

MWID : MWID
bits : 4 - 5 (2 bit)

FACCEN : FACCEN
bits : 6 - 6 (1 bit)

BURSTEN : BURSTEN
bits : 8 - 8 (1 bit)

WAITPOL : WAITPOL
bits : 9 - 9 (1 bit)

WRAPMOD : WRAPMOD
bits : 10 - 10 (1 bit)

WAITCFG : WAITCFG
bits : 11 - 11 (1 bit)

WREN : WREN
bits : 12 - 12 (1 bit)

WAITEN : WAITEN
bits : 13 - 13 (1 bit)

EXTMOD : EXTMOD
bits : 14 - 14 (1 bit)

ASYNCWAIT : ASYNCWAIT
bits : 15 - 15 (1 bit)

CPSIZE : CPSIZE
bits : 16 - 18 (3 bit)

CBURSTRW : CBURSTRW
bits : 19 - 19 (1 bit)


PCR3

PC Card/NAND Flash control register 3
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR3 PCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWAITEN PBKEN PTYP PWID ECCEN TCLR TAR ECCPS

PWAITEN : PWAITEN
bits : 1 - 1 (1 bit)

PBKEN : PBKEN
bits : 2 - 2 (1 bit)

PTYP : PTYP
bits : 3 - 3 (1 bit)

PWID : PWID
bits : 4 - 5 (2 bit)

ECCEN : ECCEN
bits : 6 - 6 (1 bit)

TCLR : TCLR
bits : 9 - 12 (4 bit)

TAR : TAR
bits : 13 - 16 (4 bit)

ECCPS : ECCPS
bits : 17 - 19 (3 bit)


SR3

FIFO status and interrupt register 3
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR3 SR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRS ILS IFS IREN ILEN IFEN FEMPT

IRS : IRS
bits : 0 - 0 (1 bit)
access : read-write

ILS : ILS
bits : 1 - 1 (1 bit)
access : read-write

IFS : IFS
bits : 2 - 2 (1 bit)
access : read-write

IREN : IREN
bits : 3 - 3 (1 bit)
access : read-write

ILEN : ILEN
bits : 4 - 4 (1 bit)
access : read-write

IFEN : IFEN
bits : 5 - 5 (1 bit)
access : read-write

FEMPT : FEMPT
bits : 6 - 6 (1 bit)
access : read-only


PMEM3

Common memory space timing register 3
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMEM3 PMEM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMSETx MEMWAITx MEMHOLDx MEMHIZx

MEMSETx : MEMSETx
bits : 0 - 7 (8 bit)

MEMWAITx : MEMWAITx
bits : 8 - 15 (8 bit)

MEMHOLDx : MEMHOLDx
bits : 16 - 23 (8 bit)

MEMHIZx : MEMHIZx
bits : 24 - 31 (8 bit)


PATT3

Attribute memory space timing register 3
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATT3 PATT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATTSETx ATTWAITx ATTHOLDx ATTHIZx

ATTSETx : ATTSETx
bits : 0 - 7 (8 bit)

ATTWAITx : ATTWAITx
bits : 8 - 15 (8 bit)

ATTHOLDx : ATTHOLDx
bits : 16 - 23 (8 bit)

ATTHIZx : ATTHIZx
bits : 24 - 31 (8 bit)


ECCR3

ECC result register 3
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECCR3 ECCR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCx

ECCx : ECCx
bits : 0 - 31 (32 bit)


PCR4

PC Card/NAND Flash control register 4
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR4 PCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWAITEN PBKEN PTYP PWID ECCEN TCLR TAR ECCPS

PWAITEN : PWAITEN
bits : 1 - 1 (1 bit)

PBKEN : PBKEN
bits : 2 - 2 (1 bit)

PTYP : PTYP
bits : 3 - 3 (1 bit)

PWID : PWID
bits : 4 - 5 (2 bit)

ECCEN : ECCEN
bits : 6 - 6 (1 bit)

TCLR : TCLR
bits : 9 - 12 (4 bit)

TAR : TAR
bits : 13 - 16 (4 bit)

ECCPS : ECCPS
bits : 17 - 19 (3 bit)


SR4

FIFO status and interrupt register 4
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR4 SR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRS ILS IFS IREN ILEN IFEN FEMPT

IRS : IRS
bits : 0 - 0 (1 bit)
access : read-write

ILS : ILS
bits : 1 - 1 (1 bit)
access : read-write

IFS : IFS
bits : 2 - 2 (1 bit)
access : read-write

IREN : IREN
bits : 3 - 3 (1 bit)
access : read-write

ILEN : ILEN
bits : 4 - 4 (1 bit)
access : read-write

IFEN : IFEN
bits : 5 - 5 (1 bit)
access : read-write

FEMPT : FEMPT
bits : 6 - 6 (1 bit)
access : read-only


PMEM4

Common memory space timing register 4
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMEM4 PMEM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMSETx MEMWAITx MEMHOLDx MEMHIZx

MEMSETx : MEMSETx
bits : 0 - 7 (8 bit)

MEMWAITx : MEMWAITx
bits : 8 - 15 (8 bit)

MEMHOLDx : MEMHOLDx
bits : 16 - 23 (8 bit)

MEMHIZx : MEMHIZx
bits : 24 - 31 (8 bit)


PATT4

Attribute memory space timing register 4
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATT4 PATT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATTSETx ATTWAITx ATTHOLDx ATTHIZx

ATTSETx : ATTSETx
bits : 0 - 7 (8 bit)

ATTWAITx : ATTWAITx
bits : 8 - 15 (8 bit)

ATTHOLDx : ATTHOLDx
bits : 16 - 23 (8 bit)

ATTHIZx : ATTHIZx
bits : 24 - 31 (8 bit)


PIO4

I/O space timing register 4
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO4 PIO4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSETx IOWAITx IOHOLDx IOHIZx

IOSETx : IOSETx
bits : 0 - 7 (8 bit)

IOWAITx : IOWAITx
bits : 8 - 15 (8 bit)

IOHOLDx : IOHOLDx
bits : 16 - 23 (8 bit)

IOHIZx : IOHIZx
bits : 24 - 31 (8 bit)


BTR2

SRAM/NOR-Flash chip-select timing register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR2 BTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

BUSTURN : BUSTURN
bits : 16 - 19 (4 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.