\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : New BitField
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0VAL : Channel 0 Current Value
bits : 0 - 0 (1 bit)
access : read-only
CH1VAL : Channel 1 Current Value
bits : 1 - 1 (1 bit)
access : read-only
CH2VAL : Channel 2 Current Value
bits : 2 - 2 (1 bit)
access : read-only
CH3VAL : Channel 3 Current Value
bits : 3 - 3 (1 bit)
access : read-only
CH4VAL : Channel 4 Current Value
bits : 4 - 4 (1 bit)
access : read-only
CH5VAL : Channel 5 Current Value
bits : 5 - 5 (1 bit)
access : read-only
CH6VAL : Channel 6 Current Value
bits : 6 - 6 (1 bit)
access : read-only
CH7VAL : Channel 7 Current Value
bits : 7 - 7 (1 bit)
access : read-only
CH8VAL : Channel 8 Current Value
bits : 8 - 8 (1 bit)
access : read-only
CH9VAL : Channel 9 Current Value
bits : 9 - 9 (1 bit)
access : read-only
CH10VAL : Channel 10 Current Value
bits : 10 - 10 (1 bit)
access : read-only
CH11VAL : Channel 11 Current Value
bits : 11 - 11 (1 bit)
access : read-only
CTI Consumer register
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
FORCETX Consumer register
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : FORCETX async channel select
bits : 0 - 3 (4 bit)
access : read-write
RXDIS Consumer register
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : RXDIS async channel select
bits : 0 - 3 (4 bit)
access : read-write
RXEN Consumer register
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : RXEN async channel select
bits : 0 - 3 (4 bit)
access : read-write
TXEN Consumer register
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : TXEN async channel select
bits : 0 - 3 (4 bit)
access : read-write
TAMPERSRC25 consumer register
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : TAMPERSRC25 async channel select
bits : 0 - 3 (4 bit)
access : read-write
TAMPERSRC26 Consumer register
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : TAMPERSRC26 async channel select
bits : 0 - 3 (4 bit)
access : read-write
TAMPERSRC27 Consumer register
address_offset : 0x11C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : TAMPERSRC27 async channel select
bits : 0 - 3 (4 bit)
access : read-write
TAMPERSRC28 Consumer register
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : TAMPERSRC28 async channel select
bits : 0 - 3 (4 bit)
access : read-write
TAMPERSRC29 Consumer register
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : TAMPERSRC29 async channel select
bits : 0 - 3 (4 bit)
access : read-write
TAMPERSRC30 Consumer register
address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : TAMPERSRC30 async channel select
bits : 0 - 3 (4 bit)
access : read-write
TAMPERSRC31 Consumer register
address_offset : 0x12C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : TAMPERSRC31 async channel select
bits : 0 - 3 (4 bit)
access : read-write
IN0 consumer register
address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : IN0 async channel select
bits : 0 - 3 (4 bit)
access : read-write
IN1 Consumer register
address_offset : 0x134 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : IN1 async channel select
bits : 0 - 3 (4 bit)
access : read-write
OSCREQ consumer register
address_offset : 0x138 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : OSC async channel select
bits : 0 - 3 (4 bit)
access : read-write
TIMEOUT Consumer register
address_offset : 0x13C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : TIMEOUT async channel select
bits : 0 - 3 (4 bit)
access : read-write
No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0VAL : Channel Value
bits : 0 - 0 (1 bit)
access : read-only
CH1VAL : Channel Value
bits : 1 - 1 (1 bit)
access : read-only
CH2VAL : Channel Value
bits : 2 - 2 (1 bit)
access : read-only
CH3VAL : Channel Value
bits : 3 - 3 (1 bit)
access : read-only
CTI Consumer Register
address_offset : 0x140 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
CTI Consumer Register
address_offset : 0x144 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
CTI Consumer Register
address_offset : 0x148 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
CTI Consumer Register
address_offset : 0x14C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
M33 Consumer Register
address_offset : 0x150 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : M33 async channel select
bits : 0 - 3 (4 bit)
access : read-write
CC0 consumer register
address_offset : 0x154 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CC0 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : CC0 sync channel select
bits : 8 - 9 (2 bit)
access : read-write
CC1 Consumer register
address_offset : 0x158 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CC1 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : CC1 sync channel select
bits : 8 - 9 (2 bit)
access : read-write
CC2 Consumer register
address_offset : 0x15C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CC2 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : CC2 sync channel select
bits : 8 - 9 (2 bit)
access : read-write
DTI Consumer register
address_offset : 0x160 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
DTI Consumer register
address_offset : 0x164 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
DTI Consumer register
address_offset : 0x168 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
CC0 consumer register
address_offset : 0x16C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CC0 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : CC0 sync channel select
bits : 8 - 9 (2 bit)
access : read-write
CC1 Consumer register
address_offset : 0x170 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CC1 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : CC1 sync channel select
bits : 8 - 9 (2 bit)
access : read-write
CC2 Consumer register
address_offset : 0x174 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CC2 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : CC2 sync channel select
bits : 8 - 9 (2 bit)
access : read-write
DTI Consumer register
address_offset : 0x178 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
DTI Consumer register
address_offset : 0x17C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
End of enumeration elements list.
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOGICAL_ZERO
Logical 0
1 : A_NOR_B
A NOR B
2 : NOT_A_AND_B
(!A) AND B
3 : NOT_A
!A
4 : A_AND_NOT_B
A AND (!B)
5 : NOT_B
!B
6 : A_XOR_B
A XOR B
7 : A_NAND_B
A NAND B
8 : A_AND_B
A AND B
9 : A_XNOR_B
A XNOR B
10 : B
B
11 : NOT_A_OR_B
(!A) OR B
12 : A
A
13 : A_OR_NOT_B
A OR (!B)
14 : A_OR_B
A OR B
15 : LOGICAL_ONE
Logical 1
End of enumeration elements list.
AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write
DTI Consumer register
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
CC0 consumer register
address_offset : 0x184 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CC0 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : CC0 sync channel select
bits : 8 - 9 (2 bit)
access : read-write
CC1 Consumer register
address_offset : 0x188 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CC1 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : CC1 sync channel select
bits : 8 - 9 (2 bit)
access : read-write
CC2 Consumer register
address_offset : 0x18C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CC2 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : CC2 sync channel select
bits : 8 - 9 (2 bit)
access : read-write
DTI Consumer register
address_offset : 0x190 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
DTI Consumer register
address_offset : 0x194 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
DTI Consumer register
address_offset : 0x198 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
CC0 consumer register
address_offset : 0x19C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CC0 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : CC0 sync channel select
bits : 8 - 9 (2 bit)
access : read-write
CC1 Consumer register
address_offset : 0x1A0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CC1 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : CC1 sync channel select
bits : 8 - 9 (2 bit)
access : read-write
CC2 Consumer register
address_offset : 0x1A4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CC2 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : CC2 sync channel select
bits : 8 - 9 (2 bit)
access : read-write
DTI Consumer register
address_offset : 0x1A8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
DTI Consumer register
address_offset : 0x1AC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
DTI Consumer register
address_offset : 0x1B0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
CC0 consumer register
address_offset : 0x1B4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CC0 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : CC0 sync channel select
bits : 8 - 9 (2 bit)
access : read-write
CC1 Consumer register
address_offset : 0x1B8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CC1 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : CC1 sync channel select
bits : 8 - 9 (2 bit)
access : read-write
CC2 Consumer register
address_offset : 0x1BC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CC2 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : CC2 sync channel select
bits : 8 - 9 (2 bit)
access : read-write
No Description
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
End of enumeration elements list.
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOGICAL_ZERO
Logical 0
1 : A_NOR_B
A NOR B
2 : NOT_A_AND_B
(!A) AND B
3 : NOT_A
!A
4 : A_AND_NOT_B
A AND (!B)
5 : NOT_B
!B
6 : A_XOR_B
A XOR B
7 : A_NAND_B
A NAND B
8 : A_AND_B
A AND B
9 : A_XNOR_B
A XNOR B
10 : B
B
11 : NOT_A_OR_B
(!A) OR B
12 : A
A
13 : A_OR_NOT_B
A OR (!B)
14 : A_OR_B
A OR B
15 : LOGICAL_ONE
Logical 1
End of enumeration elements list.
AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write
DTI Consumer register
address_offset : 0x1C0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
DTI Consumer register
address_offset : 0x1C4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
DTI Consumer register
address_offset : 0x1C8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
CLK consumer register
address_offset : 0x1CC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CLK async channel select
bits : 0 - 3 (4 bit)
access : read-write
IR Consumer register
address_offset : 0x1D0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : IR async channel select
bits : 0 - 3 (4 bit)
access : read-write
RX Consumer register
address_offset : 0x1D4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : RX async channel select
bits : 0 - 3 (4 bit)
access : read-write
TRIGGER Consumer register
address_offset : 0x1D8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : TRIGGER async channel select
bits : 0 - 3 (4 bit)
access : read-write
ASYNCTRIG consumer register
address_offset : 0x1E8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : ASYNCTRIG async channel select
bits : 0 - 3 (4 bit)
access : read-write
ASYNCTRIG Consumer register
address_offset : 0x1EC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : ASYNCTRIG async channel select
bits : 0 - 3 (4 bit)
access : read-write
SYNCTRIG Consumer register
address_offset : 0x1F0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPRSSEL : SYNCTRIG sync channel select
bits : 8 - 9 (2 bit)
access : read-write
SYNCTRIG Consumer register
address_offset : 0x1F4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPRSSEL : SYNCTRIG sync channel select
bits : 8 - 9 (2 bit)
access : read-write
SRC0 consumer register
address_offset : 0x1F8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : SRC0 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SRC1 Consumer register
address_offset : 0x1FC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : SRC1 async channel select
bits : 0 - 3 (4 bit)
access : read-write
No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
End of enumeration elements list.
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOGICAL_ZERO
Logical 0
1 : A_NOR_B
A NOR B
2 : NOT_A_AND_B
(!A) AND B
3 : NOT_A
!A
4 : A_AND_NOT_B
A AND (!B)
5 : NOT_B
!B
6 : A_XOR_B
A XOR B
7 : A_NAND_B
A NAND B
8 : A_AND_B
A AND B
9 : A_XNOR_B
A XNOR B
10 : B
B
11 : NOT_A_OR_B
(!A) OR B
12 : A
A
13 : A_OR_NOT_B
A OR (!B)
14 : A_OR_B
A OR B
15 : LOGICAL_ONE
Logical 1
End of enumeration elements list.
AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write
SRC0 consumer register
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : SRC0 async channel select
bits : 0 - 3 (4 bit)
access : read-write
SRC1 Consumer register
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : SRC1 async channel select
bits : 0 - 3 (4 bit)
access : read-write
No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
End of enumeration elements list.
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOGICAL_ZERO
Logical 0
1 : A_NOR_B
A NOR B
2 : NOT_A_AND_B
(!A) AND B
3 : NOT_A
!A
4 : A_AND_NOT_B
A AND (!B)
5 : NOT_B
!B
6 : A_XOR_B
A XOR B
7 : A_NAND_B
A NAND B
8 : A_AND_B
A AND B
9 : A_XNOR_B
A XNOR B
10 : B
B
11 : NOT_A_OR_B
(!A) OR B
12 : A
A
13 : A_OR_NOT_B
A OR (!B)
14 : A_OR_B
A OR B
15 : LOGICAL_ONE
Logical 1
End of enumeration elements list.
AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write
No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
End of enumeration elements list.
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOGICAL_ZERO
Logical 0
1 : A_NOR_B
A NOR B
2 : NOT_A_AND_B
(!A) AND B
3 : NOT_A
!A
4 : A_AND_NOT_B
A AND (!B)
5 : NOT_B
!B
6 : A_XOR_B
A XOR B
7 : A_NAND_B
A NAND B
8 : A_AND_B
A AND B
9 : A_XNOR_B
A XNOR B
10 : B
B
11 : NOT_A_OR_B
(!A) OR B
12 : A
A
13 : A_OR_NOT_B
A OR (!B)
14 : A_OR_B
A OR B
15 : LOGICAL_ONE
Logical 1
End of enumeration elements list.
AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write
No Description
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
End of enumeration elements list.
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOGICAL_ZERO
Logical 0
1 : A_NOR_B
A NOR B
2 : NOT_A_AND_B
(!A) AND B
3 : NOT_A
!A
4 : A_AND_NOT_B
A AND (!B)
5 : NOT_B
!B
6 : A_XOR_B
A XOR B
7 : A_NAND_B
A NAND B
8 : A_AND_B
A AND B
9 : A_XNOR_B
A XNOR B
10 : B
B
11 : NOT_A_OR_B
(!A) OR B
12 : A
A
13 : A_OR_NOT_B
A OR (!B)
14 : A_OR_B
A OR B
15 : LOGICAL_ONE
Logical 1
End of enumeration elements list.
AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write
No Description
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
End of enumeration elements list.
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOGICAL_ZERO
Logical 0
1 : A_NOR_B
A NOR B
2 : NOT_A_AND_B
(!A) AND B
3 : NOT_A
!A
4 : A_AND_NOT_B
A AND (!B)
5 : NOT_B
!B
6 : A_XOR_B
A XOR B
7 : A_NAND_B
A NAND B
8 : A_AND_B
A AND B
9 : A_XNOR_B
A XNOR B
10 : B
B
11 : NOT_A_OR_B
(!A) OR B
12 : A
A
13 : A_OR_NOT_B
A OR (!B)
14 : A_OR_B
A OR B
15 : LOGICAL_ONE
Logical 1
End of enumeration elements list.
AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write
No Description
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
End of enumeration elements list.
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOGICAL_ZERO
Logical 0
1 : A_NOR_B
A NOR B
2 : NOT_A_AND_B
(!A) AND B
3 : NOT_A
!A
4 : A_AND_NOT_B
A AND (!B)
5 : NOT_B
!B
6 : A_XOR_B
A XOR B
7 : A_NAND_B
A NAND B
8 : A_AND_B
A AND B
9 : A_XNOR_B
A XNOR B
10 : B
B
11 : NOT_A_OR_B
(!A) OR B
12 : A
A
13 : A_OR_NOT_B
A OR (!B)
14 : A_OR_B
A OR B
15 : LOGICAL_ONE
Logical 1
End of enumeration elements list.
AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write
No Description
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
End of enumeration elements list.
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOGICAL_ZERO
Logical 0
1 : A_NOR_B
A NOR B
2 : NOT_A_AND_B
(!A) AND B
3 : NOT_A
!A
4 : A_AND_NOT_B
A AND (!B)
5 : NOT_B
!B
6 : A_XOR_B
A XOR B
7 : A_NAND_B
A NAND B
8 : A_AND_B
A AND B
9 : A_XNOR_B
A XNOR B
10 : B
B
11 : NOT_A_OR_B
(!A) OR B
12 : A
A
13 : A_OR_NOT_B
A OR (!B)
14 : A_OR_B
A OR B
15 : LOGICAL_ONE
Logical 1
End of enumeration elements list.
AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write
No Description
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
End of enumeration elements list.
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOGICAL_ZERO
Logical 0
1 : A_NOR_B
A NOR B
2 : NOT_A_AND_B
(!A) AND B
3 : NOT_A
!A
4 : A_AND_NOT_B
A AND (!B)
5 : NOT_B
!B
6 : A_XOR_B
A XOR B
7 : A_NAND_B
A NAND B
8 : A_AND_B
A AND B
9 : A_XNOR_B
A XNOR B
10 : B
B
11 : NOT_A_OR_B
(!A) OR B
12 : A
A
13 : A_OR_NOT_B
A OR (!B)
14 : A_OR_B
A OR B
15 : LOGICAL_ONE
Logical 1
End of enumeration elements list.
AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write
No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
End of enumeration elements list.
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOGICAL_ZERO
Logical 0
1 : A_NOR_B
A NOR B
2 : NOT_A_AND_B
(!A) AND B
3 : NOT_A
!A
4 : A_AND_NOT_B
A AND (!B)
5 : NOT_B
!B
6 : A_XOR_B
A XOR B
7 : A_NAND_B
A NAND B
8 : A_AND_B
A AND B
9 : A_XNOR_B
A XNOR B
10 : B
B
11 : NOT_A_OR_B
(!A) OR B
12 : A
A
13 : A_OR_NOT_B
A OR (!B)
14 : A_OR_B
A OR B
15 : LOGICAL_ONE
Logical 1
End of enumeration elements list.
AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write
No Description
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
End of enumeration elements list.
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOGICAL_ZERO
Logical 0
1 : A_NOR_B
A NOR B
2 : NOT_A_AND_B
(!A) AND B
3 : NOT_A
!A
4 : A_AND_NOT_B
A AND (!B)
5 : NOT_B
!B
6 : A_XOR_B
A XOR B
7 : A_NAND_B
A NAND B
8 : A_AND_B
A AND B
9 : A_XNOR_B
A XNOR B
10 : B
B
11 : NOT_A_OR_B
(!A) OR B
12 : A
A
13 : A_OR_NOT_B
A OR (!B)
14 : A_OR_B
A OR B
15 : LOGICAL_ONE
Logical 1
End of enumeration elements list.
AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write
No Description
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
End of enumeration elements list.
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
No Description
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
End of enumeration elements list.
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
No Description
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
End of enumeration elements list.
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
No Description
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
End of enumeration elements list.
SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write
CALDN consumer register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CALDN async channel select
bits : 0 - 3 (4 bit)
access : read-write
CALUP Consumer register
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CALUP async channel select
bits : 0 - 3 (4 bit)
access : read-write
CLK consumer register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CLK async channel select
bits : 0 - 3 (4 bit)
access : read-write
RX Consumer register
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : RX async channel select
bits : 0 - 3 (4 bit)
access : read-write
TRIGGER Consumer register
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : TRIGGER async channel select
bits : 0 - 3 (4 bit)
access : read-write
CLK consumer register
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CLK async channel select
bits : 0 - 3 (4 bit)
access : read-write
RX Consumer register
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : RX async channel select
bits : 0 - 3 (4 bit)
access : read-write
TRIGGER Consumer register
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : TRIGGER async channel select
bits : 0 - 3 (4 bit)
access : read-write
CLK consumer register
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CLK async channel select
bits : 0 - 3 (4 bit)
access : read-write
RX Consumer register
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : RX async channel select
bits : 0 - 3 (4 bit)
access : read-write
No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0PULSE : Channel pulse
bits : 0 - 0 (1 bit)
access : write-only
CH1PULSE : Channel pulse
bits : 1 - 1 (1 bit)
access : write-only
CH2PULSE : Channel pulse
bits : 2 - 2 (1 bit)
access : write-only
CH3PULSE : Channel pulse
bits : 3 - 3 (1 bit)
access : write-only
CH4PULSE : Channel pulse
bits : 4 - 4 (1 bit)
access : write-only
CH5PULSE : Channel pulse
bits : 5 - 5 (1 bit)
access : write-only
CH6PULSE : Channel pulse
bits : 6 - 6 (1 bit)
access : write-only
CH7PULSE : Channel pulse
bits : 7 - 7 (1 bit)
access : write-only
CH8PULSE : Channel pulse
bits : 8 - 8 (1 bit)
access : write-only
CH9PULSE : Channel pulse
bits : 9 - 9 (1 bit)
access : write-only
CH10PULSE : Channel pulse
bits : 10 - 10 (1 bit)
access : write-only
CH11PULSE : Channel pulse
bits : 11 - 11 (1 bit)
access : write-only
TRIGGER Consumer register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : TRIGGER async channel select
bits : 0 - 3 (4 bit)
access : read-write
SCAN consumer register
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : SCAN async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : SCAN sync channel select
bits : 8 - 9 (2 bit)
access : read-write
SINGLE Consumer register
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : SINGLE async channel select
bits : 0 - 3 (4 bit)
access : read-write
SPRSSEL : SINGLE sync channel select
bits : 8 - 9 (2 bit)
access : read-write
DMAREQ0 consumer register
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DMAREQ0 async channel select
bits : 0 - 3 (4 bit)
access : read-write
DMAREQ1 Consumer register
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DMAREQ1 async channel select
bits : 0 - 3 (4 bit)
access : read-write
START Consumer register
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : START async channel select
bits : 0 - 3 (4 bit)
access : read-write
CLEAR consumer register
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CLEAR async channel select
bits : 0 - 3 (4 bit)
access : read-write
START Consumer register
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : START async channel select
bits : 0 - 3 (4 bit)
access : read-write
STOP Consumer register
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : STOP async channel select
bits : 0 - 3 (4 bit)
access : read-write
MODEM DIN consumer register
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : DIN async channel select
bits : 0 - 3 (4 bit)
access : read-write
S0IN consumer register
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : S0IN async channel select
bits : 0 - 3 (4 bit)
access : read-write
No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0LEVEL : Channel Level
bits : 0 - 0 (1 bit)
access : read-write
CH1LEVEL : Channel Level
bits : 1 - 1 (1 bit)
access : read-write
CH2LEVEL : Channel Level
bits : 2 - 2 (1 bit)
access : read-write
CH3LEVEL : Channel Level
bits : 3 - 3 (1 bit)
access : read-write
CH4LEVEL : Channel Level
bits : 4 - 4 (1 bit)
access : read-write
CH5LEVEL : Channel Level
bits : 5 - 5 (1 bit)
access : read-write
CH6LEVEL : Channel Level
bits : 6 - 6 (1 bit)
access : read-write
CH7LEVEL : Channel Level
bits : 7 - 7 (1 bit)
access : read-write
CH8LEVEL : Channel Level
bits : 8 - 8 (1 bit)
access : read-write
CH9LEVEL : Channel Level
bits : 9 - 9 (1 bit)
access : read-write
CH10LEVEL : Channel Level
bits : 10 - 10 (1 bit)
access : read-write
CH11LEVEL : Channel Level
bits : 11 - 11 (1 bit)
access : read-write
S1IN Consumer register
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : S1IN async channel select
bits : 0 - 3 (4 bit)
access : read-write
CLR consumer register
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CLR async channel select
bits : 0 - 3 (4 bit)
access : read-write
CTI Consumer register
address_offset : 0xF4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
CTI Consumer register
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
CTI Consumer register
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSEL : CTI async channel select
bits : 0 - 3 (4 bit)
access : read-write
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