Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP Version ID
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LOCKKEY : Configuration Lock Key
bits : 0 - 15 (16 bit)
access : write-only
Enumeration:
37879 : UNLOCK
Write this value to unlock
End of enumeration elements list.
No Description
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Clock Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
DPLLREFCLK is not clocked
1 : HFXO
HFXO is clocking DPLLREFCLK
2 : LFXO
LFXO is clocking DPLLREFCLK
3 : CLKIN0
CLKIN0 is clocking DPLLREFCLK
End of enumeration elements list.
No Description
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Clock Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
1 : HFRCODPLL
HFRCODPLL is clocking EM01GRPACLK
2 : HFXO
HFXO is clocking EM01GRPACLK
3 : FSRCO
FSRCO is clocking EM01GRPACLK
4 : HFRCOEM23
HFRCOEM23 is clocking EM01GRPACLK
5 : HFRCODPLLRT
HFRCODPLL (retimed) is clocking EM01GRPACLK. Check with datasheet for frequency limitation when using retiming with voltage scaling.
6 : HFXORT
HFXO (retimed) is clocking EM01GRPACLK. Check with datasheet for frequency limitation when using retiming with voltage scaling.
End of enumeration elements list.
No Description
address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Clock Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
1 : HFRCODPLL
HFRCODPLL is clocking EM01GRPCCLK
2 : HFXO
HFXO is clocking EM01GRPCCLK
3 : FSRCO
FSRCO is clocking EM01GRPCCLK
4 : HFRCOEM23
HFRCOEM23 is clocking EM01GRPCCLK
5 : HFRCODPLLRT
HFRCODPLL (retimed) is clocking EM01GRPCCLK. Check with datasheet for frequency limitation when using retiming with voltage scaling.
6 : HFXORT
HFXO (retimed) is clocking EM01GRPCCLK. Check with datasheet for frequency limitation when using retiming with voltage scaling.
End of enumeration elements list.
No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LOCKKEY : Configuration Lock Key
bits : 0 - 15 (16 bit)
access : write-only
Enumeration:
37879 : UNLOCK
Write this value to unlock
End of enumeration elements list.
No Description
address_offset : 0x140 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Clock Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
1 : LFRCO
LFRCO is clocking EM23GRPACLK
2 : LFXO
LFXO is clocking EM23GRPACLK
3 : ULFRCO
ULFRCO is clocking EM23GRPACLK
End of enumeration elements list.
No Description
address_offset : 0x160 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Clock Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
1 : LFRCO
LFRCO is clocking EM4GRPACLK
2 : LFXO
LFXO is clocking EM4GRPACLK
3 : ULFRCO
ULFRCO is clocking EM4GRPACLK
End of enumeration elements list.
No Description
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Clock Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
1 : EM01GRPACLK
EM01GRPACLK is clocking IADCCLK
2 : FSRCO
FSRCO is clocking IADCCLK
3 : HFRCOEM23
HFRCOEM23 is clocking IADCCLK
End of enumeration elements list.
No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALRDY : Calibration Ready Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
CALOF : Calibration Overflow Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write
No Description
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Clock Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
1 : LFRCO
LFRCO is clocking WDOG0CLK
2 : LFXO
LFXO is clocking WDOG0CLK
3 : ULFRCO
ULFRCO is clocking WDOG0CLK
4 : HCLKDIV1024
HCLKDIV1024 is clocking WDOG0CLK
End of enumeration elements list.
No Description
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Clock Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
1 : LFRCO
LFRCO is clocking WDOG0CLK
2 : LFXO
LFXO is clocking WDOG0CLK
3 : ULFRCO
ULFRCO is clocking WDOG0CLK
4 : HCLKDIV1024
HCLKDIV1024 is clocking WDOG0CLK
End of enumeration elements list.
No Description
address_offset : 0x220 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Clock Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DISABLED
EUSART0 is not clocked
1 : EM01GRPCCLK
EM01GRPCCLK is clocking EUSART0
2 : HFRCOEM23
HFRCOEM23 is clocking EUSART0
3 : LFRCO
LFRCO is clocking EUSART0
4 : LFXO
LFXO is clocking EUSART0
End of enumeration elements list.
No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALRDY : Calibration Ready Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
CALOF : Calibration Overflow Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
No Description
address_offset : 0x240 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Clock Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
1 : LFRCO
LFRCO is clocking SYSRTC0CLK
2 : LFXO
LFXO is clocking SYSRTC0CLK
3 : ULFRCO
ULFRCO is clocking SYSRTC0CLK
End of enumeration elements list.
No Description
address_offset : 0x250 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Clock Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
1 : LFRCO
LFRCO is clocking LCDCLK
2 : LFXO
LFXO is clocking LCDCLK
3 : ULFRCO
ULFRCO is clocking LCDCLK
End of enumeration elements list.
No Description
address_offset : 0x260 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Clock Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DISABLED
VDAC is not clocked
1 : EM01GRPACLK
EM01GRPACLK is clocking VDAC
2 : EM23GRPACLK
EM23GRPACLK is clocking VDAC
3 : FSRCO
FSRCO is clocking VDAC
4 : HFRCOEM23
HFRCOEM23 is clocking VDAC
End of enumeration elements list.
No Description
address_offset : 0x270 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Clock Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
PCNT0 is not clocked
1 : EM23GRPACLK
EM23GRPACLK is clocking PCNT0
2 : PCNTS0
External pin PCNT_S0 is clocking PCNT0
End of enumeration elements list.
No Description
address_offset : 0x280 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable
bits : 0 - 0 (1 bit)
access : read-write
DBGCLK : Enable Clock for Debugger
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x290 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Clock Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
1 : FSRCO
FSRCO is clocking LESENSEHFCLK
2 : HFRCOEM23
HFRCOEM23 is clocking LESENSEHFCLK
End of enumeration elements list.
No Description
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CALSTART : Calibration Start
bits : 0 - 0 (1 bit)
access : write-only
CALSTOP : Calibration Stop
bits : 1 - 1 (1 bit)
access : write-only
No Description
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALTOP : Calibration Counter Top Value
bits : 0 - 19 (20 bit)
access : read-write
CONT : Continuous Calibration
bits : 23 - 23 (1 bit)
access : read-write
UPSEL : Calibration Up-counter Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : DISABLED
Up-counter is not clocked
1 : PRS
PRS CMU_CALUP consumer is clocking up-counter
2 : HFXO
HFXO is clocking up-counter
3 : LFXO
LFXO is clocking up-counter
4 : HFRCODPLL
HFRCODPLL is clocking up-counter
5 : HFRCOEM23
HFRCOEM23 is clocking up-counter
8 : FSRCO
FSRCO is clocking up-counter
9 : LFRCO
LFRCO is clocking up-counter
10 : ULFRCO
ULFRCO is clocking up-counter
End of enumeration elements list.
DOWNSEL : Calibration Down-counter Select
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : DISABLED
Down-counter is not clocked
1 : HCLK
HCLK is clocking down-counter
2 : PRS
PRS CMU_CALDN consumer is clocking down-counter
3 : HFXO
HFXO is clocking down-counter
4 : LFXO
LFXO is clocking down-counter
5 : HFRCODPLL
HFRCODPLL is clocking down-counter
6 : HFRCOEM23
HFRCOEM23 is clocking down-counter
9 : FSRCO
FSRCO is clocking down-counter
10 : LFRCO
LFRCO is clocking down-counter
11 : ULFRCO
ULFRCO is clocking down-counter
End of enumeration elements list.
No Description
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CALCNT : Calibration Result Counter Value
bits : 0 - 19 (20 bit)
access : read-only
No Description
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDMA : Enable Bus Clock
bits : 0 - 0 (1 bit)
access : read-write
LDMAXBAR : Enable Bus Clock
bits : 1 - 1 (1 bit)
access : read-write
RADIOAES : Enable Bus Clock
bits : 2 - 2 (1 bit)
access : read-write
GPCRC : Enable Bus Clock
bits : 3 - 3 (1 bit)
access : read-write
TIMER0 : Enable Bus Clock
bits : 4 - 4 (1 bit)
access : read-write
TIMER1 : Enable Bus Clock
bits : 5 - 5 (1 bit)
access : read-write
TIMER2 : Enable Bus Clock
bits : 6 - 6 (1 bit)
access : read-write
TIMER3 : Enable Bus Clock
bits : 7 - 7 (1 bit)
access : read-write
TIMER4 : Enable Bus Clock
bits : 8 - 8 (1 bit)
access : read-write
USART0 : Enable Bus Clock
bits : 9 - 9 (1 bit)
access : read-write
IADC0 : Enable Bus Clock
bits : 10 - 10 (1 bit)
access : read-write
AMUXCP0 : Enable Bus Clock
bits : 11 - 11 (1 bit)
access : read-write
LETIMER0 : Enable Bus Clock
bits : 12 - 12 (1 bit)
access : read-write
WDOG0 : Enable Bus Clock
bits : 13 - 13 (1 bit)
access : read-write
I2C0 : Enable Bus Clock
bits : 14 - 14 (1 bit)
access : read-write
I2C1 : Enable Bus Clock
bits : 15 - 15 (1 bit)
access : read-write
SYSCFG : Enable Bus Clock
bits : 16 - 16 (1 bit)
access : read-write
DPLL0 : Enable Bus Clock
bits : 17 - 17 (1 bit)
access : read-write
HFRCO0 : Enable Bus Clock
bits : 18 - 18 (1 bit)
access : read-write
HFRCOEM23 : Enable Bus Clock
bits : 19 - 19 (1 bit)
access : read-write
HFXO0 : Enable Bus Clock
bits : 20 - 20 (1 bit)
access : read-write
FSRCO : Enable Bus Clock
bits : 21 - 21 (1 bit)
access : read-write
LFRCO : Enable Bus Clock
bits : 22 - 22 (1 bit)
access : read-write
LFXO : Enable Bus Clock
bits : 23 - 23 (1 bit)
access : read-write
ULFRCO : Enable Bus Clock
bits : 24 - 24 (1 bit)
access : read-write
LESENSE : Enable Bus Clock
bits : 25 - 25 (1 bit)
access : read-write
GPIO : Enable Bus Clock
bits : 26 - 26 (1 bit)
access : read-write
PRS : Enable Bus Clock
bits : 27 - 27 (1 bit)
access : read-write
BURAM : Enable Bus Clock
bits : 28 - 28 (1 bit)
access : read-write
BURTC : Enable Bus Clock
bits : 29 - 29 (1 bit)
access : read-write
SYSRTC0 : Enable Bus Clock
bits : 30 - 30 (1 bit)
access : read-write
DCDC : Enable Bus Clock
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGC : Enable Bus Clock
bits : 0 - 0 (1 bit)
access : read-write
MODEM : Enable Bus Clock
bits : 1 - 1 (1 bit)
access : read-write
RFCRC : Enable Bus Clock
bits : 2 - 2 (1 bit)
access : read-write
FRC : Enable Bus Clock
bits : 3 - 3 (1 bit)
access : read-write
PROTIMER : Enable Bus Clock
bits : 4 - 4 (1 bit)
access : read-write
RAC : Enable Bus Clock
bits : 5 - 5 (1 bit)
access : read-write
SYNTH : Enable Bus Clock
bits : 6 - 6 (1 bit)
access : read-write
RFSCRATCHPAD : Enable Bus Clock
bits : 7 - 7 (1 bit)
access : read-write
HOSTMAILBOX : Enable Bus Clock
bits : 8 - 8 (1 bit)
access : read-write
RFMAILBOX : Enable Bus Clock
bits : 9 - 9 (1 bit)
access : read-write
SEMAILBOXHOST : Enable Bus Clock
bits : 10 - 10 (1 bit)
access : read-write
BUFC : Enable Bus Clock
bits : 11 - 11 (1 bit)
access : read-write
LCD : Enable Bus Clock
bits : 12 - 12 (1 bit)
access : read-write
KEYSCAN : Enable Bus Clock
bits : 13 - 13 (1 bit)
access : read-write
SMU : Enable Bus Clock
bits : 14 - 14 (1 bit)
access : read-write
ICACHE0 : Enable Bus Clock
bits : 15 - 15 (1 bit)
access : read-write
MSC : Enable Bus Clock
bits : 16 - 16 (1 bit)
access : read-write
WDOG1 : Enable Bus Clock
bits : 17 - 17 (1 bit)
access : read-write
ACMP0 : Enable Bus Clock
bits : 18 - 18 (1 bit)
access : read-write
ACMP1 : Enable Bus Clock
bits : 19 - 19 (1 bit)
access : read-write
VDAC0 : Enable Bus Clock
bits : 20 - 20 (1 bit)
access : read-write
PCNT0 : Enable Bus Clock
bits : 21 - 21 (1 bit)
access : read-write
EUSART0 : Enable Bus Clock
bits : 22 - 22 (1 bit)
access : read-write
EUSART1 : Enable Bus Clock
bits : 23 - 23 (1 bit)
access : read-write
EUSART2 : Enable Bus Clock
bits : 24 - 24 (1 bit)
access : read-write
RFECA0 : Enable Bus Clock
bits : 25 - 25 (1 bit)
access : read-write
RFECA1 : Enable Bus Clock
bits : 26 - 26 (1 bit)
access : read-write
DMEM : Enable Bus Clock
bits : 27 - 27 (1 bit)
access : read-write
ECAIFADC : Enable Bus Clock
bits : 28 - 28 (1 bit)
access : read-write
No Description
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Clock Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
1 : FSRCO
FSRCO is clocking SYSCLK
2 : HFRCODPLL
HFRCODPLL is clocking SYSCLK
3 : HFXO
HFXO is clocking SYSCLK
4 : CLKIN0
CLKIN0 is clocking SYSCLK
End of enumeration elements list.
PCLKPRESC : PCLK Prescaler
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DIV1
PCLK is HCLK divided by 1
1 : DIV2
PCLK is HCLK divided by 2
End of enumeration elements list.
HCLKPRESC : HCLK Prescaler
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : DIV1
HCLK is SYSCLK divided by 1
1 : DIV2
HCLK is SYSCLK divided by 2
3 : DIV4
HCLK is SYSCLK divided by 4
7 : DIV8
HCLK is SYSCLK divided by 8
15 : DIV16
HCLK is SYSCLK divided by 16
End of enumeration elements list.
RHCLKPRESC : Radio HCLK Prescaler
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DIV1
Radio HCLK is SYSCLK divided by 1
1 : DIV2
Radio HCLK is SYSCLK divided by 2
End of enumeration elements list.
No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CALRDY : Calibration Ready
bits : 0 - 0 (1 bit)
access : read-only
WDOGLOCK : Configuration Lock Status for WDOG
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : UNLOCKED
WDOG configuration lock is unlocked
1 : LOCKED
WDOG configuration lock is locked
End of enumeration elements list.
LOCK : Configuration Lock Status
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : UNLOCKED
Configuration lock is unlocked
1 : LOCKED
Configuration lock is locked
End of enumeration elements list.
No Description
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : TRACECLK Prescaler
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : DIV1
TRACECLK is SYSCLK divided by 1
1 : DIV2
TRACECLK is SYSCLK divided by 2
3 : DIV4
TRACECLK is SYSCLK divided by 4
End of enumeration elements list.
No Description
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKOUTSEL0 : Clock Output Select 0
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : DISABLED
CLKOUT0 is not clocked
1 : HCLK
HCLK is clocking CLKOUT0
2 : HFEXPCLK
HFEXPCLK is clocking CLKOUT0
3 : ULFRCO
ULFRCO is clocking CLKOUT0
4 : LFRCO
LFRCO is clocking CLKOUT0
5 : LFXO
LFXO is clocking CLKOUT0
6 : HFRCODPLL
HFRCODPLL is clocking CLKOUT0
7 : HFXO
HFXO is clocking CLKOUT0
8 : FSRCO
FSRCO is clocking CLKOUT0
9 : HFRCOEM23
HFRCOEM23 is clocking CLKOUT0
End of enumeration elements list.
CLKOUTSEL1 : Clock Output Select 1
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : DISABLED
CLKOUT1 is not clocked
1 : HCLK
HCLK is clocking CLKOUT1
2 : HFEXPCLK
HFEXPCLK is clocking CLKOUT1
3 : ULFRCO
ULFRCO is clocking CLKOUT1
4 : LFRCO
LFRCO is clocking CLKOUT1
5 : LFXO
LFXO is clocking CLKOUT1
6 : HFRCODPLL
HFRCODPLL is clocking CLKOUT1
7 : HFXO
HFXO is clocking CLKOUT1
8 : FSRCO
FSRCO is clocking CLKOUT1
9 : HFRCOEM23
HFRCOEM23 is clocking CLKOUT1
End of enumeration elements list.
CLKOUTSEL2 : Clock Output Select 2
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : DISABLED
CLKOUT2 is not clocked
1 : HCLK
HCLK is clocking CLKOUT2
2 : HFEXPCLK
HFEXPCLK is clocking CLKOUT2
3 : ULFRCO
ULFRCO is clocking CLKOUT2
4 : LFRCO
LFRCO is clocking CLKOUT2
5 : LFXO
LFXO is clocking CLKOUT2
6 : HFRCODPLL
HFRCODPLL is clocking CLKOUT2
7 : HFXO
HFXO is clocking CLKOUT2
8 : FSRCO
FSRCO is clocking CLKOUT2
9 : HFRCOEM23
HFRCOEM23 is clocking CLKOUT2
End of enumeration elements list.
PRESC : EXPORTCLK Prescaler
bits : 24 - 28 (5 bit)
access : read-write
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