\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
A write access to any address in this area will be mapped to the TX FIFO (only for the payload). A read access to any address in this area will be mapped to the RX FIFO (only for the payload). Using an address range (16 x 32-bit) rather than one single address mapped to the FIFO allows using incremental bursts.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO : FIFO
bits : 0 - 31 (32 bit)
access : read-write
TX Status register.
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REMBYTES : REMBYTES
bits : 0 - 15 (16 bit)
access : read-only
MSGINFO : MSGINFO
bits : 16 - 19 (4 bit)
access : read-only
TXINT : TXINT
bits : 20 - 20 (1 bit)
access : read-only
TXFULL : TXFULL
bits : 21 - 21 (1 bit)
access : read-only
TXERROR : TXERROR
bits : 23 - 23 (1 bit)
access : read-only
RX Status register.
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REMBYTES : REMBYTES
bits : 0 - 15 (16 bit)
access : read-only
MSGINFO : MSGINFO
bits : 16 - 19 (4 bit)
access : read-only
RXINT : RXINT
bits : 20 - 20 (1 bit)
access : read-only
RXEMPTY : RXEMPTY
bits : 21 - 21 (1 bit)
access : read-only
RXHDR : RXHDR
bits : 22 - 22 (1 bit)
access : read-only
RXERROR : RXERROR
bits : 23 - 23 (1 bit)
access : read-only
TX Protection register.
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UNPROTECTED : UNPROTECTED
bits : 21 - 21 (1 bit)
access : read-only
PRIVILEGED : PRIVILEGED
bits : 22 - 22 (1 bit)
access : read-only
NONSECURE : NONSECURE
bits : 23 - 23 (1 bit)
access : read-only
USER : USER
bits : 24 - 31 (8 bit)
access : read-only
RX Protection register.
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UNPROTECTED : UNPROTECTED
bits : 21 - 21 (1 bit)
access : read-only
PRIVILEGED : PRIVILEGED
bits : 22 - 22 (1 bit)
access : read-only
NONSECURE : NONSECURE
bits : 23 - 23 (1 bit)
access : read-only
USER : USER
bits : 24 - 31 (8 bit)
access : read-only
A write access to this register will be mapped to the TX FIFO (only for header).
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXHEADER : TXHEADER
bits : 0 - 31 (32 bit)
access : write-only
A read access to this register will be mapped to the RX FIFO (only for the header).
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXHEADER : RXHEADER
bits : 0 - 31 (32 bit)
access : read-only
Configuration register.
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXINTEN : TXINTEN
bits : 0 - 0 (1 bit)
access : read-write
RXINTEN : RXINTEN
bits : 1 - 1 (1 bit)
access : read-write
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