\n

PRORTC_NS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

IPVERSION

STATUS

IF

IEN

PRECNT

CNT

COMBCNT

SYNCBUSY

LOCK

CC0_CTRL

CC0_OCVALUE

CC0_ICVALUE

CC1_CTRL

EN

CC1_OCVALUE

CC1_ICVALUE

CFG

CMD


IPVERSION

No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : IP VERSION
bits : 0 - 31 (32 bit)
access : read-only


STATUS

No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUNNING RTCCLOCKSTATUS

RUNNING : RTCC running status
bits : 0 - 0 (1 bit)
access : read-only

RTCCLOCKSTATUS : Lock Status
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

RTCC registers are unlocked

1 : LOCKED

RTCC registers are locked

End of enumeration elements list.


IF

No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF CNTTICK CC0 CC1

OF : Overflow Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

CNTTICK : Main counter tick
bits : 1 - 1 (1 bit)
access : read-write

CC0 : CC Channel n Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write

CC1 : CC Channel n Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write


IEN

No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF CNTTICK CC0 CC1

OF : OF Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

CNTTICK : CNTTICK Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

CC0 : CC Channel n Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

CC1 : CC Channel n Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write


PRECNT

No Description
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRECNT PRECNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRECNT

PRECNT : Pre-Counter Value
bits : 0 - 14 (15 bit)
access : read-write


CNT

No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter Value
bits : 0 - 31 (32 bit)
access : read-write


COMBCNT

No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

COMBCNT COMBCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRECNT CNTLSB

PRECNT : Pre-Counter Value
bits : 0 - 14 (15 bit)
access : read-only

CNTLSB : Counter Value
bits : 15 - 31 (17 bit)
access : read-only


SYNCBUSY

No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START STOP PRECNT CNT

START : Sync busy for START
bits : 0 - 0 (1 bit)
access : read-only

STOP : Sync busy for STOP
bits : 1 - 1 (1 bit)
access : read-only

PRECNT : Sync busy for PRECNT
bits : 2 - 2 (1 bit)
access : read-only

CNT : Sync busy for CNT
bits : 3 - 3 (1 bit)
access : read-only


LOCK

No Description
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : Configuration Lock Key
bits : 0 - 15 (16 bit)
access : write-only

Enumeration:

44776 : UNLOCK

Write to unlock RTCC lockable registers

End of enumeration elements list.


CC0_CTRL

No Description
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC0_CTRL CC0_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE CMOA COMPBASE ICEDGE

MODE : CC Channel Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : OFF

Compare/Capture channel turned off

1 : INPUTCAPTURE

Input capture

2 : OUTPUTCOMPARE

Output compare

End of enumeration elements list.

CMOA : Compare Match Output Action
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0 : PULSE

A single clock cycle pulse is generated on output

1 : TOGGLE

Toggle output on compare match

2 : CLEAR

Clear output on compare match

3 : SET

Set output on compare match

End of enumeration elements list.

COMPBASE : Capture compare channel comparison base.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : CNT

RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register.

1 : PRECNT

Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT.

End of enumeration elements list.

ICEDGE : Input Capture Edge Select
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

0 : RISING

Rising edges detected

1 : FALLING

Falling edges detected

2 : BOTH

Both edges detected

3 : NONE

No edge detection, signal is left as it is

End of enumeration elements list.


CC0_OCVALUE

No Description
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC0_OCVALUE CC0_OCVALUE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OC

OC : Output Compare Value
bits : 0 - 31 (32 bit)
access : read-write


CC0_ICVALUE

No Description
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CC0_ICVALUE CC0_ICVALUE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC

IC : Input Capture Value
bits : 0 - 31 (32 bit)
access : read-only


CC1_CTRL

No Description
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC1_CTRL CC1_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE CMOA COMPBASE ICEDGE

MODE : CC Channel Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : OFF

Compare/Capture channel turned off

1 : INPUTCAPTURE

Input capture

2 : OUTPUTCOMPARE

Output compare

End of enumeration elements list.

CMOA : Compare Match Output Action
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0 : PULSE

A single clock cycle pulse is generated on output

1 : TOGGLE

Toggle output on compare match

2 : CLEAR

Clear output on compare match

3 : SET

Set output on compare match

End of enumeration elements list.

COMPBASE : Capture compare channel comparison base.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : CNT

RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register.

1 : PRECNT

Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT.

End of enumeration elements list.

ICEDGE : Input Capture Edge Select
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

0 : RISING

Rising edges detected

1 : FALLING

Falling edges detected

2 : BOTH

Both edges detected

3 : NONE

No edge detection, signal is left as it is

End of enumeration elements list.


EN

No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : RTCC Enable
bits : 0 - 0 (1 bit)
access : read-write


CC1_OCVALUE

No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC1_OCVALUE CC1_OCVALUE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OC

OC : Output Compare Value
bits : 0 - 31 (32 bit)
access : read-write


CC1_ICVALUE

No Description
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CC1_ICVALUE CC1_ICVALUE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC

IC : Input Capture Value
bits : 0 - 31 (32 bit)
access : read-only


CFG

No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEBUGRUN PRECNTCCV0TOP CNTCCV1TOP CNTTICK CNTPRESC

DEBUGRUN : Debug Mode Run Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : X0

RTCC is frozen in debug mode

1 : X1

RTCC is running in debug mode

End of enumeration elements list.

PRECNTCCV0TOP : Pre-counter CCV0 top value enable.
bits : 1 - 1 (1 bit)
access : read-write

CNTCCV1TOP : CCV1 top value enable
bits : 2 - 2 (1 bit)
access : read-write

CNTTICK : Counter prescaler mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : PRESC

CNT register ticks according to configuration in CNTPRESC.

1 : CCV0MATCH

CNT register ticks when PRECNT matches RTCC_CC0_CCV[14:0]

End of enumeration elements list.

CNTPRESC : Counter prescaler value.
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0 : DIV1

CLK_CNT = (RTCC LF CLK)/1

1 : DIV2

CLK_CNT = (RTCC LF CLK)/2

2 : DIV4

CLK_CNT = (RTCC LF CLK)/4

3 : DIV8

CLK_CNT = (RTCC LF CLK)/8

4 : DIV16

CLK_CNT = (RTCC LF CLK)/16

5 : DIV32

CLK_CNT = (RTCC LF CLK)/32

6 : DIV64

CLK_CNT = (RTCC LF CLK)/64

7 : DIV128

CLK_CNT = (RTCC LF CLK)/128

8 : DIV256

CLK_CNT = (RTCC LF CLK)/256

9 : DIV512

CLK_CNT = (RTCC LF CLK)/512

10 : DIV1024

CLK_CNT = (RTCC LF CLK)/1024

11 : DIV2048

CLK_CNT = (RTCC LF CLK)/2048

12 : DIV4096

CLK_CNT = (RTCC LF CLK)/4096

13 : DIV8192

CLK_CNT = (RTCC LF CLK)/8192

14 : DIV16384

CLK_CNT = (RTCC LF CLK)/16384

15 : DIV32768

CLK_CNT = (RTCC LF CLK)/32768

End of enumeration elements list.


CMD

No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START STOP

START : Start RTCC main counter
bits : 0 - 0 (1 bit)
access : write-only

STOP : Stop RTCC main counter
bits : 1 - 1 (1 bit)
access : write-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.