\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXMAXREQ : TX Max Req
bits : 0 - 0 (1 bit)
access : read-write
RXPPREQ : RX PP Req
bits : 1 - 1 (1 bit)
access : read-write
Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RATDRFIMDCDCCTRL0 : RFIMDCDCCTRL0 Protection Bit
bits : 0 - 0 (1 bit)
access : read-write
RATDRFIMDCDCCTRL1 : RFIMDCDCCTRL1 Protection Bit
bits : 1 - 1 (1 bit)
access : read-write
RATDRFIMDCDCCTRL2 : RFIMDCDCCTRL2 Protection Bit
bits : 2 - 2 (1 bit)
access : read-write
No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCDCDIVEN : DCDC DIV Enable
bits : 0 - 0 (1 bit)
access : read-write
DCDCDIVINVEN : DCDC DIV Inverter Enable
bits : 1 - 1 (1 bit)
access : read-write
DCDCDIVRATIO : DCDC DIV Ratio
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : DIVRATIO8
Dividing master_rf clk by 8, D=50%
1 : DIVRATIO9
Dividing master_rf clk by 9, D=44.4%
2 : DIVRATIO10
Dividing master_rf clk by 10, D=40%
3 : DIVRATIO11
Dividing master_rf clk by 11, D=36.4%
4 : DIVRATIO12
Dividing master_rf clk by 12, D=50%
5 : DIVRATIO13
Dividing master_rf clk by 13, D=46.2%
6 : DIVRATIO14
Dividing master_rf clk by 14, D=42.9%
7 : DIVRATIO15
Dividing master_rf clk by 15, D=40%
8 : DIVRATIO16
Dividing master_rf clk by 16, D=50%
9 : DIVRATIO17
Dividing master_rf clk by 17, D=47.1%
10 : DIVRATIO18
Dividing master_rf clk by 18, D=44.4%
11 : DIVRATIO19
Dividing master_rf clk by 19, D=42.1%
12 : DIVRATIO20
Dividing master_rf clk by 20, D=60%
13 : DIVRATIO21
Dividing master_rf clk by 21, D=57.1%
14 : DIVRATIO22
Dividing master_rf clk by 22, D=54.5%
15 : DIVRATIO23
Dividing master_rf clk by 23, D=52.2%
End of enumeration elements list.
No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPTMAX : Pulse Pairing Time Max
bits : 0 - 8 (9 bit)
access : read-write
PPTMIN : Pulse Pairing Time Min
bits : 9 - 17 (9 bit)
access : read-write
PPND : Pulse Pairing Period
bits : 18 - 26 (9 bit)
access : read-write
PPCALEN : Pulse Pairing Calibration Loop Enable
bits : 27 - 27 (1 bit)
access : read-write
PPSYNCONLY : Pulse Pairing Sync Only
bits : 28 - 28 (1 bit)
access : read-write
No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCDCEN : DCDC Enable Status
bits : 0 - 0 (1 bit)
access : read-only
TXMAXSTATUS : TX MAX Status
bits : 1 - 1 (1 bit)
access : read-only
RXPPSTATUS : RX PP Status
bits : 2 - 2 (1 bit)
access : read-only
WNO1 : Cal Loop WNO1 value
bits : 8 - 16 (9 bit)
access : read-only
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