Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP Version
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFRAMESENT : Frame sent
bits : 0 - 0 (1 bit)
access : read-write
TXSYNCSENT : Sync word sent
bits : 1 - 1 (1 bit)
access : read-write
TXPRESENT : Preamble sent
bits : 2 - 2 (1 bit)
access : read-write
TXRAMPDONE : Mod ramper idle
bits : 3 - 3 (1 bit)
access : read-write
LDTNOARR : No signal Detected in LDT
bits : 4 - 4 (1 bit)
access : read-write
PHDSADET : PHASE DSA DETECT
bits : 5 - 5 (1 bit)
access : read-write
PHYUNCODEDET : CONCURRENT UNCODED PHY DET
bits : 6 - 6 (1 bit)
access : read-write
PHYCODEDET : CONCURRENT CODED PHY DET
bits : 7 - 7 (1 bit)
access : read-write
RXTIMDET : Timing detected
bits : 8 - 8 (1 bit)
access : read-write
RXPREDET : Preamble detected
bits : 9 - 9 (1 bit)
access : read-write
RXFRAMEDET0 : Frame with sync-word 0 detected
bits : 10 - 10 (1 bit)
access : read-write
RXFRAMEDET1 : Frame with sync-word 1 detected
bits : 11 - 11 (1 bit)
access : read-write
RXTIMLOST : Timing lost
bits : 12 - 12 (1 bit)
access : read-write
RXPRELOST : Preamble lost
bits : 13 - 13 (1 bit)
access : read-write
RXFRAMEDETOF : Frame detection overflow
bits : 14 - 14 (1 bit)
access : read-write
RXTIMNF : Timing not found
bits : 15 - 15 (1 bit)
access : read-write
FRCTIMOUT : DEMOD-FRC req/ack timeout
bits : 16 - 16 (1 bit)
access : read-write
ETS : Early timestamp
bits : 17 - 17 (1 bit)
access : read-write
CFGANTPATTRD : CFGANTPATTRD
bits : 18 - 18 (1 bit)
access : read-write
RXRESTARTRSSIMAPRE : RX restart using RSSI MA filter
bits : 19 - 19 (1 bit)
access : read-write
RXRESTARTRSSIMASYNC : RX restart using RSSI MA filter
bits : 20 - 20 (1 bit)
access : read-write
SQDET : SQ Detected
bits : 21 - 21 (1 bit)
access : read-write
SQNOTDET : SQ NOT Detected
bits : 22 - 22 (1 bit)
access : read-write
ANTDIVRDY : RSSI and CORR data Ready
bits : 23 - 23 (1 bit)
access : read-write
SOFTRESETDONE : Soft reset done
bits : 24 - 24 (1 bit)
access : read-write
SQPRENOTDET : SQ NOT Detected
bits : 25 - 25 (1 bit)
access : read-write
SQFRAMENOTDET : SQ NOT Detected
bits : 26 - 26 (1 bit)
access : read-write
SQAFCOUTOFBAND : SQ afc out of band
bits : 27 - 27 (1 bit)
access : read-write
No Description
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANARAMPLUT42 : Analog Ramp LUT
bits : 0 - 4 (5 bit)
access : read-write
ANARAMPLUT43 : Analog Ramp LUT
bits : 5 - 9 (5 bit)
access : read-write
ANARAMPLUT44 : Analog Ramp LUT
bits : 10 - 14 (5 bit)
access : read-write
ANARAMPLUT45 : Analog Ramp LUT
bits : 15 - 19 (5 bit)
access : read-write
ANARAMPLUT46 : Analog Ramp LUT
bits : 20 - 24 (5 bit)
access : read-write
ANARAMPLUT47 : Analog Ramp LUT
bits : 25 - 29 (5 bit)
access : read-write
No Description
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANARAMPLUT48 : Analog Ramp LUT
bits : 0 - 4 (5 bit)
access : read-write
ANARAMPLUT49 : Analog Ramp LUT
bits : 5 - 9 (5 bit)
access : read-write
ANARAMPLUT50 : Analog Ramp LUT
bits : 10 - 14 (5 bit)
access : read-write
ANARAMPLUT51 : Analog Ramp LUT
bits : 15 - 19 (5 bit)
access : read-write
ANARAMPLUT52 : Analog Ramp LUT
bits : 20 - 24 (5 bit)
access : read-write
ANARAMPLUT53 : Analog Ramp LUT
bits : 25 - 29 (5 bit)
access : read-write
No Description
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANARAMPLUT54 : Analog Ramp LUT
bits : 0 - 4 (5 bit)
access : read-write
ANARAMPLUT55 : Analog Ramp LUT
bits : 5 - 9 (5 bit)
access : read-write
ANARAMPLUT56 : Analog Ramp LUT
bits : 10 - 14 (5 bit)
access : read-write
ANARAMPLUT57 : Analog Ramp LUT
bits : 15 - 19 (5 bit)
access : read-write
ANARAMPLUT58 : Analog Ramp LUT
bits : 20 - 24 (5 bit)
access : read-write
ANARAMPLUT59 : Analog Ramp LUT
bits : 25 - 29 (5 bit)
access : read-write
No Description
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANARAMPLUT60 : Analog Ramp LUT
bits : 0 - 4 (5 bit)
access : read-write
ANARAMPLUT61 : Analog Ramp LUT
bits : 5 - 9 (5 bit)
access : read-write
ANARAMPLUT62 : Analog Ramp LUT
bits : 10 - 14 (5 bit)
access : read-write
ANARAMPLUT63 : Analog Ramp LUT
bits : 15 - 19 (5 bit)
access : read-write
No Description
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCESTIEN : DC Offset Estimation Enable
bits : 0 - 0 (1 bit)
access : read-write
DCCOMPEN : DC Offset Compensation Enable
bits : 1 - 1 (1 bit)
access : read-write
DCRSTEN : DC Compensation Filter Reset Enable
bits : 2 - 2 (1 bit)
access : read-write
DCCOMPFREEZE : DC Offset Compensation Filter Freeze
bits : 3 - 3 (1 bit)
access : read-write
DCCOMPGEAR : DC Offset Compensation Filter Gear
bits : 4 - 6 (3 bit)
access : read-write
DCLIMIT : DC offset limit
bits : 7 - 8 (2 bit)
access : read-write
Enumeration:
0 : FULLSCALE
1000 mV
1 : FULLSCALEBY4
250 mV
2 : FULLSCALEBY8
125 mV
3 : FULLSCALEBY16
62 mV
End of enumeration elements list.
DCGAINGEAREN : DC Offset Gain Change Filter Gear Enable
bits : 9 - 9 (1 bit)
access : read-write
DCGAINGEAR : DC Offset Gain Change Filter Gear
bits : 10 - 12 (3 bit)
access : read-write
DCGAINGEARSMPS : DC Offset Gain Change Samples
bits : 13 - 20 (8 bit)
access : read-write
No Description
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCCOMPINITVALI : I-channel initialization value
bits : 0 - 14 (15 bit)
access : read-write
DCCOMPINITVALQ : Q-channel initialization value
bits : 15 - 29 (15 bit)
access : read-write
DCCOMPINIT : Initialize filter state
bits : 30 - 30 (1 bit)
access : read-write
No Description
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCCOMPESTIVALI : I-channel DC-Offset Estimated value
bits : 0 - 14 (15 bit)
access : read-only
DCCOMPESTIVALQ : Q-channel DC-Offset Estimated value
bits : 15 - 29 (15 bit)
access : read-only
No Description
address_offset : 0x11C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCRATIO2 : SRC2 ratio
bits : 12 - 26 (15 bit)
access : read-write
SRCENABLE2 : SRC2 enable
bits : 27 - 27 (1 bit)
access : read-write
INTOSR : Forcing Integer OSR
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FOEPREAVG0 : First estimate
bits : 0 - 2 (3 bit)
access : read-write
FOEPREAVG1 : Second estimate
bits : 3 - 5 (3 bit)
access : read-write
FOEPREAVG2 : Third estimate
bits : 6 - 8 (3 bit)
access : read-write
FOEPREAVG3 : Fourth estimate
bits : 9 - 11 (3 bit)
access : read-write
FOEPREAVG4 : Fifth estimate
bits : 12 - 14 (3 bit)
access : read-write
FOEPREAVG5 : Sixth estimate
bits : 15 - 17 (3 bit)
access : read-write
FOEPREAVG6 : Seventh estimate
bits : 18 - 20 (3 bit)
access : read-write
FOEPREAVG7 : Eighth estimate
bits : 21 - 23 (3 bit)
access : read-write
No Description
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIKETHD : Spike threshold
bits : 0 - 7 (8 bit)
access : read-write
UNMODTHD : Unmodulated carrier detector threshold
bits : 8 - 13 (6 bit)
access : read-write
FDEVMINTHD : Frequency deviation minimum threshold
bits : 14 - 19 (6 bit)
access : read-write
FDEVMAXTHD : Frequency deviation maximum threshold
bits : 20 - 31 (12 bit)
access : read-write
No Description
address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POWABSTHD : Power absolute threshold
bits : 0 - 15 (16 bit)
access : read-write
POWRELTHD : Relative power detector threshold
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
Threshold is 6dB. The relative power detector will trigger when the current RSSI is 6dB stronger than the previously detected RSSI.
1 : MODE1
Threshold is 9dB. The relative power detector will trigger when the current RSSI is 9dB stronger than the previously detected RSSI.
2 : MODE2
Threshold is 12dB. The relative power detector will trigger when the current RSSI is 12dB stronger than the previously detected RSSI.
3 : MODE3
Threshold is 15dB. The relative power detector will trigger when the current RSSI is 15dB stronger than the previously detected RSSI.
End of enumeration elements list.
DSARSTCNT : DSA reset counter
bits : 18 - 20 (3 bit)
access : read-write
RSSIJMPTHD : RSSI jump detector threshold
bits : 21 - 24 (4 bit)
access : read-write
FREQLATDLY : Frequency late delay
bits : 25 - 26 (2 bit)
access : read-write
PWRFLTBYP : Power filter bypass
bits : 27 - 27 (1 bit)
access : read-write
AMPFLTBYP : Amplitude filter bypass
bits : 28 - 28 (1 bit)
access : read-write
PWRDETDIS : Power detection disabled
bits : 29 - 29 (1 bit)
access : read-write
FREQSCALE : Frequency scale factor
bits : 30 - 30 (1 bit)
access : read-write
No Description
address_offset : 0x12C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POWABSTHDLOG : Power threshold in logarithm-scale
bits : 0 - 7 (8 bit)
access : read-write
JUMPDETEN : Power jump detection enable
bits : 9 - 9 (1 bit)
access : read-write
FDADJTHD : Frequency deviation ripple threshold
bits : 10 - 15 (6 bit)
access : read-write
PMDETPASSTHD : DSA Preamble detection counter threshold
bits : 16 - 19 (4 bit)
access : read-write
FREQESTTHD : Frequency Estimation Timeout Threshold
bits : 20 - 24 (5 bit)
access : read-write
INTERFERDET : Interference detection threshold
bits : 25 - 29 (5 bit)
access : read-write
PMDETFORCE : Force DSA preamble detector
bits : 30 - 30 (1 bit)
access : read-write
No Description
address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIKETHDLO : Spike threshold
bits : 0 - 7 (8 bit)
access : read-write
UNMODTHDLO : Unmodulated carrier detector threshold
bits : 8 - 13 (6 bit)
access : read-write
FDEVMINTHDLO : Frequency deviation minimum threshold
bits : 14 - 19 (6 bit)
access : read-write
FDEVMAXTHDLO : Frequency deviation maximum threshold
bits : 20 - 31 (12 bit)
access : read-write
No Description
address_offset : 0x134 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POWABSTHDLO : Power absolute threshold for low power
bits : 0 - 15 (16 bit)
access : read-write
ARRTOLERTHD0LO : Arrival tolerance threshold 0
bits : 16 - 20 (5 bit)
access : read-write
ARRTOLERTHD1LO : Arrival tolerance threshold 1
bits : 21 - 25 (5 bit)
access : read-write
SWTHD : Enable switch threshold for low power
bits : 26 - 26 (1 bit)
access : read-write
No Description
address_offset : 0x138 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSAMODE : Mode of Digital Signal Arrival detector
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
DSA is disabled
1 : ENABLED
DSA is enabled by the relative/absolute RSSI detector and is reset by using detectors for spike content and frequency deviation. The RSSI jump detector is used to recover from false detects.
End of enumeration elements list.
ARRTHD : Signal arrival valid counter threshold
bits : 2 - 5 (4 bit)
access : read-write
ARRTOLERTHD0 : Arrival tolerance threshold 0
bits : 6 - 10 (5 bit)
access : read-write
ARRTOLERTHD1 : Arrival tolerance threshold 1
bits : 11 - 15 (5 bit)
access : read-write
SCHPRD : Search period window length
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : TS2
The search period is 2 symbol periods.
1 : TS4
The search period is 4 symbol periods.
End of enumeration elements list.
FREQAVGSYM : DSA frequency estimation averaging
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : AVG2TS
Frequency estimation over 2 symbol periods.
1 : AVG4TS
Frequency estimation over 4 symbol periods.
End of enumeration elements list.
TRANRSTDSA : power transient detector Reset DSA
bits : 18 - 18 (1 bit)
access : read-write
DSARSTON : DSA detection reset
bits : 19 - 19 (1 bit)
access : read-write
GAINREDUCDLY : Detection Delay of AGC gain reduction
bits : 21 - 22 (2 bit)
access : read-write
LOWDUTY : Low duty cycle delay
bits : 23 - 25 (3 bit)
access : read-write
RESTORE : Power detector reset of DSA
bits : 26 - 26 (1 bit)
access : read-write
AGCBAUDEN : Consider Baud_en from AGC
bits : 27 - 27 (1 bit)
access : read-write
AMPJUPTHD : Amplitude jump detection thrshold
bits : 28 - 31 (4 bit)
access : read-write
No Description
address_offset : 0x13C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIGMIXFREQ : Digital mixer frequency control word
bits : 0 - 19 (20 bit)
access : read-write
DIGMIXMODE : Digital mixer frequency control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : CFOSR
Mixer frequency specified by CFOSR.
1 : DIGMIXFREQ
Mixer frequency specified by DIGMIXFREQ.
End of enumeration elements list.
MIXERCONJ : Digital mixer input conjugate
bits : 21 - 21 (1 bit)
access : read-write
DIGMIXFB : Digital mixer Frequency Correction
bits : 22 - 22 (1 bit)
access : read-write
No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFRAMESENT : Frame sent
bits : 0 - 0 (1 bit)
access : read-write
TXSYNCSENT : Sync word sent
bits : 1 - 1 (1 bit)
access : read-write
TXPRESENT : Preamble sent
bits : 2 - 2 (1 bit)
access : read-write
TXRAMPDONE : Mod ramper idle
bits : 3 - 3 (1 bit)
access : read-write
LDTNOARR : No signal Detected in LDT
bits : 4 - 4 (1 bit)
access : read-write
PHDSADET : PHASE DSA DETECT
bits : 5 - 5 (1 bit)
access : read-write
PHYUNCODEDET : CONCURRENT UNCODED PHY DET
bits : 6 - 6 (1 bit)
access : read-write
PHYCODEDET : CONCURRENT CODED PHY DET
bits : 7 - 7 (1 bit)
access : read-write
RXTIMDET : Timing detected
bits : 8 - 8 (1 bit)
access : read-write
RXPREDET : Preamble detected
bits : 9 - 9 (1 bit)
access : read-write
RXFRAMEDET0 : Frame with sync-word 0 detected
bits : 10 - 10 (1 bit)
access : read-write
RXFRAMEDET1 : Frame with sync-word 1 detected
bits : 11 - 11 (1 bit)
access : read-write
RXTIMLOST : Timing lost
bits : 12 - 12 (1 bit)
access : read-write
RXPRELOST : Preamble lost
bits : 13 - 13 (1 bit)
access : read-write
RXFRAMEDETOF : Frame detection overflow
bits : 14 - 14 (1 bit)
access : read-write
RXTIMNF : Timing not found
bits : 15 - 15 (1 bit)
access : read-write
FRCTIMOUT : DEMOD-FRC req/ack timeout
bits : 16 - 16 (1 bit)
access : read-write
ETS : Early time stamp
bits : 17 - 17 (1 bit)
access : read-write
CFGANTPATTRD : CFGANTPATTRD
bits : 18 - 18 (1 bit)
access : read-write
RXRESTARTRSSIMAPRE : RX restart using RSSI MA filter
bits : 19 - 19 (1 bit)
access : read-write
RXRESTARTRSSIMASYNC : RX restart using RSSI MA filter
bits : 20 - 20 (1 bit)
access : read-write
SQDET : SQ DET
bits : 21 - 21 (1 bit)
access : read-write
SQNOTDET : SQ Not DET
bits : 22 - 22 (1 bit)
access : read-write
ANTDIVRDY : RSSI and CORR data Ready
bits : 23 - 23 (1 bit)
access : read-write
SOFTRESETDONE : Soft reset done
bits : 24 - 24 (1 bit)
access : read-write
SQPRENOTDET : SQ Not DET
bits : 25 - 25 (1 bit)
access : read-write
SQFRAMENOTDET : SQ Not DET
bits : 26 - 26 (1 bit)
access : read-write
SQAFCOUTOFBAND : SQ afc out of band
bits : 27 - 27 (1 bit)
access : read-write
No Description
address_offset : 0x140 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTDEMODEN : Viterbi demodulator enable
bits : 0 - 0 (1 bit)
access : read-write
HARDDECISION : Hard decision
bits : 1 - 1 (1 bit)
access : read-write
VITERBIKSI1 : VITERBI KSI1
bits : 2 - 8 (7 bit)
access : read-write
VITERBIKSI2 : VITERBI KSI2
bits : 9 - 15 (7 bit)
access : read-write
VITERBIKSI3 : VITERBI KSI3
bits : 16 - 22 (7 bit)
access : read-write
SYNTHAFC : Synthesizer AFC in Viterbi demod
bits : 23 - 23 (1 bit)
access : read-write
CORRCYCLE : Correction cycles
bits : 24 - 27 (4 bit)
access : read-write
CORRSTPSIZE : Correction step size
bits : 28 - 31 (4 bit)
access : read-write
No Description
address_offset : 0x144 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXPECTPATT : Expected pattern
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x148 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VITERBIKSI3WB : WB KSI3
bits : 0 - 6 (7 bit)
access : read-write
KSI3SWENABLE : WB KSI3 Switching Enable
bits : 7 - 7 (1 bit)
access : read-write
VTFRQLIM : Viterbi frequency limiter
bits : 8 - 16 (9 bit)
access : read-write
EXPSYNCLEN : Expected sync length
bits : 18 - 26 (9 bit)
access : read-write
EXPECTHT : Expected patterns head and tail
bits : 28 - 31 (4 bit)
access : read-write
No Description
address_offset : 0x14C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQTRACKMODE : Frequency tracking mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
Frequency tracking disabled. Only a one-time frequency offset compensation applied through DSA.
1 : MODE1
Frequency tracking enabled with one correction, when needed, every 16 symbol periods.
2 : MODE2
Frequency tracking enabled with one correction, when needed, every 32 symbol periods.
3 : MODE3
Frequency tracking enabled with one correction, when needed, every 48 symbol periods.
End of enumeration elements list.
TIMTRACKTHD : Timing tracking threshold
bits : 2 - 5 (4 bit)
access : read-write
TIMEACQUTHD : Time acquisition threshold
bits : 6 - 13 (8 bit)
access : read-write
TIMGEAR : Timing Gear
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : GEAR0
Execute timing tracking regardless of difference between Early/Late and Current correlation values. Referred to as fast gear. Same as GEAR3
1 : GEAR1
Execute timing tracking only when correlation value of Early/Late is 75% or less of the Current correlation value. Referred to as medium gear.
2 : GEAR2
Execute timing tracking only when correlation value of Early/Late is 50% or less of the Current correlation value. Referred to as slow gear.
End of enumeration elements list.
FREQBIAS : Frequency estimation bias
bits : 18 - 21 (4 bit)
access : read-write
HIPWRTHD : High Power detection threshold
bits : 22 - 29 (8 bit)
access : read-write
No Description
address_offset : 0x150 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTBLETIMINGSEL : Viterbi BLE timing stamp selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : FRAMEDET_DELAY
Delayed frame detection will be used as Timing stamp. This mode should be selected for legacy demod and Long Range BLE demod.
1 : END_FRAME_PULSE
The end of frame detection from Narrow Viterbi demod will be used as Timing stamp. This signal is a narrow pulse signal and pulse width is one xo clock cycle.
2 : END_FRAME
The end of frame detection from Narrow Viterbi demod will be used as Timing stamp. This signal is a wdie pulse signal
3 : INV_END_FRAME
For testing only.
End of enumeration elements list.
TIMINGDELAY : Viterbi BLE Delay timer
bits : 4 - 11 (8 bit)
access : read-write
FLENOFF : Timing Stamp Frame Length Offset
bits : 12 - 15 (4 bit)
access : read-write
DISDEMODOF : Disable VT Demod Over Flow Detection
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x154 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BRESTINT : Integer part of estimated baudrate
bits : 0 - 5 (6 bit)
access : read-only
BRESTNUM : Fractional part of estimated baudrate
bits : 6 - 10 (5 bit)
access : read-only
No Description
address_offset : 0x158 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTOCGEN : Enable automatic clock gating
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x15C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORCEOFF : Manual control clocks
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x160 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
POEI : In-phase component of POE.
bits : 0 - 9 (10 bit)
access : read-only
POEQ : Quadrature component of POE.
bits : 16 - 25 (10 bit)
access : read-only
No Description
address_offset : 0x164 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMENABLE : Enable Direct Mode
bits : 0 - 0 (1 bit)
access : read-write
SYNCASYNC : Choose Synchronous or Asynchronous mode
bits : 1 - 1 (1 bit)
access : read-write
SYNCPREAM : Synchronous mode preamble
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : ADD0
No preamble bits appended
1 : ADD8
8 preamble bits appended
2 : ADD16
16 preamble bits appended
3 : ADD32
32 preamble bits appended
End of enumeration elements list.
CLKWIDTH : Synchronous mode clock pulse width
bits : 8 - 12 (5 bit)
access : read-write
No Description
address_offset : 0x16C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LRSS : Long Range Signal Selection
bits : 0 - 3 (4 bit)
access : read-write
LRTIMEOUTTHD : Long Range Time Out Threshold
bits : 4 - 14 (11 bit)
access : read-write
CHPWRACCUDEL : Channel Power Accumulated Delay
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : DEL0
Use accumulated channel power value
1 : DEL32
Delayed by 32 chips
2 : DEL64
Delayed by 64 chips
End of enumeration elements list.
HYSVAL : Hysteresis Value for BBSS
bits : 18 - 20 (3 bit)
access : read-write
AVGWIN : Average window
bits : 21 - 23 (3 bit)
access : read-write
LRSPIKETHADD : Long Range DSA spike threshold addition
bits : 24 - 27 (4 bit)
access : read-write
LOGICBASEDPUGATE : Logic Based Phase Unwrap Gating
bits : 28 - 28 (1 bit)
access : read-write
LOGICBASEDLRDEMODGATE : Logic Based Long Range Demod Gating
bits : 29 - 29 (1 bit)
access : read-write
PREFILTLEN : Prefilter Length
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : LEN32
Filter length is 32
1 : LEN64
Filter length is 64
2 : LEN96
Filter length is 96
3 : LEN128
Filter length is 128
End of enumeration elements list.
No Description
address_offset : 0x170 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LRCHPWRTH1 : Long Range channel power threshold
bits : 0 - 7 (8 bit)
access : read-write
LRCHPWRTH2 : Long Range channel power threshold
bits : 8 - 15 (8 bit)
access : read-write
LRCHPWRTH3 : Long Range channel power threshold
bits : 16 - 23 (8 bit)
access : read-write
LRCHPWRTH4 : Long Range channel power threshold
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0x174 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LRCHPWRTH5 : Long Range channel power threshold
bits : 0 - 7 (8 bit)
access : read-write
LRCHPWRTH6 : Long Range channel power threshold
bits : 8 - 15 (8 bit)
access : read-write
LRCHPWRTH7 : Long Range channel power threshold
bits : 16 - 23 (8 bit)
access : read-write
LRCHPWRTH8 : Long Range channel power threshold
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0x178 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LRCHPWRTH9 : Long Range channel power threshold
bits : 0 - 7 (8 bit)
access : read-write
LRCHPWRTH10 : Long Range channel power threshold
bits : 8 - 15 (8 bit)
access : read-write
LRCHPWRSH1 : Long Range channel power shift
bits : 16 - 19 (4 bit)
access : read-write
LRCHPWRSH2 : Long Range channel power shift
bits : 20 - 23 (4 bit)
access : read-write
LRCHPWRSH3 : Long Range channel power shift
bits : 24 - 27 (4 bit)
access : read-write
LRCHPWRSH4 : Long Range channel power shift
bits : 28 - 31 (4 bit)
access : read-write
No Description
address_offset : 0x17C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LRCHPWRSH5 : Long Range channel power shift
bits : 0 - 3 (4 bit)
access : read-write
LRCHPWRSH6 : Long Range channel power shift
bits : 4 - 7 (4 bit)
access : read-write
LRCHPWRSH7 : Long Range channel power shift
bits : 8 - 11 (4 bit)
access : read-write
LRCHPWRSH8 : Long Range channel power shift
bits : 12 - 15 (4 bit)
access : read-write
LRCHPWRSH9 : Long Range channel power shift
bits : 16 - 19 (4 bit)
access : read-write
LRCHPWRSH10 : Long Range channel power shift
bits : 20 - 23 (4 bit)
access : read-write
LRCHPWRSH11 : Long Range channel power shift
bits : 24 - 27 (4 bit)
access : read-write
No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEMODSTATE : DEMOD state
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0 : OFF
Off state
1 : TIMINGSEARCH
Timing search
2 : PRESEARCH
Preamble search
3 : FRAMESEARCH
Frame search
4 : RXFRAME
Payload Detection
5 : FRAMEDETMODE0
Timing search with sliding window (FDM0)
End of enumeration elements list.
BCRCFEDSADET : BCR CFE DSA DETECTION
bits : 3 - 3 (1 bit)
access : read-only
FRAMEDETID : Frame Detected ID
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : FRAMEDET0
Last frame was detected with sync word defined in SYNC0.
1 : FRAMEDET1
Last frame was detected with sync word defined in SYNC1.
End of enumeration elements list.
ANTSEL : Selected Antenna
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : ANTENNA0
Antenna 0 is selected (ANT0 = 1 and ANT1 = 0).
1 : ANTENNA1
Antenna 1 is selected (ANT0 = 0 and ANT1 = 1).
End of enumeration elements list.
TIMSEQINV : Timing Sequence Inverted
bits : 6 - 6 (1 bit)
access : read-only
TIMLOSTCAUSE : Timing Lost Cause
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : LOWCORR
Timing lost during Preamble Search or due to low correlation value during Frame Search.
1 : TIMEOUT
Timing lost due to incorrect symbols detected during Frame Search.
End of enumeration elements list.
DSADETECTED : PHASE-DSA detected
bits : 8 - 8 (1 bit)
access : read-only
DSAFREQESTDONE : DSA frequency estimation complete
bits : 9 - 9 (1 bit)
access : read-only
VITERBIDEMODTIMDET : TRECS Demod timing detected
bits : 10 - 10 (1 bit)
access : read-only
VITERBIDEMODFRAMEDET : TRECS Demod frame detected
bits : 11 - 11 (1 bit)
access : read-only
STAMPSTATE : BLE Viterbi Demod Timing Stamp
bits : 12 - 14 (3 bit)
access : read-only
TRECSDSAADET : TRECS DSA DETECTION
bits : 15 - 15 (1 bit)
access : read-only
CORR : Correlation
bits : 16 - 23 (8 bit)
access : read-only
WEAKSYMBOLS : Weak symbols
bits : 24 - 31 (8 bit)
access : read-only
No Description
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LRCHPWRSPIKETH : Long Range channel power spike threshold
bits : 0 - 7 (8 bit)
access : read-write
LRSPIKETHD : Long Range spike threshold
bits : 8 - 18 (11 bit)
access : read-write
LRCHPWRTH11 : Long Range channel power threshold
bits : 20 - 27 (8 bit)
access : read-write
LRCHPWRSH12 : Long Range channel power shift
bits : 28 - 31 (4 bit)
access : read-write
No Description
address_offset : 0x184 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CI500 : Long Range CI mapping for 500kbps
bits : 0 - 1 (2 bit)
access : read-write
FRCACKTIMETHD : FRC acknowledge timeout threshold
bits : 2 - 7 (6 bit)
access : read-write
LRCORRMODE : LR Correlator operation Mode
bits : 8 - 8 (1 bit)
access : read-write
No Description
address_offset : 0x188 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COHDYNAMICBBSSEN : Dynamic BBSS enable bit
bits : 0 - 0 (1 bit)
access : read-write
COHDYNAMICSYNCTHRESH : Dynamic syncword threshold enable bit
bits : 1 - 1 (1 bit)
access : read-write
COHDYNAMICPRETHRESH : Dynamic preamble threshold enable bit
bits : 2 - 2 (1 bit)
access : read-write
COHCHPWRLOCK : Channel power lock
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TIMDET
Channel power locked when timing is detected
1 : DSADET
Channel power locked when DSA is detected
End of enumeration elements list.
COHCHPWRRESTART : Channel power restart
bits : 4 - 4 (1 bit)
access : read-write
COHDYNAMICPRETHRESHSEL : Dynamic preamble threshold selection
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : SEL0
1x sync coeff
1 : SEL1
0.94x sync coeff
2 : SEL2
0.88x sync coeff
3 : SEL3
0.74x sync coeff
4 : SEL4
0.5x sync coeff
End of enumeration elements list.
COHCHPWRTH0 : Channel power threshold
bits : 8 - 15 (8 bit)
access : read-write
COHCHPWRTH1 : Channel power threshold
bits : 16 - 23 (8 bit)
access : read-write
COHCHPWRTH2 : Channel power threshold
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0x18C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCTHRESH0 : Minimum correlation threshold
bits : 0 - 7 (8 bit)
access : read-write
SYNCTHRESH1 : Minimum correlation threshold
bits : 8 - 15 (8 bit)
access : read-write
SYNCTHRESH2 : Minimum correlation threshold
bits : 16 - 23 (8 bit)
access : read-write
SYNCTHRESH3 : Minimum correlation threshold
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0x190 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCTHRESHDELTA0 : Syncword correlation delta threshold
bits : 0 - 3 (4 bit)
access : read-write
SYNCTHRESHDELTA1 : Syncword correlation delta threshold
bits : 4 - 7 (4 bit)
access : read-write
SYNCTHRESHDELTA2 : Syncword correlation delta threshold
bits : 8 - 11 (4 bit)
access : read-write
SYNCTHRESHDELTA3 : Syncword correlation delta threshold
bits : 12 - 15 (4 bit)
access : read-write
DSAPEAKCHPWRTH : DSA Peak Check CHpwr Threshold
bits : 16 - 23 (8 bit)
access : read-write
FIXEDCDTHFORIIR : .
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0x194 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COHDSAEN : DSA enable bit
bits : 0 - 0 (1 bit)
access : read-write
COHDSAADDWNDSIZE : DSA additional window size
bits : 1 - 10 (10 bit)
access : read-write
CDSS : DSA Signal Selection
bits : 11 - 13 (3 bit)
access : read-write
DSAPEAKCHKEN : DSA Peak Checking Enable
bits : 14 - 14 (1 bit)
access : read-write
DSAPEAKINDLEN : DSA Peak Index length
bits : 15 - 17 (3 bit)
access : read-write
DSAPEAKCHPWREN : DSA Peak Check channel power enable
bits : 18 - 18 (1 bit)
access : read-write
LOGICBASEDCOHDEMODGATE : Logic Based clock gate
bits : 19 - 19 (1 bit)
access : read-write
DYNIIRCOEFOPTION : Dynamic IIR
bits : 20 - 21 (2 bit)
access : read-write
ONEPEAKQUALEN : One Peak
bits : 22 - 22 (1 bit)
access : read-write
PEAKCHKTIMOUT : Peak Check Time Out
bits : 23 - 27 (5 bit)
access : read-write
COHDSADETDIS : DSA Detection Disable
bits : 28 - 28 (1 bit)
access : read-write
COHDSACMPLX : DSA Complex
bits : 29 - 29 (1 bit)
access : read-write
No Description
address_offset : 0x198 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PRESTOP : Preamble stop
bits : 0 - 0 (1 bit)
access : write-only
CHPWRACCUCLR : Channel Power Accumulation Clear
bits : 1 - 1 (1 bit)
access : write-only
AFCTXLOCK : Lock AFC TX compensation
bits : 3 - 3 (1 bit)
access : write-only
AFCTXCLEAR : Clear AFC TX compensation.
bits : 4 - 4 (1 bit)
access : write-only
AFCRXCLEAR : Clear AFC RX compensation.
bits : 5 - 5 (1 bit)
access : write-only
No Description
address_offset : 0x1A4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATICSYNCTHRESHEN : Static Sync Threshold Enable
bits : 8 - 8 (1 bit)
access : read-write
STATICSYNCTHRESH : Static Sync Threshold
bits : 9 - 16 (8 bit)
access : read-write
No Description
address_offset : 0x1A8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIGIGAINEN : Digital Gain Enable
bits : 0 - 0 (1 bit)
access : read-write
DIGIGAINSEL : Digital Gain Select
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : GAINM3
GAINM3
1 : GAINM2P75
GAINM2P75
2 : GAINM2P5
GAINM2P5
3 : GAINM2P25
GAINM2P25
4 : GAINM2
GAINM2
5 : GAINM1P75
GAINM1P75
6 : GAINM1P5
GAINM1P5
7 : GAINM1P25
GAINM1P25
8 : GAINM1
GAINM1
9 : GAINM0P75
GAINM0P75
10 : GAINM0P5
GAINM0P5
11 : GAINM0P25
GAINM0P25
12 : GAINM0
GAINM0
13 : GAINP0P25
GAINP0P25
14 : GAINP0P5
GAINP0P5
15 : GAINP0P75
GAINP0P75
16 : GAINP1
GAINP1
17 : GAINP1P25
GAINP1P25
18 : GAINP1P5
GAINP1P5
19 : GAINP1P75
GAINP1P75
20 : GAINP2
GAINP2
21 : GAINP2P25
GAINP2P25
22 : GAINP2P5
GAINP2P5
23 : GAINP2P75
GAINP2P75
24 : GAINP3
GAINP3
End of enumeration elements list.
DIGIGAINDOUBLE : Digital Gain Doubled
bits : 6 - 6 (1 bit)
access : read-write
DIGIGAINHALF : Digital Gain Halved
bits : 7 - 7 (1 bit)
access : read-write
DEC0GAIN : DEC0 Gain Select
bits : 8 - 8 (1 bit)
access : read-write
No Description
address_offset : 0x1AC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSTPONESEL :
bits : 0 - 1 (2 bit)
access : read-write
ADVANCESEL :
bits : 2 - 3 (2 bit)
access : read-write
NEWWNDSEL :
bits : 4 - 5 (2 bit)
access : read-write
WEAKSEL :
bits : 6 - 7 (2 bit)
access : read-write
SYNCSENTSEL :
bits : 8 - 9 (2 bit)
access : read-write
PRESENTSEL :
bits : 10 - 11 (2 bit)
access : read-write
LOWCORRSEL :
bits : 12 - 13 (2 bit)
access : read-write
ANT0SEL :
bits : 14 - 15 (2 bit)
access : read-write
ANT1SEL :
bits : 16 - 17 (2 bit)
access : read-write
IFADCCLKSEL :
bits : 18 - 19 (2 bit)
access : read-write
No Description
address_offset : 0x1B4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MINCOSTTHD : Minimum Cost Threshold
bits : 0 - 9 (10 bit)
access : read-write
RTSCHWIN : Real time CFE searching window
bits : 10 - 13 (4 bit)
access : read-write
RTSCHMODE : Real Time CFE searching mode
bits : 14 - 14 (1 bit)
access : read-write
TRACKINGWIN : Correlator size for Tracking
bits : 15 - 17 (3 bit)
access : read-write
SYNCACQWIN : SYNC Correlator Size
bits : 18 - 20 (3 bit)
access : read-write
EXTENSCHBYP : Bypass extending Search Time
bits : 21 - 21 (1 bit)
access : read-write
SINEWEN : Enable SINE WEIGHT
bits : 29 - 29 (1 bit)
access : read-write
VTAFCFRAME : Viterbi AFC FRAME Mode
bits : 30 - 30 (1 bit)
access : read-write
RTCFEEN : TRECS Enable
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x1B8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETSLOC : Early Time Stamp Location
bits : 0 - 9 (10 bit)
access : read-write
CAPSIGONPRS : Capture Signal On PRS
bits : 10 - 10 (1 bit)
access : read-write
CAPTRIG : Trigger to capture
bits : 12 - 29 (18 bit)
access : read-write
No Description
address_offset : 0x1BC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETSTIMVAL : ETSTIMVAL
bits : 0 - 16 (17 bit)
access : read-write
ETSCOUNTEREN : ETSCOUNTEREN
bits : 17 - 17 (1 bit)
access : read-write
No Description
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHPWRACCUMUX : Channel power
bits : 0 - 7 (8 bit)
access : read-only
BBSSMUX : Actual Baseband Signal Selection
bits : 8 - 11 (4 bit)
access : read-only
LRBLECI : RXed packet's LR BLE coding indicator
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0 : LR125k
FEC block 2 coded using C=8, 125kbps
1 : LR500k
FEC block 2 coded using C=2, 500kbps
End of enumeration elements list.
UNCODEDPHY : UNCODED PHY DET
bits : 14 - 14 (1 bit)
access : read-only
CODEDPHY : CODED PHY DET
bits : 15 - 15 (1 bit)
access : read-only
RTCOST : TRECS demod real time cost
bits : 18 - 31 (14 bit)
access : read-only
No Description
address_offset : 0x1C0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANTDFLTSEL : Ant Default Select
bits : 0 - 5 (6 bit)
access : read-write
ANTCOUNT : Total Ant count
bits : 6 - 11 (6 bit)
access : read-write
ANTSWTYPE : Ant Switch Type
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : US_2
2us ant switching
1 : US_4
4us ant switching
2 : US_6
6us ant switching
3 : US_8
8us ant switching
End of enumeration elements list.
ANTSWRST : Ant SW rst pulse
bits : 14 - 14 (1 bit)
access : write-only
CFGANTPATTEN : Configure Ant Pattern Enable
bits : 15 - 15 (1 bit)
access : read-write
ANTSWENABLE : Ant sw enable
bits : 16 - 16 (1 bit)
access : read-write
EXTDSTOPPULSECNT : Extend Stop Pulse Counter
bits : 17 - 24 (8 bit)
access : read-write
No Description
address_offset : 0x1C4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEPERIOD : Time Period of xtal
bits : 0 - 23 (24 bit)
access : read-write
No Description
address_offset : 0x1C8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANTSWSTARTTIM : Ant switch start time
bits : 0 - 17 (18 bit)
access : read-write
No Description
address_offset : 0x1CC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANTSWENDTIM : Ant switch start time
bits : 0 - 17 (18 bit)
access : read-write
No Description
address_offset : 0x1D0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMEXPECTPATT : Expected PM pattern
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x1D4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMACQUINGWIN : PM Correlator Size
bits : 0 - 2 (3 bit)
access : read-write
PMCOSTVALTHD : Min COST Validation for AFC
bits : 3 - 5 (3 bit)
access : read-write
PMTIMEOUTSEL : PM searching timeout Threshold
bits : 6 - 7 (2 bit)
access : read-write
PHSCALE : PHASE Scaler
bits : 8 - 9 (2 bit)
access : read-write
PMMINCOSTTHD : Min. Cost thrshold for TRECS PM
bits : 14 - 23 (10 bit)
access : read-write
COSTHYST : PM Seaching COST HYST
bits : 25 - 29 (5 bit)
access : read-write
PREAMSCH : PM detection enable in TRECS
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x1D8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRECSOSR : TRECS OSR
bits : 0 - 2 (3 bit)
access : read-write
DTIMLOSSTHD : Timing Loss Threshold
bits : 3 - 12 (10 bit)
access : read-write
DTIMLOSSEN : ENABLE TIMING LOSS DETECTION
bits : 14 - 14 (1 bit)
access : read-write
PMOFFSET : PM SCH ADRESS offsrt
bits : 16 - 24 (9 bit)
access : read-write
No Description
address_offset : 0x1DC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGANTPATTVAL : CFGANTPATTVAL
bits : 0 - 29 (30 bit)
access : read-write
No Description
address_offset : 0x1E4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0COEFF0 : SET 0 CHF COE0
bits : 0 - 9 (10 bit)
access : read-write
SET0COEFF1 : SET 0 CHF COE1
bits : 10 - 19 (10 bit)
access : read-write
SET0COEFF2 : SET 0 CHF COE2
bits : 20 - 29 (10 bit)
access : read-write
No Description
address_offset : 0x1E8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0COEFF3 : SET 0 CHF COE3
bits : 0 - 10 (11 bit)
access : read-write
SET0COEFF4 : SET 0 CHF COE4
bits : 11 - 21 (11 bit)
access : read-write
No Description
address_offset : 0x1EC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0COEFF5 : SET 0 CHF COE5
bits : 0 - 10 (11 bit)
access : read-write
SET0COEFF6 : SET 0 CHF COE6
bits : 11 - 22 (12 bit)
access : read-write
No Description
address_offset : 0x1F0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0COEFF7 : SET 0 CHF COE7
bits : 0 - 11 (12 bit)
access : read-write
SET0COEFF8 : SET 0 CHF COE8
bits : 12 - 23 (12 bit)
access : read-write
No Description
address_offset : 0x1F4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0COEFF9 : SET 0 CHF COE9
bits : 0 - 13 (14 bit)
access : read-write
SET0COEFF10 : SET 0 CHF COE10
bits : 14 - 27 (14 bit)
access : read-write
No Description
address_offset : 0x1F8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0COEFF11 : SET 0 CHF COE11
bits : 0 - 13 (14 bit)
access : read-write
SET0COEFF12 : SET 0 CHF COE12
bits : 14 - 29 (16 bit)
access : read-write
No Description
address_offset : 0x1FC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0COEFF13 : SET 0 CHF COE13
bits : 0 - 15 (16 bit)
access : read-write
SET0COEFF14 : SET 0 CHF COE14
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BBPFOUTABS1 : Pre-filter Correlation Output
bits : 0 - 10 (11 bit)
access : read-only
BBPFOUTABS : Pre-filter Correlation Output for BLR
bits : 11 - 21 (11 bit)
access : read-only
LRDSALIVE : BLRDSA Prefilter above LRSPIKETHD
bits : 22 - 22 (1 bit)
access : read-only
COHDSALIVE : COHDSA Prefilter above CDTH
bits : 23 - 23 (1 bit)
access : read-only
LRDSADET : DSA prefilter above LRSPIKETHD
bits : 24 - 24 (1 bit)
access : read-only
COHDSADET : DSA prefilter above CDTH
bits : 25 - 25 (1 bit)
access : read-only
SYNCSECPEAKABTH : SYNC second peak above threshold
bits : 26 - 26 (1 bit)
access : read-only
SOFTRSTDONE : Soft reset done
bits : 27 - 27 (1 bit)
access : read-only
No Description
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET1COEFF0 : SET 1 CHF COE0
bits : 0 - 9 (10 bit)
access : read-write
SET1COEFF1 : SET 1 CHF COE1
bits : 10 - 19 (10 bit)
access : read-write
SET1COEFF2 : SET 1 CHF COE2
bits : 20 - 29 (10 bit)
access : read-write
No Description
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET1COEFF3 : SET 1 CHF COE3
bits : 0 - 10 (11 bit)
access : read-write
SET1COEFF4 : SET 1 CHF COE4
bits : 11 - 21 (11 bit)
access : read-write
No Description
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET1COEFF5 : SET 1 CHF COE5
bits : 0 - 10 (11 bit)
access : read-write
SET1COEFF6 : SET 1 CHF COE6
bits : 11 - 22 (12 bit)
access : read-write
No Description
address_offset : 0x20C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET1COEFF7 : SET 1 CHF COE7
bits : 0 - 11 (12 bit)
access : read-write
SET1COEFF8 : SET 1 CHF COE8
bits : 12 - 23 (12 bit)
access : read-write
No Description
address_offset : 0x210 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET1COEFF9 : SET 1 CHF COE9
bits : 0 - 13 (14 bit)
access : read-write
SET1COEFF10 : SET 1 CHF COE10
bits : 14 - 27 (14 bit)
access : read-write
No Description
address_offset : 0x214 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET1COEFF11 : SET 1 CHF COE11
bits : 0 - 13 (14 bit)
access : read-write
SET1COEFF12 : SET 1 CHF COE12
bits : 14 - 29 (16 bit)
access : read-write
No Description
address_offset : 0x218 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET1COEFF13 : SET 1 CHF COE13
bits : 0 - 15 (16 bit)
access : read-write
SET1COEFF14 : SET 1 CHF COE14
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x21C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FWSWCOEFFEN : FW Switch CHF COE. Enable
bits : 0 - 0 (1 bit)
access : read-write
FWSELCOEFF : FW Select CHF COE. set
bits : 1 - 1 (1 bit)
access : read-write
SWCOEFFEN : Switch CHF COE. Enable
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x220 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHFLATENCY : CHF Latency
bits : 0 - 1 (2 bit)
access : read-write
No Description
address_offset : 0x224 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRMSCHTIME : FRAME SCH TIME OUT THRD
bits : 0 - 15 (16 bit)
access : read-write
PMRSTSYCNEN : ENABLE CLEAN SYNC
bits : 29 - 29 (1 bit)
access : read-write
DSARSTSYCNEN : ENABLE CLEAN SYNC
bits : 30 - 30 (1 bit)
access : read-write
PMENDSCHEN : EnABLE SCH PM END
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x228 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREFILTCOEFF : Preamble Filter Coefficients
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x22C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRESTARTUPONMARSSI : Restart RX upon RSSI MA above threshold
bits : 0 - 0 (1 bit)
access : read-write
RXRESTARTMATHRESHOLD : Threshold for the RSSI MA filter
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : DB0
0 DB
1 : DB1
1 DB
2 : DB2
2 DB
3 : DB3
3 DB
4 : DB4
4 DB
5 : DB5
6 : DB6
6 DB
7 : DB7
8 : DB8
9 : DB9
10 : DB10
11 : DB11
12 : DB12
13 : DB13
14 : DB14
15 : DB15
15 DB
End of enumeration elements list.
RXRESTARTMALATCHSEL : latch the RSSI MA filter output
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : RE_PRE_DET
rising edge of per det
1 : RE_SYNC_DET
rising edge of sync det
2 : EITHER1
either of the two
3 : EITHER2
either of the two
End of enumeration elements list.
RXRESTARTMACOMPENSEL : Enable the comparator
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : PRE_DET
preamble detection
1 : FRAME_SYNC_DET
frame/sync detection
2 : BOTH1
both preamble and frame/sync detection
3 : BOTH2
both preamble and frame/sync detection
End of enumeration elements list.
RXRESTARTMATAP : Number of taps for the MA filter
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : TAPS4
1 : TAPS8
End of enumeration elements list.
RXRESTARTB4PREDET : whether to restart RX before pre det
bits : 16 - 16 (1 bit)
access : read-write
ANTSWRSTFLTTDIS : ANT SW RESET Filter Disable
bits : 30 - 30 (1 bit)
access : read-write
FLTRSTEN : RX Chain Filter reset enable
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x230 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQEN : SQ enable
bits : 0 - 0 (1 bit)
access : read-write
SQSWRST : SQ hold demod
bits : 1 - 1 (1 bit)
access : write-only
SQTIMOUT : SQ Timeout
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x234 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQSTG2TIMOUT : SQ Timeout
bits : 0 - 15 (16 bit)
access : read-write
SQSTG3TIMOUT : SQ Timeout
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x238 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQISELECT : SQI selection bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CORR
1 : ERROR
End of enumeration elements list.
CHIPERROR : Chip errors
bits : 16 - 23 (8 bit)
access : read-only
No Description
address_offset : 0x23C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADPRETHRESH : Preamble threshold
bits : 0 - 7 (8 bit)
access : read-write
ENADPRETHRESH : Enable Preamble threshold
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable use of Preamble threshold after timing detection
1 : ENABLE
Enable use of Preamble threshold after timing detection
End of enumeration elements list.
ANTDIVDISCCA : Antenna switch disable for CSMA
bits : 9 - 9 (1 bit)
access : read-write
ANTDIVSELCCA : Antenna switch selection for CSMA
bits : 10 - 10 (1 bit)
access : read-write
No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ANT0RSSI : ANT0 RSSI value
bits : 0 - 8 (9 bit)
access : read-only
ANT1RSSI : ANT1 RSSI value
bits : 16 - 24 (9 bit)
access : read-only
No Description
address_offset : 0x240 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FWSELANT : FW antenna selection
bits : 0 - 0 (1 bit)
access : read-write
FWANTSWCMD : FW Antenna SW cmd
bits : 1 - 1 (1 bit)
access : write-only
FWANTDIVEN : Enable FW ANT-DIV mode
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x244 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANTWAIT : ANTENNA WAIT TIME
bits : 0 - 4 (5 bit)
access : read-write
SKIPRSSITHD : RSSI THD to SKIP 2th ANTENNA Evaluate
bits : 5 - 12 (8 bit)
access : read-write
SKIPCORRTHD : CORR THD to SKIP 2th ANTENNA Evaluate
bits : 16 - 23 (8 bit)
access : read-write
SKIP2ANT : SKIP 2th ANTENNA Evaluate
bits : 30 - 30 (1 bit)
access : read-write
No Description
address_offset : 0x248 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CORRANDDIVTHD : Correlation Selection in region
bits : 0 - 9 (10 bit)
access : read-write
RSSIANDDIVTHD : RSSI Selection in region
bits : 10 - 18 (9 bit)
access : read-write
RSSICORR0 : RSSI-CORR Selection in Region0
bits : 28 - 28 (1 bit)
access : read-write
RSSICORR1 : RSSI-CORR Selection in Region1
bits : 29 - 29 (1 bit)
access : read-write
RSSICORR2 : RSSI-CORR Selection in Region2
bits : 30 - 30 (1 bit)
access : read-write
RSSICORR3 : RSSI-CORR Selection in Region3
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x24C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMDETTHD : Preamble Detection Thrshould
bits : 0 - 4 (5 bit)
access : read-write
PMTIMLOSTHD : Preamble Timing loss thrshold
bits : 5 - 12 (8 bit)
access : read-write
PMTIMLOSEN : Preamble timing loss detection
bits : 13 - 13 (1 bit)
access : read-write
RSSIFLTBYP : Bypass RSSI Filering
bits : 14 - 14 (1 bit)
access : read-write
PMDETEN : PREAMBLE DET
bits : 15 - 15 (1 bit)
access : read-write
REMODOSR : REMOD INPUT OSR
bits : 16 - 21 (6 bit)
access : read-write
REMODDWN : REMOD downsampling ratio
bits : 22 - 25 (4 bit)
access : read-write
REMODOUTSEL : REMOD OUTPUT Selection
bits : 26 - 27 (2 bit)
access : read-write
REMODEN : REMOD ENABLE
bits : 28 - 28 (1 bit)
access : read-write
BCRDETECTOR : Enbale BCRDMOD Dtetector ONLY
bits : 29 - 29 (1 bit)
access : read-write
BCRTRECSCONC : BCR/LEGACY CONCURRENT MODE
bits : 30 - 30 (1 bit)
access : read-write
BCRLEGACYCONC : BCR/TRECS CONCURRENT MODE
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x270 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRCALEN : IRCAL enable bit
bits : 0 - 0 (1 bit)
access : read-write
MURSHF : MUR shift value
bits : 1 - 5 (5 bit)
access : read-write
MUISHF : MUI shift value
bits : 7 - 12 (6 bit)
access : read-write
IRCORREN : IR Correction enable bit
bits : 13 - 13 (1 bit)
access : read-write
IRCALCOEFRSTCMD : IRCAL coef reset cmd
bits : 14 - 14 (1 bit)
access : write-only
IRCALIFADCDBG : IRCAL IFADC DBG
bits : 15 - 15 (1 bit)
access : read-write
No Description
address_offset : 0x274 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRV : CRV coefficient
bits : 0 - 14 (15 bit)
access : read-only
CIV : CIV coefficient
bits : 16 - 30 (15 bit)
access : read-only
No Description
address_offset : 0x278 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRVWD : CRV coefficient
bits : 0 - 14 (15 bit)
access : read-write
CRVWEN : CIV Coefficient Write Enable
bits : 15 - 15 (1 bit)
access : read-write
CIVWD : CIV coefficient
bits : 16 - 30 (15 bit)
access : read-write
CIVWEN : CIV Coefficient Write Enable
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x27C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRVWD : CRV coefficient
bits : 0 - 14 (15 bit)
access : read-write
CRVWEN : CIV Coefficient Write Enable
bits : 15 - 15 (1 bit)
access : read-write
CIVWD : CIV coefficient
bits : 16 - 30 (15 bit)
access : read-write
CIVWEN : CIV Coefficient Write Enable
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRESTARTMAFLTDOUT : RSSI MA filter output value
bits : 0 - 8 (9 bit)
access : read-only
No Description
address_offset : 0x280 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCTRL1 : AD control
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x284 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCTRL2 : AD control
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x288 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADRSSI0 : ANT0 RSSI
bits : 0 - 9 (10 bit)
access : read-only
ADRSSI1 : ANT1 RSSI
bits : 16 - 25 (10 bit)
access : read-only
No Description
address_offset : 0x28C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCORR0 : ANT0 CORR
bits : 0 - 16 (17 bit)
access : read-only
ADSTAT1 : ADSTAT1
bits : 17 - 31 (15 bit)
access : read-only
No Description
address_offset : 0x290 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADRSSI0P : Previous ANT0 RSSI
bits : 0 - 9 (10 bit)
access : read-only
ADRSSI1P : Previous ANT1 RSSI
bits : 16 - 25 (10 bit)
access : read-only
No Description
address_offset : 0x294 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCORR0P : Previous ANT0 CORR
bits : 0 - 16 (17 bit)
access : read-only
ADSTAT2 : ADSTAT2
bits : 17 - 31 (15 bit)
access : read-only
No Description
address_offset : 0x298 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADAGCGRTHR : AGC gain reduced threshold
bits : 0 - 5 (6 bit)
access : read-write
ADRSSIGRTHR : RSSI gain reduced threshold
bits : 16 - 25 (10 bit)
access : read-write
ADGRMODE : Gain reduced mode
bits : 30 - 31 (2 bit)
access : read-write
No Description
address_offset : 0x29C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDIRECTCORR : AD direct selection correlation
bits : 0 - 16 (17 bit)
access : read-write
No Description
address_offset : 0x2A0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADBACORRTHR : AD best antenna correlation thr
bits : 0 - 16 (17 bit)
access : read-write
ADBACORRDIFF : AD best antenna correlation diff
bits : 17 - 31 (15 bit)
access : read-write
No Description
address_offset : 0x2A4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADBARSSITHR : AD best antenna RSSI thr
bits : 0 - 9 (10 bit)
access : read-write
ADBARSSIDIFF : AD best antenna RSSI diff
bits : 16 - 25 (10 bit)
access : read-write
No Description
address_offset : 0x2A8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADBAAGCTHR : AD best antenna AGC thr
bits : 0 - 5 (6 bit)
access : read-write
ADBAMODE : AD best antenna mode
bits : 8 - 9 (2 bit)
access : read-write
No Description
address_offset : 0x2AC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCORR1 : ANT1 CORR
bits : 0 - 16 (17 bit)
access : read-only
No Description
address_offset : 0x2B0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCORR1P : Previous ANT1 CORR
bits : 0 - 16 (17 bit)
access : read-only
No Description
address_offset : 0x2B4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADSTATEC : Current AD state
bits : 0 - 3 (4 bit)
access : read-only
ADSTATEP : Previous AD state
bits : 4 - 7 (4 bit)
access : read-only
ADSTATEP2 : 2nd previous AD state
bits : 8 - 11 (4 bit)
access : read-only
ADSTATEN : Next AD state
bits : 12 - 15 (4 bit)
access : read-only
ADTD0 : timdet0
bits : 16 - 16 (1 bit)
access : read-only
ADTD0P : timdet0p
bits : 17 - 17 (1 bit)
access : read-only
ADTD1 : timdet1
bits : 18 - 18 (1 bit)
access : read-only
ADTD1P : timdet1p
bits : 19 - 19 (1 bit)
access : read-only
ADAS : antsel
bits : 20 - 20 (1 bit)
access : read-only
ADBA : best_antenna
bits : 21 - 21 (1 bit)
access : read-only
ADSTATREAD : ADSTATREAD
bits : 22 - 22 (1 bit)
access : read-write
ADSTAT1SEL : ADSTAT1SEL
bits : 23 - 26 (4 bit)
access : read-write
ADSTAT2SEL : ADSTAT2SEL
bits : 27 - 30 (4 bit)
access : read-write
No Description
address_offset : 0x2B8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADOSETANT0 : AD output mux
bits : 0 - 15 (16 bit)
access : read-write
ADOSETANT1 : AD output mux
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x2BC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADOSWITCHANT : AD output mux
bits : 0 - 15 (16 bit)
access : read-write
ADORESTARTRX : AD output mux
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ANT0CORR : ANT0 Correlation value
bits : 0 - 9 (10 bit)
access : read-only
ANT1CORR : ANT1 Correlation value
bits : 10 - 19 (10 bit)
access : read-only
ANT0OUT : ANT0 OUTPUT
bits : 30 - 30 (1 bit)
access : read-only
ANT1OUT : ANT1 OUTPUT
bits : 31 - 31 (1 bit)
access : read-only
No Description
address_offset : 0x2C0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADOQUAL0UPDATE : AD output mux
bits : 0 - 15 (16 bit)
access : read-write
ADOQUAL1UPDATE : AD output mux
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x2C4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADOQUAL0CLEAR : AD output mux
bits : 0 - 15 (16 bit)
access : read-write
ADOQUAL1CLEAR : AD output mux
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x2C8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADOMUX : AD output mux
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x2CC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADNEXTSTATESW0 : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADNEXTSTATESW1 : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x2D0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADNEXTSTATESW2 : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADNEXTSTATESW3 : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x2D4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADNEXTSTATESW4 : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADNEXTSTATESW5 : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x2D8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADNEXTSTATESW6 : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADNEXTSTATESW7 : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x2DC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADNEXTSTATESW8 : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADNEXTSTATESW9 : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x2E0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADNEXTSTATESW10 : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADNEXTSTATESW11 : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x2E4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADNEXTSTATESW12 : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADNEXTSTATESW13 : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x2E8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADNEXTSTATESW14 : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADNEXTSTATESW15 : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x2EC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADFSMCOND0ENA : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADFSMCOND1ENA : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x2F0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADFSMCOND2ENA : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADFSMCOND3ENA : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x2F4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADFSMCOND0ENB : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADFSMCOND1ENB : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x2F8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADFSMCOND2ENB : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADFSMCOND3ENB : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x2FC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADFSMCONDSEL : AD next states
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FDEVEST : Frequency Deviation Error Estimation
bits : 0 - 5 (6 bit)
access : read-only
DEMODSOFT : PHASE DEMOD Soft code
bits : 6 - 18 (13 bit)
access : read-only
CFEPHDIFF : CEF PHASE DIFF INPUT
bits : 19 - 28 (10 bit)
access : read-only
MINCOSTPASS : Min.COST Threshold Pass
bits : 29 - 29 (1 bit)
access : read-only
CFEDSADET : CFE-based DSA Detection
bits : 31 - 31 (1 bit)
access : read-only
No Description
address_offset : 0x300 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADFSMNEXTFORCE : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADFSMCONDTRUE : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x304 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADITENTEREN : AD FSM IT enter enable
bits : 0 - 15 (16 bit)
access : read-write
ADITLEAVEEN : AD FSM IT leave enable
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x308 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADENTERFREEZEEN : AD FSM enter freeze enable
bits : 0 - 0 (1 bit)
access : read-write
ADLEAVEFREEZEEN : AD FSM leave freeze enable
bits : 1 - 1 (1 bit)
access : read-write
ADFROZEN : AD FSM frozen
bits : 2 - 2 (1 bit)
access : read-only
ADUNFREEZENEXT : AD FSM unfreeze next state
bits : 3 - 6 (4 bit)
access : read-write
ADUNFREEZE : AD FSM unfreeze
bits : 16 - 16 (1 bit)
access : write-only
No Description
address_offset : 0x30C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADITENTERSTATUS : AD FSM IT enter status
bits : 0 - 15 (16 bit)
access : read-only
ADITLEAVESTATUS : AD FSM IT leave status
bits : 16 - 31 (16 bit)
access : read-only
No Description
address_offset : 0x310 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADFSMCOND0ENC : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADFSMCOND1ENC : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x314 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADFSMCOND2ENC : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADFSMCOND3ENC : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x318 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADFSMCONDOR0 : AD FSM OR cond
bits : 0 - 15 (16 bit)
access : read-write
ADFSMCONDOR1 : AD FSM OR cond
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x31C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADFSMCOND0END : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADFSMCOND1END : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x320 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADFSMCOND2END : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADFSMCOND3END : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x324 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADOSETANTFORCE : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADORESTARTRXFORCE : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x328 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADOQUALUPDATEFORCE : AD next states
bits : 0 - 15 (16 bit)
access : read-write
ADOQUALCLEARFORCE : AD next states
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x32C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADODEMODRXREQ : AD next states
bits : 0 - 31 (32 bit)
access : read-write
address_offset : 0x330 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCRNCOFF : BCRNCOFF
bits : 0 - 21 (22 bit)
access : read-write
BCRERRRSTEN : BCRERRRSTEN
bits : 22 - 22 (1 bit)
access : read-write
BCRFBBYP : BCRFBBYP
bits : 23 - 23 (1 bit)
access : read-write
BCRALIGN : BCRALIGN
bits : 24 - 24 (1 bit)
access : read-write
DISTOGG : DISTOGG
bits : 25 - 25 (1 bit)
access : read-write
CRSLOW : CRSLOW
bits : 26 - 28 (3 bit)
access : read-write
CRFAST : CRFAST
bits : 29 - 31 (3 bit)
access : read-write
address_offset : 0x334 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRGAIN : CRGAIN
bits : 0 - 10 (11 bit)
access : read-write
CGAINX2 : CGAINX2
bits : 11 - 11 (1 bit)
access : read-write
RXNCOCOMP : RXNCOCOMP
bits : 12 - 12 (1 bit)
access : read-write
RXCOMPLAT : RXCOMPLAT
bits : 13 - 13 (1 bit)
access : read-write
ESCMIDPT : ESCMIDPT
bits : 14 - 14 (1 bit)
access : read-write
DISMIDPT : DISMIDPT
bits : 15 - 15 (1 bit)
access : read-write
BCROSR : BCROSR
bits : 16 - 27 (12 bit)
access : read-write
ESTOSREN : ESTOSREN
bits : 28 - 28 (1 bit)
access : read-write
BCRSWSYCW : BCRSWSYCW
bits : 29 - 29 (1 bit)
access : read-write
PHCOMP2FSK : PHCOMP2FSK
bits : 30 - 30 (1 bit)
access : read-write
SLICEFBBYP : SLICE BYP
bits : 31 - 31 (1 bit)
access : read-write
address_offset : 0x338 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCRDEMODEN : BCR DEMOD ENABLE
bits : 0 - 0 (1 bit)
access : read-write
PULCORRBYP : BYPASS PULSE CORR
bits : 1 - 1 (1 bit)
access : read-write
RAWSYN : RAWSYN
bits : 2 - 2 (1 bit)
access : read-write
CONSCHKBYP : CONSCHKBYP
bits : 3 - 3 (1 bit)
access : read-write
PH0SIZE : PH0SIZE
bits : 4 - 4 (1 bit)
access : read-write
LOCKUPBYP : LOCKUPBYP
bits : 5 - 5 (1 bit)
access : read-write
RAWFASTMA : RAWFASTMA
bits : 6 - 6 (1 bit)
access : read-write
SPIKEREMOV : SPIKEREMOV
bits : 7 - 7 (1 bit)
access : read-write
RAWFLTSEL : RAWFLTSEL
bits : 8 - 9 (2 bit)
access : read-write
MANCHDLY : Manchester decoder delay
bits : 10 - 10 (1 bit)
access : read-write
CICDINSCALE : CIC INPUT SCALE
bits : 11 - 11 (1 bit)
access : read-write
DATAFLTBY : DATA filter Bypass
bits : 12 - 12 (1 bit)
access : read-write
PREATH : PREATH
bits : 14 - 18 (5 bit)
access : read-write
SKIPSYN : SKIPSYN
bits : 19 - 19 (1 bit)
access : read-write
PMPATTERN : PMPATTERN
bits : 20 - 21 (2 bit)
access : read-write
NONSTDPK : NONSTDPK
bits : 22 - 22 (1 bit)
access : read-write
SLICERFAST : SLICERFAST
bits : 23 - 23 (1 bit)
access : read-write
DIRECTMODE : Direct mode
bits : 24 - 24 (1 bit)
access : read-write
DETECTORSEL : DETECTORSEL
bits : 25 - 27 (3 bit)
access : read-write
BBPMDETEN : BINARY BIT PREAMBLE DET
bits : 28 - 28 (1 bit)
access : read-write
MANCHPH : Manchester decoder phase
bits : 29 - 29 (1 bit)
access : read-write
INVRXBIT : INVRXBIT
bits : 30 - 30 (1 bit)
access : read-write
PHSRCSEL : PHSRCSEL
bits : 31 - 31 (1 bit)
access : read-write
address_offset : 0x33C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OOKFRZEN : OOKFRZEN
bits : 0 - 0 (1 bit)
access : read-write
RAWGAIN : RAWGAIN
bits : 1 - 2 (2 bit)
access : read-write
NOISEFLEST : Noise Floore Estimation Enable
bits : 3 - 3 (1 bit)
access : read-write
PKTRUNK : PKD TRUNKATION DISABLE
bits : 5 - 5 (1 bit)
access : read-write
MAFREQDWN : MAFREQDWN
bits : 6 - 6 (1 bit)
access : read-write
SQUELCLKEN : Squelch bit clock enable
bits : 7 - 7 (1 bit)
access : read-write
BWPK : BWPK
bits : 8 - 12 (5 bit)
access : read-write
ABPK : ABOVE PEAK
bits : 13 - 15 (3 bit)
access : read-write
DECAYSWAL : DECAYSWAL
bits : 16 - 17 (2 bit)
access : read-write
DECAY : DECAY
bits : 18 - 21 (4 bit)
access : read-write
ATTACK : ATTACK
bits : 22 - 24 (3 bit)
access : read-write
SQUELCH : SQUELCH
bits : 25 - 27 (3 bit)
access : read-write
RAWNDEC : RAW DATA DEC
bits : 28 - 30 (3 bit)
access : read-write
BCRDEMODOOK : BCR Demod OOK enable
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMDETCORR : Correlation value
bits : 0 - 7 (8 bit)
access : read-only
TIMDETFREQOFFEST : Frequency offset estimate
bits : 8 - 15 (8 bit)
access : read-only
TIMDETPREERRORS : Preamble errors
bits : 16 - 19 (4 bit)
access : read-only
TIMDETPASS : Timing detection pass
bits : 24 - 24 (1 bit)
access : read-only
TIMDETINDEX : Timing detection index
bits : 25 - 28 (4 bit)
access : read-only
address_offset : 0x340 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZEROOFF : ZERO OFFSET
bits : 0 - 6 (7 bit)
access : read-write
LARGEFREQERR : LARGEFREQERR
bits : 15 - 15 (1 bit)
access : read-write
AFCGAINOVRFLW : AFCGAINOVRFLW
bits : 29 - 29 (1 bit)
access : read-write
EN2TBEST : EN2TBEST
bits : 30 - 30 (1 bit)
access : read-write
ENAFCCLKSW : ENAFCCLKSW
bits : 31 - 31 (1 bit)
access : read-write
address_offset : 0x344 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LGWAIT : LGWAIT
bits : 0 - 3 (4 bit)
access : read-write
SHWAIT : SHWAIT
bits : 4 - 7 (4 bit)
access : read-write
GEARSW : GEARSW
bits : 14 - 15 (2 bit)
access : read-write
AFCMAEN : AFCMAEN
bits : 18 - 18 (1 bit)
access : read-write
ENFZPMEND : ENFZPMEND
bits : 19 - 19 (1 bit)
access : read-write
NONFRZEN : NONFRZEN
bits : 20 - 20 (1 bit)
access : read-write
ONESHOTWAITCNT : ONESHOTWAITCNT
bits : 21 - 24 (4 bit)
access : read-write
ONESHOTAFCEN : ONESHOTAFCEN
bits : 25 - 25 (1 bit)
access : read-write
SKIPPMDET : SKIPPMDET
bits : 26 - 26 (1 bit)
access : read-write
PMRSTEN : PM RST Enable
bits : 27 - 27 (1 bit)
access : read-write
ENAFCFRZ : ENAFCFRZ
bits : 28 - 28 (1 bit)
access : read-write
HALFPHCOMP : HALFPHCOMP
bits : 29 - 29 (1 bit)
access : read-write
ENAFC : ENAFC
bits : 30 - 30 (1 bit)
access : read-write
ENFBPLL : ENFBPLL
bits : 31 - 31 (1 bit)
access : read-write
address_offset : 0x348 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THD4GFSK : THD4GFSK
bits : 0 - 15 (16 bit)
access : read-write
CODE4GFSK : CODE4GFSK
bits : 16 - 23 (8 bit)
access : read-write
PHCOMPBYP : PHCOMPBYP
bits : 30 - 30 (1 bit)
access : read-write
EN4GFSK : Enable BCR demod 4GFSK
bits : 31 - 31 (1 bit)
access : read-write
address_offset : 0x34C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHCOMP4FSK0 : PHCOMP4FSK0
bits : 0 - 6 (7 bit)
access : read-write
PHCOMP4FSK1 : PHCOMP4FSK1
bits : 8 - 14 (7 bit)
access : read-write
FDEVCOMPRATIO : Freq. Dev. Comp. Ratio
bits : 16 - 22 (7 bit)
access : read-write
FDEVCOMPEN : Freq. Dev. Comp. Enable
bits : 23 - 23 (1 bit)
access : read-write
S2PMAP : S2PMAP
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : S2p_mapping0
{a1,a0}, {a3,a2}, {a5,a4}
1 : S2p_mapping1
{a0,a1}, {a2,a3}, {a4,a5}
2 : S2p_mapping2
{a0,a_1},{a2,a1}, {a4,a3}
3 : S2p_mapping3
{a_1,,a0}, {a1,a2},{a3,a4}
End of enumeration elements list.
Recommended not to be used.
address_offset : 0x350 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWANTTIMER : SWANTTIMER
bits : 5 - 10 (6 bit)
access : read-write
BECOEN : BECO MODE Enable
bits : 12 - 12 (1 bit)
access : read-write
SKIP2PHTHD : SKIP2PHTHD
bits : 15 - 15 (1 bit)
access : read-write
ANWAIT : ANWAIT
bits : 16 - 21 (6 bit)
access : read-write
AGCGAINUPB : AGC GAIN UP
bits : 22 - 22 (1 bit)
access : read-write
SKIP2PH : SKIP2PH
bits : 23 - 23 (1 bit)
access : read-write
BYP1P5 : BYP1P5
bits : 24 - 24 (1 bit)
access : read-write
ANT2PMTHD : ANT2PMTHD
bits : 25 - 28 (4 bit)
access : read-write
BCRDEMODANTDIV : BCRDEMODANTDIV
bits : 31 - 31 (1 bit)
access : read-write
address_offset : 0x354 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSSIARRTHD : RSSIARRTHD
bits : 0 - 7 (8 bit)
access : read-write
RSSIMATAP : RSSIMATAP
bits : 8 - 8 (1 bit)
access : read-write
MUTERSSICNT : MUTERSSICNT
bits : 10 - 12 (3 bit)
access : read-write
PRWOFFSET : Power measurement Offset
bits : 25 - 31 (7 bit)
access : read-write
address_offset : 0x358 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCHPRDLO : SCHPRDLO
bits : 0 - 2 (3 bit)
access : read-write
EYEQUALEN : EYEQUALEN
bits : 3 - 3 (1 bit)
access : read-write
SCHPRDHI : SCHPRDHI
bits : 4 - 6 (3 bit)
access : read-write
ARRRSTEN : ARRRSTEN
bits : 7 - 7 (1 bit)
access : read-write
ARRTOLER : ARRTOLER
bits : 8 - 12 (5 bit)
access : read-write
DIFF0RSTEN : DIFF0RSTEN
bits : 13 - 13 (1 bit)
access : read-write
PHSPIKETHD : PHASE SPIKE
bits : 14 - 20 (7 bit)
access : read-write
ARRDETTHD : ARRDETTHD
bits : 21 - 24 (4 bit)
access : read-write
SCHFRZEN : SCHFRZEN
bits : 25 - 25 (1 bit)
access : read-write
EYEXESTEN : EYEXESTEN
bits : 26 - 26 (1 bit)
access : read-write
EYEXESTFAST : EYEXESTFAST
bits : 27 - 27 (1 bit)
access : read-write
ARRDETSRC : ARR DET SRC
bits : 28 - 29 (2 bit)
access : read-write
ARRQPM : ARRIVAL QUALIFY PM DET
bits : 30 - 30 (1 bit)
access : read-write
ARRDETEN : ARRDETEN
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x35C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARREYEQUAL : ARREYEQUAL
bits : 0 - 6 (7 bit)
access : read-write
EYEOPENTHD : Expected Deviation
bits : 7 - 17 (11 bit)
access : read-write
SYMBWMAX : Expected MAX Duration
bits : 18 - 22 (5 bit)
access : read-write
SYMBWMIN : Expected MIN Duration
bits : 23 - 25 (3 bit)
access : read-write
BCRCFESRC : BCR CFE INPUT SOURCE
bits : 26 - 26 (1 bit)
access : read-write
CFEQUALTHD : BCR Demod CFE Qualifer THRD
bits : 27 - 29 (3 bit)
access : read-write
KSICOMPEN : BCR KSI COMP. ENABLE
bits : 30 - 30 (1 bit)
access : read-write
ENCFEQUAL : Enable BCE CFE Qualifer
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x360 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CONSYMOL : Max.NO. of CONSECTIVE
bits : 0 - 4 (5 bit)
access : read-write
RAWDCHKALWAYON : RAW DATA Quality Check Always on
bits : 5 - 5 (1 bit)
access : read-write
OUTRNGCHK : OUT RANGE CHECK
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x364 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCRKSI1 : BCR KSI1
bits : 0 - 6 (7 bit)
access : read-write
BCRKSI2 : BCR KSI2
bits : 8 - 14 (7 bit)
access : read-write
BCRKSI3 : BCR KSI3
bits : 16 - 22 (7 bit)
access : read-write
No Description
address_offset : 0x368 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCRPMEXP : BCR PM Pattern
bits : 0 - 15 (16 bit)
access : read-write
BCRCFECOSTTHD : BCR MinCOST THD
bits : 16 - 23 (8 bit)
access : read-write
BCRPHSCALE : SCALING FACTOR
bits : 25 - 26 (2 bit)
access : read-write
BCRCFESCHWIN : BCR CFEDSA WIN
bits : 27 - 29 (3 bit)
access : read-write
BCRPMACQWIN : BCR PM CORR SIZE
bits : 30 - 31 (2 bit)
access : read-write
No Description
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DETSTATE : Detection FSM state
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
0 : OFF
Off state
10 : TIMINGSEARCH
Timing search
20 : PRESEARCH
Preamble search
30 : FRAMESEARCH
Frame search
40 : RXFRAME
Payload Detection
50 : FRAMEDETMODE0
Timing search with sliding window (FDM0)
End of enumeration elements list.
DSASTATE : Demodulator DSA FSM state
bits : 7 - 9 (3 bit)
access : read-only
Enumeration:
0 : IDLE
IDLE state
1 : ARRIVALCHK
Arrival Check
2 : STATUSCHK
Status Check
3 : SAMPPW
SAMP_PW
4 : WAITPWRUP
WAIT_PWRUP
5 : WAITDSALO
WAIT_DSALO
6 : WAITABORT
WAIT_ABORT
7 : STOP
STOP
End of enumeration elements list.
LRBLESTATE : Demodulator long-range BLE FSM state
bits : 10 - 14 (5 bit)
access : read-only
Enumeration:
0 : IDLE
IDLE state
1 : CLEANUP
CLEANUP
2 : CORRCOE
CORRCOE
3 : WAITLRDSA
WAIT_LR_DSA
4 : MAXCORR
MAXCORR
5 : WAITRDY
WAIT_RDY
6 : FEC1DATA
FEC1_DATA
7 : FEC1ACK
FEC1_ACK
8 : PAUSE
PAUSE
9 : FEC2DATA
FEC2_DATA
10 : FEC2ACK
FEC2_ACK
11 : TRACKCUR
TRACK_CUR
12 : TRACKEAR
TRACK_EAR
13 : TRACKLAT
TRACK_LAT
14 : TRACKDONE
TRACK_DONE
15 : TDECISION
T_DECISION
16 : STOP
STOP
End of enumeration elements list.
NBBLESTATE : Demodulator Narrow-band BLE FSM state
bits : 15 - 19 (5 bit)
access : read-only
Enumeration:
0 : IDLE
IDLE state
1 : VTINITI
VTINITI
2 : ADDRNXT
ADDR_NXT
3 : INICOST
INI_COST
4 : CALCCOST
CALC_COST
5 : INITALACQU
INITAL_ACQU
6 : INITALCOSTCALC
INITAL_COST_CALC
7 : MINCOSTCALC
MIN_COST_CALC
8 : FREQACQU
FREQ_ACQU
9 : FREQACQUDONE
FREQ_ACQU_DONE
10 : TIMINGACQUEARLY
TIMING_ACQU_EARLY
11 : TIMINGACQUCURR
TIMING_ACQU_CURR
12 : TIMINGACQULATE
TIMING_ACQU_LATE
13 : TIMINGACQUDONE
TIMING_ACQU_DONE
14 : VIRTBIINIT0
VIRTBI_INIT0
15 : VIRTBIINIT1
VIRTBI_INIT1
16 : VIRTBIRXSYNC
VIRTBI_RXSYNC
17 : VIRTBIRXPAYLOAD
VIRTBI_RXPAYLOAD
18 : HARDRXSYNC
HARD_RXSYNC
19 : HARDXPAYLOAD
HARD_RXPAYLOAD
20 : TRACKFREQ
TRACK_FREQ
21 : TRACKTIMEARLY
TRACK_TIM_EARLY
22 : TRACKTIMCURR
TRACK_TIM_CURR
23 : TRACKTIMLATE
TRACK_TIM_LATE
24 : TRACKDONE
TRACK_DONE
25 : TRACKDECISION
TRACK_DECISION
26 : STOP
STOP
27 : WAITACK
WAIT_ACK
28 : DEBUG
DEBUG
End of enumeration elements list.
ANTDIVSTATE : Antenna diversity control state
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : IDLE
Idle state
1 : FIRST_ANT0
First ANT0 selection
2 : FIRST_ANT1
First ANT1 selection
3 : TIMSEARCH_ANT0
Timing search on ANT0
4 : TIMSEARCH_ANT1
Timing search on ANT1
5 : TIMDET_ANT0
Check ANT1 after timing detecton ANT0
6 : TIMDET_ANT1
Check ANT0 after timing detecton ANT1
7 : EVALUATE
Evaluate and select better antenna
8 : TIMSEARCH_SELECTED
Searching on better antenna
9 : TIMDET_SELECTED
Selected better antenna
10 : REPEAT_ANT0
Repeat ANT0
11 : REPEAT_ANT1
Repeat ANT1
15 : MANUAL
Manual mode
End of enumeration elements list.
No Description
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FREQOFFEST : Frequency offset estimate
bits : 0 - 12 (13 bit)
access : read-only
CORRVAL : Correlation value
bits : 13 - 23 (11 bit)
access : read-only
SOFTVAL : Soft detection value
bits : 24 - 31 (8 bit)
access : read-only
No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable peripheral clock to this module
bits : 0 - 0 (1 bit)
access : read-write
No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFCADJRX : AFC adjustment for RX
bits : 0 - 18 (19 bit)
access : read-only
AFCSCALEM : AFC scaling mantissa
bits : 20 - 24 (5 bit)
access : read-write
AFCSCALEE : AFC scaling exponent
bits : 28 - 31 (4 bit)
access : read-write
No Description
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPARE : Spare register
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFCADJTX : AFC adjustment for TX
bits : 0 - 18 (19 bit)
access : read-only
AFCSCALEM : AFC scaling mantissa
bits : 20 - 24 (5 bit)
access : read-write
AFCSCALEE : AFC scaling exponent
bits : 28 - 31 (4 bit)
access : read-write
No Description
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIGIQSWAPEN : Digital I/Q swap enable
bits : 4 - 4 (1 bit)
access : read-write
No Description
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FDM0DIFFDIS : Frame Detection Mode 0 disable
bits : 0 - 0 (1 bit)
access : read-write
MAPFSK : Mapping of FSK symbols
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
0 : MAP0
4FSK: Symbol 11, 10, 00, 01 for decreasing frequency. 2FSK/MSK/ASK/OOK: Symbol 1 is high/positive frequency or high amplitude, symbol 0 is low/negative frequency or low amplitude.
1 : MAP1
4FSK: Symbol 01, 00, 10, 11 for decreasing frequency. 2FSK/MSK/ASK/OOK: Symbol 0 is high/negative frequency or high amplitude, symbol 1 is low/negative frequency or low amplitude.
2 : MAP2
4FSK: Symbol 10, 11, 01, 00 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined.
3 : MAP3
4FSK: Symbol 00, 01, 11, 10 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined.
4 : MAP4
4FSK: Symbol 11, 01, 00, 10 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined.
5 : MAP5
4FSK: Symbol 10, 00, 01, 11 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined.
6 : MAP6
4FSK: Symbol 01, 11, 10, 00 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined.
7 : MAP7
4FSK: Symbol 00, 10, 11, 01 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined.
End of enumeration elements list.
CODING : Symbol coding
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : NRZ
Non Return to Zero
1 : MANCHESTER
Manchester Coding
2 : DSSS
Direct Sequence Spread Spectrum
3 : LINECODE
Line code. Maps 0 to 0011 symbol and 1 to 1100 symbols
End of enumeration elements list.
MODFORMAT : Modulation format
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : FSK2
Frequency Shift Keying with 2 symbols
1 : FSK4
Frequency Shift Keying with 4 symbols
2 : BPSK
Binary Phase Shift Keying
3 : DBPSK
Differentially encoded Binary Phase Shift Keying
4 : OQPSK
Half Sine Shaped Offset Quadrature Phase Shift Keying
5 : MSK
Minimum Shift Keying
6 : OOKASK
On Off Keying and Amplitude Shift Keying
End of enumeration elements list.
DUALCORROPTDIS : Dual Correlation Optimization Disable
bits : 9 - 9 (1 bit)
access : read-write
OOKASYNCPIN : OOK asynchronous pin mode
bits : 10 - 10 (1 bit)
access : read-write
DSSSLEN : DSSS length
bits : 11 - 15 (5 bit)
access : read-write
DSSSSHIFTS : DSSS shifts
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : NOSHIFT
No symbols are defined by shifting.
1 : SHIFT1
Next symbol generated by 1 cyclic shift.
2 : SHIFT2
Next symbol generated by 2 cyclic shifts.
3 : SHIFT4
Next symbol generated by 4 cyclic shifts.
4 : SHIFT8
Next symbol generated by 8 cyclic shifts.
5 : SHIFT16
Next symbol generated by 16 cyclic shifts.
End of enumeration elements list.
DSSSDOUBLE : DSSS double
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
0 : DIS
Doubling is disabled.
1 : INV
Doubling is enabled by using inverted symbols.
2 : CONJ
Doubling is enabled by using complex conjugated symbols.
End of enumeration elements list.
DETDIS : Detection disable
bits : 21 - 21 (1 bit)
access : read-write
DIFFENCMODE : Differential encoding mode
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
0 : DIS
Differential Encoding is disabled.
1 : RR0
Transmit the XOR-ed value of the Raw symbol and the last Raw symbol. Initial Raw symbol is 0.
2 : RE0
Transmit the XOR-ed value of the Raw symbol and the last Encoded symbol. Initial Encoded symbol is 0.
3 : RR1
Transmit the XOR-ed value of the Raw symbol and the last Raw symbol. Initial Raw symbol is 1.
4 : RE1
Transmit the XOR-ed value of the Raw symbol and the last Encoded symbol. Initial Encoded symbol is 1.
End of enumeration elements list.
SHAPING : Shaping filter
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
Filter disabled.
1 : ODDLENGTH
Filter has odd length. Filter uses coefficients 0,1,2,3,4,5,6,7,8,7,6,5,4,3,2,1,0.
2 : EVENLENGTH
Filter has even length. Filter uses coefficients 0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0.
3 : ASYMMETRIC
Filter has asymmetrical coefficients. Filter uses coefficients 0,1,2,3,4,5,6,7.
End of enumeration elements list.
DEMODRAWDATASEL : Demod raw data select
bits : 27 - 29 (3 bit)
access : read-write
Enumeration:
0 : DIS
Disabled.
1 : ENTROPY
1-bit entropy source extracted from the RF receive chain, to be used for random number generation.
2 : ADC
2 * 3-bit I and Q ADC data.
3 : FILTLSB
2 * 16-bit I and Q channel filtered data downmixed to zero-IF. The receive signal chain has 19 bits dynamic range at this point, and the FILTLSB setting outputs the 16 least significant bits (with saturation).
4 : FILTMSB
2 * 16-bit I and Q channel filtered data downmixed to zero-IF. The receive signal chain has 19 bits dynamic range at this point, and the FILTMSB setting outputs the 16 most significant bits (with truncation).
5 : FILTFULL
2 * 19-bit I and Q channel filtered data downmixed to zero-IF. The FILTFULL option will output all 19 bits of dynamic range, sign extended to 32 bits.
6 : FREQ
8-bit received frequency data (or logarithmic amplitude for ASK/OOK).
7 : DEMOD
8-bit demodulated data (freq/amp/phase). When coherent detection is enabled, only the in-phase component is selected.
End of enumeration elements list.
FRAMEDETDEL : FRAMEDET delay
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : DEL0
No delay
1 : DEL8
8 baud delay
2 : DEL16
16 baud delay
3 : DEL32
32 baud delay
End of enumeration elements list.
No Description
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCBITS : Number of sync-word bits
bits : 0 - 4 (5 bit)
access : read-write
SYNCERRORS : Maximum number of sync errors
bits : 5 - 8 (4 bit)
access : read-write
DUALSYNC : Dual sync words.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Demodulator only searches for SYNC0.
1 : ENABLED
Demodulator searches for SYNC0 and SYNC1 in parallel.
End of enumeration elements list.
TXSYNC : Transmit sync word.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SYNC0
Modulator transmits SYNC0.
1 : SYNC1
Modulator transmits SYNC1.
End of enumeration elements list.
SYNCDATA : Sync data.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
SYNC is not part of transmit payload. Modulator adds SYNC in transmit.
1 : ENABLED
SYNC is part of transmit payload. Modulator does not add SYNC in transmit.
End of enumeration elements list.
SYNC1INV : SYNC1 invert.
bits : 12 - 12 (1 bit)
access : read-write
COMPMODE : Compensation mode
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DIS
Compensation is disabled.
1 : PRELOCK
Compensation locks when preamble is detected.
2 : FRAMELOCK
Compensation locks when frame is detected.
3 : NOLOCK
Compensation is always running
End of enumeration elements list.
RESYNCPER : Resync period
bits : 16 - 19 (4 bit)
access : read-write
PHASEDEMOD : Phase demodulation
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : BDD
Bit Differential Detection.
1 : MBDD
Multibit Differential Detection.
2 : COH
Coherent Detection.
End of enumeration elements list.
FREQOFFESTPER : Frequency offset estimation period
bits : 22 - 24 (3 bit)
access : read-write
FREQOFFESTLIM : Frequency offset limit
bits : 25 - 31 (7 bit)
access : read-write
No Description
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQITHRESH : Signal Quality Indicator threshold
bits : 0 - 7 (8 bit)
access : read-write
RXFRCDIS : Receive FRC disable
bits : 8 - 8 (1 bit)
access : read-write
RXPINMODE : Receive pin mode
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SYNCHRONOUS
Detected payload bits are clocked out on DOUT. Only setups with 1 bit per symbol are supported.
1 : ASYNCHRONOUS
DOUT is continuously providing the sign of the detected frequency deviation before offset compensation. Only 2/4-FSK is supported.
End of enumeration elements list.
TXPINMODE : Transmit pin mode
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : OFF
Pinmode is turned off. Data is gathered from FRC. DOUT/DCLK clocks out transmitted data.
1 : MFM
Pinmode is turned off. Multi-Level FM Data is gathered from FRC. No support for frame handling nor coding
2 : ASYNCHRONOUS
DIN/PRS controls transmitted baud directly. DCLK is set to 0. No support for frame handling nor coding. Only 2-FSK and OOK/ASK can be used.
3 : SYNCHRONOUS
DIN/PRS is sampled on the rising edge of DCLK and used as payload. Frame handling and coding is supported. Only setups with 1 bit per symbol is supported.
End of enumeration elements list.
DATAFILTER : Datafilter
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : DISABLED
Datafilter disabled
1 : SHORT
Short datafilter enabled. 2*RXBRFRAC should be more than 3.
2 : MEDIUM
Medium datafilter enabled. 2*RXBRFRAC should be more than 4.
3 : LONG
Long datafilter enabled. 2*RXBRFRAC should be more than 5.
4 : LEN6
Datafilter with length 6 enabled. 2*RXBRFRAC should be more than 6.
5 : LEN7
Datafilter with length 7 enabled. 2*RXBRFRAC should be more than 7.
6 : LEN8
Datafilter with length 8 enabled. 2*RXBRFRAC should be more than 8.
7 : LEN9
Datafilter with length 9 enabled. 2*RXBRFRAC should be more than 9.
End of enumeration elements list.
BRDIVA : Baudrate division factor A
bits : 15 - 18 (4 bit)
access : read-write
BRDIVB : Baudrate division factor B
bits : 19 - 22 (4 bit)
access : read-write
DEVMULA : Deviation multiplication factor A
bits : 23 - 24 (2 bit)
access : read-write
DEVMULB : Deviation multiplication factor B
bits : 25 - 26 (2 bit)
access : read-write
RATESELMODE : Rate select mode
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
0 : NOCHANGE
No rate change. BRDIVA/DEVMULA is used for entire frame.
1 : PAYLOAD
Change rate for payload. BRDIVA/DEVMULA is used for header and BRDIVB/DEVMULB is used for payload.
2 : FRC
FRC selects between BRDIVA/DEVMULA and BRDIVB/DEVMULB for each symbol in the payload. Header uses BRDIVA/DEVMULA.
3 : SYNC
The configured/detected syncword decides the settings used for the payload. SYNC0 uses BRDIVA/DEVMULA and SYNC1 uses BRDIVB/DEVMULB. Header uses BRDIVA/DEVMULA.
End of enumeration elements list.
DEVWEIGHTDIS : Deviation weighting disable.
bits : 29 - 29 (1 bit)
access : read-write
DMASEL : DMA select.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : SOFT
SOFTVAL field
1 : CORR
CORRVAL field
2 : FREQOFFEST
FREQOFFEST field
3 : POE
POE field
End of enumeration elements list.
No Description
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSDINEN : DIN PRS enable
bits : 0 - 0 (1 bit)
access : read-write
TIMINGBASESGAIN : Timing Bases Gain
bits : 1 - 2 (2 bit)
access : read-write
ANTDIVMODE : Antenna Diversity mode
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : ANTENNA0
Antenna 0 (ANT0=1, ANT1=0) is used. It is used to control the anntenna manually no matter which demodulator is selected .
1 : ANTENNA1
Antenna 1 (ANT0=0, ANT1=1) is used.It is used to control the anntenna manually no matter which demodulator is selected .
2 : ANTSELFIRST
Select-First algorithm. It is used for for coh-demod and legacy demod only.
3 : ANTSELCORR
Select-Best algorithm based on correlation value.It is used for for coh-demod and legacy demod only.
4 : ANTSELRSSI
Select-Best algorithm based on RSSI value.It is used for for coh-demod and legacy demod only.
5 : PHDEMODANTDIV
Select PHASE Demod ANT-DIV algorithm
End of enumeration elements list.
ANTDIVREPEATDIS : Antenna diversity repeat disable
bits : 11 - 11 (1 bit)
access : read-write
TSAMPMODE : Timing Search Amplitude Mode
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : OFF
Amplitude is not used during timing search.
1 : ON
Timing detection is disabled for windows where at least one sample is below limit set by TSAMPLIM.
2 : DIFF
Timing detection is disabled for windows where the difference between samples is higher than the limit set by TSAMPLIM.
End of enumeration elements list.
TSAMPDEL : Timing Search Amplitude delay
bits : 14 - 15 (2 bit)
access : read-write
TSAMPLIM : Timing Search Amplitude limit
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISICOMP : Inter Symbol Interference compensation
bits : 0 - 3 (4 bit)
access : read-write
DEVOFFCOMP : Deviation offset compensation
bits : 4 - 4 (1 bit)
access : read-write
PREDISTGAIN : Predistortion gain
bits : 5 - 9 (5 bit)
access : read-write
PREDISTDEB : Predistortion debounce
bits : 10 - 12 (3 bit)
access : read-write
PREDISTAVG : Predistortion Average
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AVG8
Average over 8 samples.
1 : AVG16
Average over 16 samples.
End of enumeration elements list.
PREDISTRST : Predistortion Reset
bits : 14 - 14 (1 bit)
access : read-write
PHASECLICKFILT : Phase click filter
bits : 15 - 21 (7 bit)
access : read-write
SOFTDSSSMODE : Soft DSSS mode
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : CORR0INV
Soft value is inverted value of symbol-0 correlation value.
1 : CORRDIFF
Soft value is difference between correlation values for symbol-0 and symbol-1.
End of enumeration elements list.
ADCSATLEVEL : ADC Saturation Level setting
bits : 23 - 25 (3 bit)
access : read-write
Enumeration:
0 : CONS1
AGC enters fast loop after first saturation sample.
1 : CONS2
2 saturation samples required before AGC enters fast loop.
2 : CONS4
4 saturation samples required before AGC enters fast loop.
3 : CONS8
8 saturation samples required before AGC enters fast loop.
4 : CONS16
16 saturation samples required before AGC enters fast loop.
5 : CONS32
32 saturation samples required before AGC enters fast loop.
6 : CONS64
64 saturation samples required before AGC enters fast loop.
End of enumeration elements list.
ADCSATDENS : ADC Saturation Density setting
bits : 26 - 27 (2 bit)
access : read-write
OFFSETPHASEMASKING : Offset phase masking
bits : 28 - 28 (1 bit)
access : read-write
OFFSETPHASESCALING : Offset phase scaling
bits : 29 - 29 (1 bit)
access : read-write
No Description
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRCALEN : Baudrate calibration enable
bits : 1 - 1 (1 bit)
access : read-write
BRCALMODE : Baudrate calibration mode
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : PEAK
Measure period between peaks in demodulated signal. This mode can give false peaks for high oversampling ratios without sufficient datafiltering.
1 : ZERO
Measure period between zero-crossings in demodulated signal. This mode can miss zero-crossings for high frequency offsets.
2 : PEAKZERO
Combine peak-period and zero-crossing periods. This mode gives best accuracy, but includes weaknesses from both PEAK and ZERO modes.
End of enumeration elements list.
BRCALAVG : Baudrate calibration averaging
bits : 4 - 5 (2 bit)
access : read-write
DETDEL : Detection delay
bits : 6 - 8 (3 bit)
access : read-write
TDEDGE : Timing detection edge mode
bits : 9 - 9 (1 bit)
access : read-write
TREDGE : Timing resynchronization edge mode
bits : 10 - 10 (1 bit)
access : read-write
DSSSCTD : DSSS Correlation Threshold Disable
bits : 11 - 11 (1 bit)
access : read-write
BBSS : Baseband Signal Selection
bits : 12 - 15 (4 bit)
access : read-write
POEPER : Phase Offset Estimation Period
bits : 16 - 19 (4 bit)
access : read-write
DEMODRAWDATASEL2 : Demod raw data select 2
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : DIS
Disabled.
1 : COH
Coherent demod 5-bit I and Q input data, 10-bit I and Q data after FOE/POE.
2 : CORR
4-bit max_corr_index and 17-bit max_corr .
3 : CHPW
8-bit channel power and 4-bit BBSSMUX
4 : BBPF
11-bit pre-filter correlation output for BLR and 11-bit pre-filter correlation output for COH demod
5 : FSM
5-bit Narrow-band BLE FSM state, 5-bit Long-range BLE FSM state, 3-bit DSA FSM state, 7-bit Detection FSM State. Captured each time state changes
End of enumeration elements list.
FOEPREAVG : Frequency Offset Estimate Pre-Averaging
bits : 24 - 26 (3 bit)
access : read-write
LINCORR : Linear Correlation
bits : 27 - 27 (1 bit)
access : read-write
RESYNCBAUDTRANS : Resynchronization Baud Transitions
bits : 29 - 29 (1 bit)
access : read-write
RESYNCLIMIT : Resynchronization Limit
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : HALF
Adjust timing if accumulated timing is higher/lower than RESYNCPER/2.
1 : ALWAYS
Adjust timing if accumulated timing is non-zero.
End of enumeration elements list.
No Description
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDREW : Timing Detection Rewind
bits : 0 - 6 (7 bit)
access : read-write
PREBASES : Preamble Bases
bits : 7 - 10 (4 bit)
access : read-write
PSTIMABORT0 : Preamble Search Timing Abort Criteria 0
bits : 11 - 11 (1 bit)
access : read-write
PSTIMABORT1 : Preamble Search Timing Abort Criteria 1
bits : 12 - 12 (1 bit)
access : read-write
PSTIMABORT2 : Preamble Search Timing Abort Criteria 2
bits : 13 - 13 (1 bit)
access : read-write
PSTIMABORT3 : Preamble Search Timing Abort Criteria 3
bits : 14 - 14 (1 bit)
access : read-write
ARW : Allow Received Window
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
0 : SMALLWND
Allow received windows when window size is less than half the RAM size.
1 : ALWAYS
Always allow received windows.
2 : NEVER
Never allow received windows.
3 : PSABORT
Allow received windows right after PSTIMABORTn tests have aborted timing and coherent detection is enabled, or when window size is less than half the RAM size.
End of enumeration elements list.
TIMTHRESHGAIN : Timing Threshold Gain
bits : 17 - 19 (3 bit)
access : read-write
CPLXCORREN : Enable Complex Correlation
bits : 20 - 20 (1 bit)
access : read-write
DSSS3SYMBOLSYNCEN : Enable three symbol sync detection
bits : 21 - 21 (1 bit)
access : read-write
TXDBPSKINV : TX DBPSK modulation encode invert
bits : 22 - 22 (1 bit)
access : read-write
TXDBPSKRAMPEN : TX DBPSK PA Ramp Enable
bits : 23 - 23 (1 bit)
access : read-write
CODINGB : Coding format
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0 : NRZ
Non Return to Zero
1 : MANCHESTER
Manchester Coding
2 : DSSS
Direct Sequence Spread Spectrum
3 : LINECODE
Line code. Maps 0 to 0011 symbol and 1 to 1100 symbols
End of enumeration elements list.
RXBRCALCDIS : RX Baudrate Calculation Disable
bits : 30 - 30 (1 bit)
access : read-write
No Description
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXBRNUM : Transmit baudrate numerator
bits : 0 - 15 (16 bit)
access : read-write
TXBRDEN : Transmit baudrate denominator
bits : 16 - 23 (8 bit)
access : read-write
No Description
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXBRNUM : Receive baudrate numerator
bits : 0 - 4 (5 bit)
access : read-write
RXBRDEN : Receive baudrate denominator
bits : 5 - 9 (5 bit)
access : read-write
RXBRINT : Receive baudrate integer
bits : 10 - 12 (3 bit)
access : read-write
No Description
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEC0 : First decimation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DF3
Decimation Factor 0 = 3. Cutoff 0.050 * f
1 : DF4WIDE
Decimation Factor 0 = 4. Cutoff 0.069 * f
2 : DF4NARROW
Decimation Factor 0 = 4. Cutoff 0.037 * f
3 : DF8WIDE
Decimation Factor 0 = 8. Cutoff 0.012 * f
4 : DF8NARROW
Decimation Factor 0 = 8. Cutoff 0.005 * f
End of enumeration elements list.
DEC1 : Second decimation
bits : 3 - 16 (14 bit)
access : read-write
DEC2 : Third decimation
bits : 17 - 22 (6 bit)
access : read-write
CFOSR : Center Frequency Oversampling Ratio
bits : 23 - 25 (3 bit)
access : read-write
Enumeration:
0 : CF7
Oversampling ratio = 7
1 : CF8
Oversampling ratio = 8
2 : CF12
Oversampling ratio = 12
3 : CF16
Oversampling ratio = 16
4 : CF32
Oversampling ratio = 32
5 : CF0
Center frequency set to 0
End of enumeration elements list.
DEC1GAIN : Second decimation filter gain
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : ADD0
No additional gain. Suggested setting for BW higher than 1kHz
1 : ADD6
6 dB additional gain. Suggested setting for BW between 250 Hz and 1 kHz
2 : ADD12
12 dB additional gain. Suggested setting for BW less than 250 Hz
End of enumeration elements list.
No Description
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : Preamble base
bits : 0 - 3 (4 bit)
access : read-write
BASEBITS : BASE bits
bits : 4 - 5 (2 bit)
access : read-write
PRESYMB4FSK : Preamble symbols 4-FSK
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : OUTER
Symbols corresponding to +/- 3dev.
1 : INNER
Symbols corresponding to +/- dev.
End of enumeration elements list.
PREERRORS : Preamble errors
bits : 7 - 10 (4 bit)
access : read-write
DSSSPRE : DSSS preamble
bits : 11 - 11 (1 bit)
access : read-write
SYNCSYMB4FSK : Sync symbols 4FSK
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : FSK2
The syncword is 2FSK modulated. Each bit in SYNCn is encoded as a positive or negative deviation. The deviation is controlled by PRESYMB4FSK.
1 : FSK4
The syncword is 4FSK modulated. Every two bits in SYNCn are encoded as a 4FSK symbol.
End of enumeration elements list.
PREAMBDETEN : Binary bit preamble det enable
bits : 13 - 13 (1 bit)
access : read-write
PREWNDERRORS : Preamble window errors
bits : 14 - 15 (2 bit)
access : read-write
TXBASES : TX bases
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC0 : Sync-word 0
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC1 : Sync word 1
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFRAMESENT : Frame sent
bits : 0 - 0 (1 bit)
access : read-write
TXSYNCSENT : Sync word sent
bits : 1 - 1 (1 bit)
access : read-write
TXPRESENT : Preamble sent
bits : 2 - 2 (1 bit)
access : read-write
TXRAMPDONE : Mod ramper idle
bits : 3 - 3 (1 bit)
access : read-write
LDTNOARR : No signal Detected in LDT
bits : 4 - 4 (1 bit)
access : read-write
PHDSADET : PHASE DSA DETECT
bits : 5 - 5 (1 bit)
access : read-write
PHYUNCODEDET : CONCURRENT UNCODED PHY DET
bits : 6 - 6 (1 bit)
access : read-write
PHYCODEDET : CONCURRENT CODED PHY DET
bits : 7 - 7 (1 bit)
access : read-write
RXTIMDET : Timing detected
bits : 8 - 8 (1 bit)
access : read-write
RXPREDET : Preamble detected
bits : 9 - 9 (1 bit)
access : read-write
RXFRAMEDET0 : Frame with sync-word 0 detected
bits : 10 - 10 (1 bit)
access : read-write
RXFRAMEDET1 : Frame with sync-word 1 detected
bits : 11 - 11 (1 bit)
access : read-write
RXTIMLOST : Timing lost
bits : 12 - 12 (1 bit)
access : read-write
RXPRELOST : Preamble lost
bits : 13 - 13 (1 bit)
access : read-write
RXFRAMEDETOF : Frame detection overflow
bits : 14 - 14 (1 bit)
access : read-write
RXTIMNF : Timing not found
bits : 15 - 15 (1 bit)
access : read-write
FRCTIMOUT : DEMOD-FRC req/ack timeout
bits : 16 - 16 (1 bit)
access : read-write
ETS : Early Time Stamp detect
bits : 17 - 17 (1 bit)
access : read-write
CFGANTPATTRD : cfg
bits : 18 - 18 (1 bit)
access : read-write
RXRESTARTRSSIMAPRE : RX restart using RSSI MA filter
bits : 19 - 19 (1 bit)
access : read-write
RXRESTARTRSSIMASYNC : RX restart using RSSI MA filter
bits : 20 - 20 (1 bit)
access : read-write
SQDET : SQ Detect
bits : 21 - 21 (1 bit)
access : read-write
SQNOTDET : SQ Not Detect
bits : 22 - 22 (1 bit)
access : read-write
ANTDIVRDY : RSSI and CORR data Ready
bits : 23 - 23 (1 bit)
access : read-write
SOFTRESETDONE : Soft reset done
bits : 24 - 24 (1 bit)
access : read-write
SQPRENOTDET : SQ Not Detect
bits : 25 - 25 (1 bit)
access : read-write
SQFRAMENOTDET : SQ Not Detect
bits : 26 - 26 (1 bit)
access : read-write
SQAFCOUTOFBAND : SQ AFC out of band
bits : 27 - 27 (1 bit)
access : read-write
No Description
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMTHRESH : Timing threshold
bits : 0 - 7 (8 bit)
access : read-write
TIMINGBASES : Timing bases
bits : 8 - 11 (4 bit)
access : read-write
ADDTIMSEQ : Additional timing sequences
bits : 12 - 15 (4 bit)
access : read-write
TIMSEQINVEN : Timing sequence inversion enable
bits : 16 - 16 (1 bit)
access : read-write
TIMSEQSYNC : Timing sequence part of sync-word
bits : 17 - 17 (1 bit)
access : read-write
FDM0THRESH : Frame Detection Mode 0 threshold
bits : 18 - 20 (3 bit)
access : read-write
OFFSUBNUM : Offset subperiod numerator
bits : 21 - 24 (4 bit)
access : read-write
OFFSUBDEN : Offset subperiod denominator
bits : 25 - 28 (4 bit)
access : read-write
TSAGCDEL : Timing Search AGC delay
bits : 29 - 29 (1 bit)
access : read-write
FASTRESYNC : Fast timing resynchronization
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : DIS
Disabled.
1 : PREDET
Allow fast resynchronization until preamble is detected.
2 : FRAMEDET
Allow fast resynchronization until frame is detected.
End of enumeration elements list.
No Description
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSSS0 : DSSS symbol 0
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODINDEXM : Modulation index mantissa.
bits : 0 - 4 (5 bit)
access : read-write
MODINDEXE : Modulation index exponent.
bits : 5 - 9 (5 bit)
access : read-write
FREQGAINE : Frequency demodulation gain - exponent
bits : 16 - 18 (3 bit)
access : read-write
FREQGAINM : Frequency demodulation gain - mantissa
bits : 19 - 21 (3 bit)
access : read-write
No Description
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFCRXMODE : AFC RX mode
bits : 10 - 12 (3 bit)
access : read-write
Enumeration:
0 : DIS
Disabled.
1 : FREE
Free running. AFCADJRX constantly updated.
2 : FREEPRESTART
Free running. AFCADJRX not updated before preamble is detected.
3 : TIMLOCK
AFCADJRX locked when timing is detected.
4 : PRELOCK
AFCADJRX locked when preamble is detected.
5 : FRAMELOCK
AFCADJRX locked when frame is detected.
6 : FRAMELOCKPRESTART
AFCADJRX not updated before preamble is detected and locked when frame is detected.
End of enumeration elements list.
AFCTXMODE : AFC TX mode
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0 : DIS
Disabled.
1 : PRELOCK
AFCADJTX loaded from AFCADJRX when preamble is detected.
2 : FRAMELOCK
AFCADJTX loaded from AFCADJRX when frame is detected.
End of enumeration elements list.
AFCRXCLR : AFCRX clear mode
bits : 15 - 15 (1 bit)
access : read-write
AFCDEL : AFC delay
bits : 16 - 20 (5 bit)
access : read-write
AFCAVGPER : AFC average period
bits : 21 - 23 (3 bit)
access : read-write
AFCLIMRESET : Reset AFCADJRX value
bits : 24 - 24 (1 bit)
access : read-write
AFCONESHOT : AFC One-Shot feature
bits : 25 - 25 (1 bit)
access : read-write
AFCENINTCOMP : Internal frequency offset compensation
bits : 26 - 26 (1 bit)
access : read-write
AFCDSAFREQOFFEST : Consider frequency offset estimation
bits : 27 - 27 (1 bit)
access : read-write
AFCDELDET : Delay Detection state machine
bits : 28 - 28 (1 bit)
access : read-write
AFCGEAR : AFC Gear
bits : 29 - 30 (2 bit)
access : read-write
No Description
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFCADJLIM : AFC adjustment limit
bits : 0 - 17 (18 bit)
access : read-write
No Description
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF0 : Shaping Coefficient 0
bits : 0 - 7 (8 bit)
access : read-write
COEFF1 : Shaping Coefficient 1
bits : 8 - 15 (8 bit)
access : read-write
COEFF2 : Shaping Coefficient 2
bits : 16 - 23 (8 bit)
access : read-write
COEFF3 : Shaping Coefficient 3
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF4 : Shaping Coefficient 4
bits : 0 - 7 (8 bit)
access : read-write
COEFF5 : Shaping Coefficient 5
bits : 8 - 15 (8 bit)
access : read-write
COEFF6 : Shaping Coefficient 6
bits : 16 - 23 (8 bit)
access : read-write
COEFF7 : Shaping Coefficient 7
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF8 : Shaping Coefficient 8
bits : 0 - 7 (8 bit)
access : read-write
COEFF9 : Shaping Coefficient 9
bits : 8 - 15 (8 bit)
access : read-write
COEFF10 : Shaping Coefficient 10
bits : 16 - 23 (8 bit)
access : read-write
COEFF11 : Shaping Coefficient 11
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF12 : Shaping Coefficient 12
bits : 0 - 7 (8 bit)
access : read-write
COEFF13 : Shaping Coefficient 13
bits : 8 - 15 (8 bit)
access : read-write
COEFF14 : Shaping Coefficient 14
bits : 16 - 23 (8 bit)
access : read-write
COEFF15 : Shaping Coefficient 15
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF16 : Shaping Coefficient 16
bits : 0 - 7 (8 bit)
access : read-write
COEFF17 : Shaping Coefficient 17
bits : 8 - 15 (8 bit)
access : read-write
COEFF18 : Shaping Coefficient 18
bits : 16 - 23 (8 bit)
access : read-write
COEFF19 : Shaping Coefficient 19
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF20 : Shaping Coefficient 20
bits : 0 - 7 (8 bit)
access : read-write
COEFF21 : Shaping Coefficient 21
bits : 8 - 15 (8 bit)
access : read-write
COEFF22 : Shaping Coefficient 22
bits : 16 - 23 (8 bit)
access : read-write
COEFF23 : Shaping Coefficient 23
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF24 : Shaping Coefficient 24
bits : 0 - 7 (8 bit)
access : read-write
COEFF25 : Shaping Coefficient 25
bits : 8 - 15 (8 bit)
access : read-write
COEFF26 : Shaping Coefficient 26
bits : 16 - 23 (8 bit)
access : read-write
COEFF27 : Shaping Coefficient 27
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF28 : Shaping Coefficient 28
bits : 0 - 7 (8 bit)
access : read-write
COEFF29 : Shaping Coefficient 29
bits : 8 - 15 (8 bit)
access : read-write
COEFF30 : Shaping Coefficient 30
bits : 16 - 23 (8 bit)
access : read-write
COEFF31 : Shaping Coefficient 31
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF32 : Shaping Coefficient 32
bits : 0 - 7 (8 bit)
access : read-write
COEFF33 : Shaping Coefficient 33
bits : 8 - 15 (8 bit)
access : read-write
COEFF34 : Shaping Coefficient 34
bits : 16 - 23 (8 bit)
access : read-write
COEFF35 : Shaping Coefficient 35
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF36 : Shaping Coefficient 36
bits : 0 - 7 (8 bit)
access : read-write
COEFF37 : Shaping Coefficient 37
bits : 8 - 15 (8 bit)
access : read-write
COEFF38 : Shaping Coefficient 38
bits : 16 - 23 (8 bit)
access : read-write
COEFF39 : Shaping Coefficient 39
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF40 : Shaping Coefficient 40
bits : 0 - 7 (8 bit)
access : read-write
COEFF41 : Shaping Coefficient 41
bits : 8 - 15 (8 bit)
access : read-write
COEFF42 : Shaping Coefficient 42
bits : 16 - 23 (8 bit)
access : read-write
COEFF43 : Shaping Coefficient 43
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFRAMESENT : Frame sent
bits : 0 - 0 (1 bit)
access : read-write
TXSYNCSENT : Sync word sent
bits : 1 - 1 (1 bit)
access : read-write
TXPRESENT : Preamble sent
bits : 2 - 2 (1 bit)
access : read-write
TXRAMPDONE : Mod ramper idle
bits : 3 - 3 (1 bit)
access : read-write
LDTNOARR : No signal Detected in LDT
bits : 4 - 4 (1 bit)
access : read-write
PHDSADET : PHASE DSA DETECT
bits : 5 - 5 (1 bit)
access : read-write
PHYUNCODEDET : CONCURRENT UNCODED PHY DET
bits : 6 - 6 (1 bit)
access : read-write
PHYCODEDET : CONCURRENT CODED PHY DET
bits : 7 - 7 (1 bit)
access : read-write
RXTIMDET : Timing detected
bits : 8 - 8 (1 bit)
access : read-write
RXPREDET : Preamble detected
bits : 9 - 9 (1 bit)
access : read-write
RXFRAMEDET0 : Frame with sync-word 0 detected
bits : 10 - 10 (1 bit)
access : read-write
RXFRAMEDET1 : Frame with sync-word 1 detected
bits : 11 - 11 (1 bit)
access : read-write
RXTIMLOST : Timing lost
bits : 12 - 12 (1 bit)
access : read-write
RXPRELOST : Preamble lost
bits : 13 - 13 (1 bit)
access : read-write
RXFRAMEDETOF : Frame detection overflow
bits : 14 - 14 (1 bit)
access : read-write
RXTIMNF : Timing not found
bits : 15 - 15 (1 bit)
access : read-write
FRCTIMOUT : DEMOD-FRC req/ack timeout
bits : 16 - 16 (1 bit)
access : read-write
ETS : Early Time Stamp detect
bits : 17 - 17 (1 bit)
access : read-write
CFGANTPATTRD : CFGANTPATTRD
bits : 18 - 18 (1 bit)
access : read-write
RXRESTARTRSSIMAPRE : RX restart using RSSI MA filter
bits : 19 - 19 (1 bit)
access : read-write
RXRESTARTRSSIMASYNC : RX restart using RSSI MA filter
bits : 20 - 20 (1 bit)
access : read-write
SQDET : SQ Detected
bits : 21 - 21 (1 bit)
access : read-write
SQNOTDET : SQ Not Detected
bits : 22 - 22 (1 bit)
access : read-write
ANTDIVRDY : RSSI and CORR data Ready
bits : 23 - 23 (1 bit)
access : read-write
SOFTRESETDONE : Soft reset done
bits : 24 - 24 (1 bit)
access : read-write
SQPRENOTDET : SQ Not Detected
bits : 25 - 25 (1 bit)
access : read-write
SQFRAMENOTDET : SQ Not Detected
bits : 26 - 26 (1 bit)
access : read-write
SQAFCOUTOFBAND : SQ afc out of band
bits : 27 - 27 (1 bit)
access : read-write
No Description
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF44 : Shaping Coefficient 44
bits : 0 - 7 (8 bit)
access : read-write
COEFF45 : Shaping Coefficient 45
bits : 8 - 15 (8 bit)
access : read-write
COEFF46 : Shaping Coefficient 46
bits : 16 - 23 (8 bit)
access : read-write
COEFF47 : Shaping Coefficient 47
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF48 : Shaping Coefficient 48
bits : 0 - 7 (8 bit)
access : read-write
COEFF49 : Shaping Coefficient 49
bits : 8 - 15 (8 bit)
access : read-write
COEFF50 : Shaping Coefficient 50
bits : 16 - 23 (8 bit)
access : read-write
COEFF51 : Shaping Coefficient 51
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF52 : Shaping Coefficient 52
bits : 0 - 7 (8 bit)
access : read-write
COEFF53 : Shaping Coefficient 53
bits : 8 - 15 (8 bit)
access : read-write
COEFF54 : Shaping Coefficient 54
bits : 16 - 23 (8 bit)
access : read-write
COEFF55 : Shaping Coefficient 55
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF56 : Shaping Coefficient 56
bits : 0 - 7 (8 bit)
access : read-write
COEFF57 : Shaping Coefficient 57
bits : 8 - 15 (8 bit)
access : read-write
COEFF58 : Shaping Coefficient 58
bits : 16 - 23 (8 bit)
access : read-write
COEFF59 : Shaping Coefficient 59
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF60 : Shaping Coefficient 60
bits : 0 - 7 (8 bit)
access : read-write
COEFF61 : Shaping Coefficient 61
bits : 8 - 15 (8 bit)
access : read-write
COEFF62 : Shaping Coefficient 62
bits : 16 - 23 (8 bit)
access : read-write
COEFF63 : Shaping Coefficient 63
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OOKSHAPINGEN : OOK/ASK PA Shaping Enable
bits : 0 - 0 (1 bit)
access : read-write
OOKSHAPINGSTEP : OOK/ASK PA Shaping Steps
bits : 1 - 9 (9 bit)
access : read-write
OOKSHAPINGRATE : OOK/ASK PA Shaping Rate
bits : 10 - 12 (3 bit)
access : read-write
OOKSHAPINGLUTSIZE : OOK/ASK Shaping LUT size
bits : 13 - 18 (6 bit)
access : read-write
No Description
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMPRATE0 : Ramp rate 0
bits : 0 - 3 (4 bit)
access : read-write
RAMPRATE1 : Ramp rate 1
bits : 4 - 7 (4 bit)
access : read-write
RAMPRATE2 : Ramp rate 2
bits : 8 - 11 (4 bit)
access : read-write
No Description
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMPLEV0 : Ramp level 0
bits : 0 - 7 (8 bit)
access : read-write
RAMPLEV1 : Ramp level 1
bits : 8 - 15 (8 bit)
access : read-write
RAMPLEV2 : Ramp level 2
bits : 16 - 23 (8 bit)
access : read-write
No Description
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANARAMPEN : PA Analog Ramp Enable
bits : 0 - 0 (1 bit)
access : read-write
RAMPOVREN : PA Analog Ramp Override
bits : 1 - 1 (1 bit)
access : read-write
RAMPOVRUPD : PA Analog Ramp Override Update Pulse
bits : 2 - 2 (1 bit)
access : write-only
ANARAMPLUTODEV : Analog Ramp LUT ODEV switch over
bits : 3 - 8 (6 bit)
access : read-write
VMIDCTRL : PA Analog Ramp VMID control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
0 : OFF
en_xdrv_vmid always off
1 : MID
en_xdrv_vmid ramp_drv threshold set to midscale
2 : HIGH
en_xdrv_vmid ramp_drv threshold set to highest level
3 : ON
en_xdrv_vmid always on
End of enumeration elements list.
MUTEDLY : PA Analog Ramp mute delay
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : TIME0US
Mute to ramp drv/odev delay set to 0us
1 : TIME0P5US
Mute to ramp drv/odev delay set to 0.5us
2 : TIME0P25US
Mute to ramp drv/odev delay set to 0.25us
3 : NOTUSED
Unused Mute to ramp drv/odev delay value
End of enumeration elements list.
No Description
address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANARAMPLUT0 : Analog Ramp LUT
bits : 0 - 4 (5 bit)
access : read-write
ANARAMPLUT1 : Analog Ramp LUT
bits : 5 - 9 (5 bit)
access : read-write
ANARAMPLUT2 : Analog Ramp LUT
bits : 10 - 14 (5 bit)
access : read-write
ANARAMPLUT3 : Analog Ramp LUT
bits : 15 - 19 (5 bit)
access : read-write
ANARAMPLUT4 : Analog Ramp LUT
bits : 20 - 24 (5 bit)
access : read-write
ANARAMPLUT5 : Analog Ramp LUT
bits : 25 - 29 (5 bit)
access : read-write
No Description
address_offset : 0xE8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANARAMPLUT6 : Analog Ramp LUT
bits : 0 - 4 (5 bit)
access : read-write
ANARAMPLUT7 : Analog Ramp LUT
bits : 5 - 9 (5 bit)
access : read-write
ANARAMPLUT8 : Analog Ramp LUT
bits : 10 - 14 (5 bit)
access : read-write
ANARAMPLUT9 : Analog Ramp LUT
bits : 15 - 19 (5 bit)
access : read-write
ANARAMPLUT10 : Analog Ramp LUT
bits : 20 - 24 (5 bit)
access : read-write
ANARAMPLUT11 : Analog Ramp LUT
bits : 25 - 29 (5 bit)
access : read-write
No Description
address_offset : 0xEC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANARAMPLUT12 : Analog Ramp LUT
bits : 0 - 4 (5 bit)
access : read-write
ANARAMPLUT13 : Analog Ramp LUT
bits : 5 - 9 (5 bit)
access : read-write
ANARAMPLUT14 : Analog Ramp LUT
bits : 10 - 14 (5 bit)
access : read-write
ANARAMPLUT15 : Analog Ramp LUT
bits : 15 - 19 (5 bit)
access : read-write
ANARAMPLUT16 : Analog Ramp LUT
bits : 20 - 24 (5 bit)
access : read-write
ANARAMPLUT17 : Analog Ramp LUT
bits : 25 - 29 (5 bit)
access : read-write
No Description
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANARAMPLUT18 : Analog Ramp LUT
bits : 0 - 4 (5 bit)
access : read-write
ANARAMPLUT19 : Analog Ramp LUT
bits : 5 - 9 (5 bit)
access : read-write
ANARAMPLUT20 : Analog Ramp LUT
bits : 10 - 14 (5 bit)
access : read-write
ANARAMPLUT21 : Analog Ramp LUT
bits : 15 - 19 (5 bit)
access : read-write
ANARAMPLUT22 : Analog Ramp LUT
bits : 20 - 24 (5 bit)
access : read-write
ANARAMPLUT23 : Analog Ramp LUT
bits : 25 - 29 (5 bit)
access : read-write
No Description
address_offset : 0xF4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANARAMPLUT24 : Analog Ramp LUT
bits : 0 - 4 (5 bit)
access : read-write
ANARAMPLUT25 : Analog Ramp LUT
bits : 5 - 9 (5 bit)
access : read-write
ANARAMPLUT26 : Analog Ramp LUT
bits : 10 - 14 (5 bit)
access : read-write
ANARAMPLUT27 : Analog Ramp LUT
bits : 15 - 19 (5 bit)
access : read-write
ANARAMPLUT28 : Analog Ramp LUT
bits : 20 - 24 (5 bit)
access : read-write
ANARAMPLUT29 : Analog Ramp LUT
bits : 25 - 29 (5 bit)
access : read-write
No Description
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANARAMPLUT30 : Analog Ramp LUT
bits : 0 - 4 (5 bit)
access : read-write
ANARAMPLUT31 : Analog Ramp LUT
bits : 5 - 9 (5 bit)
access : read-write
ANARAMPLUT32 : Analog Ramp LUT
bits : 10 - 14 (5 bit)
access : read-write
ANARAMPLUT33 : Analog Ramp LUT
bits : 15 - 19 (5 bit)
access : read-write
ANARAMPLUT34 : Analog Ramp LUT
bits : 20 - 24 (5 bit)
access : read-write
ANARAMPLUT35 : Analog Ramp LUT
bits : 25 - 29 (5 bit)
access : read-write
No Description
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANARAMPLUT36 : Analog Ramp LUT
bits : 0 - 4 (5 bit)
access : read-write
ANARAMPLUT37 : Analog Ramp LUT
bits : 5 - 9 (5 bit)
access : read-write
ANARAMPLUT38 : Analog Ramp LUT
bits : 10 - 14 (5 bit)
access : read-write
ANARAMPLUT39 : Analog Ramp LUT
bits : 15 - 19 (5 bit)
access : read-write
ANARAMPLUT40 : Analog Ramp LUT
bits : 20 - 24 (5 bit)
access : read-write
ANARAMPLUT41 : Analog Ramp LUT
bits : 25 - 29 (5 bit)
access : read-write
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