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address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
Read to get the hard-wired chip revision.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAJOR : Hardwired Chip Revision Major value
bits : 0 - 5 (6 bit)
access : read-write
FAMILY : Hardwired Chip Family value
bits : 6 - 11 (6 bit)
access : read-write
MINOR : Hardwired Chip Revision Minor value
bits : 12 - 19 (8 bit)
access : read-write
Read to get the chip revision programmed by feature configuration.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAJOR : Chip Revision Major value
bits : 0 - 5 (6 bit)
access : read-write
FAMILY : Chip Family value
bits : 6 - 11 (6 bit)
access : read-write
MINOR : Chip Revision Minor value
bits : 12 - 19 (8 bit)
access : read-write
Configure to provide general RAM configuration.
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRFAULTEN : Invalid Address Bus Fault Response Enabl
bits : 0 - 0 (1 bit)
access : read-write
CLKDISFAULTEN : Disabled Clkbus Bus Fault Enable
bits : 1 - 1 (1 bit)
access : read-write
RAMECCERRFAULTEN : Two bit ECC error bus fault response ena
bits : 5 - 5 (1 bit)
access : read-write
Configure to provide general RAM retention configuration.
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMRETNCTRL : DMEM0 blockset retention control
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALLON
None of the RAM blocks powered down
4 : BLK3
Power down RAM block 3 (address range 0x2000C000-0x20010000)
6 : BLK2TO3
Power down RAM blocks 3 and above (address range 0x20008000-0x20010000)
7 : BLK1TO3
Power down RAM blocks 1 and above (address range 0x20004000-0x20010000)
End of enumeration elements list.
Configure the source of the system tick for the M33.
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSTICEXTCLKEN : SysTick External Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Configure RAM bias configure bits.
address_offset : 0x30C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMBIASCTRL : RAM Bias Control
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : No
None
1 : VSB100
Voltage Source Bias 100mV
2 : VSB200
Voltage Source Bias 200mV
4 : VSB300
Voltage Source Bias 300mV
8 : VSB400
Voltage Source Bias 400mV
End of enumeration elements list.
No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : New BitField
bits : 0 - 31 (32 bit)
access : read-only
Configure SEQRAM Retention controls.
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQRAMRETNCTRL : SEQRAM Retention Control
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ALLON
SEQRAM not powered down
1 : BLK0
Power down SEQRAM block 0
2 : BLK1
Power down SEQRAM block 1
3 : ALLOFF
Power down all SEQRAM blocks
End of enumeration elements list.
FRCRAMRETNCTRL : FRCRAM Retention Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : ALLON
FRCRAM not powered down
1 : ALLOFF
Power down FRCRAM
End of enumeration elements list.
Configure to set RAM ECC control.
address_offset : 0x408 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQRAMECCEN : SEQRAM ECC Enable
bits : 0 - 0 (1 bit)
access : read-write
SEQRAMECCEWEN : SEQRAM ECC Error Writeback Enable
bits : 1 - 1 (1 bit)
access : read-write
FRCRAMECCEN : FRCRAM ECC Enable
bits : 8 - 8 (1 bit)
access : read-write
FRCRAMECCEWEN : FRCRAM ECC Error Writeback Enable
bits : 9 - 9 (1 bit)
access : read-write
Read to get status of the SEQRAM ECC error address.
address_offset : 0x410 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEQRAMECCADDR : SEQRAM ECC Address
bits : 0 - 31 (32 bit)
access : read-only
Read to get status of the FRCRAM ECC error address.
address_offset : 0x414 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCRAMECCADDR : FRCRAM ECC Error Address
bits : 0 - 31 (32 bit)
access : read-only
Configure Host ICACHERAM retention configuration.
address_offset : 0x418 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMRETNCTRL : ICACHERAM Retention control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ALLON
None of the Host ICACHE RAM blocks powered down
1 : ALLOFF
Power down all Host ICACHE RAM blocks
End of enumeration elements list.
Configure DMEM0 port remap selection.
address_offset : 0x41C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDMAPORTSEL : LDMA portmap selection
bits : 0 - 0 (1 bit)
access : read-write
SRWAESPORTSEL : SRWAES portmap selection
bits : 1 - 1 (1 bit)
access : read-write
AHBSRWPORTSEL : AHBSRW portmap selection
bits : 2 - 2 (1 bit)
access : read-write
SRWECA0PORTSEL : SRWECA0 portmap selection
bits : 3 - 3 (1 bit)
access : read-write
SRWECA1PORTSEL : SRWECA1 portmap selection
bits : 4 - 4 (1 bit)
access : read-write
Generic data space for user to pass to root, e.g., address of struct in mem
address_offset : 0x600 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 31 (32 bit)
access : read-write
Generic data space for user to pass to root, e.g., address of struct in mem
address_offset : 0x604 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 31 (32 bit)
access : read-write
This register returns the status of the SE managed locks.
address_offset : 0x608 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSLOCK : Bus Lock
bits : 0 - 0 (1 bit)
access : read-only
REGLOCK : Register Lock
bits : 1 - 1 (1 bit)
access : read-only
MFRLOCK : Manufacture Lock
bits : 2 - 2 (1 bit)
access : read-only
ROOTDBGLOCK : Root Debug Lock
bits : 8 - 8 (1 bit)
access : read-only
USERDBGAPLOCK : User Debug Access Port Lock
bits : 16 - 16 (1 bit)
access : read-only
USERDBGLOCK : User Invasive Debug Lock
bits : 17 - 17 (1 bit)
access : read-only
USERNIDLOCK : User Non-invasive Debug Lock
bits : 18 - 18 (1 bit)
access : read-only
USERSPIDLOCK : User Secure Invasive Debug Lock
bits : 19 - 19 (1 bit)
access : read-only
USERSPNIDLOCK : User Secure Non-invasive Debug Lock
bits : 20 - 20 (1 bit)
access : read-only
RADIOIDBGLOCK : Radio Invasive Debug Lock
bits : 21 - 21 (1 bit)
access : read-only
RADIONIDBGLOCK : Radio Non-invasive Debug Lock
bits : 22 - 22 (1 bit)
access : read-only
EFUSEUNLOCKED : E-Fuse Unlocked
bits : 31 - 31 (1 bit)
access : read-only
SE Software version
address_offset : 0x60C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWVERSION : SW Version
bits : 0 - 31 (32 bit)
access : read-write
Read to get system status.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW0 : Software Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
SW1 : Software Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write
SW2 : Software Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write
SW3 : Software Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write
FPIOC : FPU Invalid Operation interrupt flag
bits : 8 - 8 (1 bit)
access : read-write
FPDZC : FPU Divide by zero interrupt flag
bits : 9 - 9 (1 bit)
access : read-write
FPUFC : FPU Underflow interrupt flag
bits : 10 - 10 (1 bit)
access : read-write
FPOFC : FPU Overflow interrupt flag
bits : 11 - 11 (1 bit)
access : read-write
FPIDC : FPU Input denormal interrupt flag
bits : 12 - 12 (1 bit)
access : read-write
FPIXC : FPU Inexact interrupt flag
bits : 13 - 13 (1 bit)
access : read-write
SEQRAMERR1B : SEQRAM Error 1-bit Interrupt Flag
bits : 24 - 24 (1 bit)
access : read-write
SEQRAMERR2B : SEQRAM Error 2-bit Interrupt Flag
bits : 25 - 25 (1 bit)
access : read-write
FRCRAMERR1B : FRCRAM Error 1-bit Interrupt Flag
bits : 28 - 28 (1 bit)
access : read-write
FRCRAMERR2B : FRCRAM Error 2-bit Interrupt Flag
bits : 29 - 29 (1 bit)
access : read-write
Write to enable interrupts.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW0 : Software Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
SW1 : Software Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
SW2 : Software Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
SW3 : Software Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
FPIOC : FPU Invalid Operation Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
FPDZC : FPU Divide by zero Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
FPUFC : FPU Underflow Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
FPOFC : FPU Overflow Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
FPIDC : FPU Input denormal Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
FPIXC : FPU Inexact Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
SEQRAMERR1B : SEQRAM Error 1-bit Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write
SEQRAMERR2B : SEQRAM Error 2-bit Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-write
FRCRAMERR1B : FRCRAM Error 1-bit Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-write
FRCRAMERR2B : FRCRAM Error 2-bit Interrupt Enable
bits : 29 - 29 (1 bit)
access : read-write
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