\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP Version ID
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ERASEPAGE : Erase Page
bits : 1 - 1 (1 bit)
access : write-only
WRITEEND : End Write Mode
bits : 2 - 2 (1 bit)
access : write-only
ERASERANGE : Erase range of pages
bits : 4 - 4 (1 bit)
access : write-only
ERASEABORT : Abort erase sequence
bits : 5 - 5 (1 bit)
access : write-only
ERASEMAIN0 : Mass erase region 0
bits : 8 - 8 (1 bit)
access : write-only
CLEARWDATA : Clear WDATA state
bits : 12 - 12 (1 bit)
access : write-only
No Description
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKBIT : page lock bit
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKBIT : page lock bit
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKBIT : page lock bit
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x12C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKBIT : page lock bit
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKBIT : page lock bit
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x134 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKBIT : page lock bit
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRB : Page Erase or Write Address Buffer
bits : 0 - 31 (32 bit)
access : read-write
This is SE read/write only register. Hostwill read back zero.
address_offset : 0x140 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REPINVALID : Repair Addr Invalid Flag
bits : 0 - 0 (1 bit)
access : read-write
REPADDR : Repair Page Address
bits : 1 - 15 (15 bit)
access : read-write
This is SE read/write only register. Hostwill read back zero.
address_offset : 0x144 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REPINVALID : Repair Addr Invalid Flag
bits : 0 - 0 (1 bit)
access : read-write
REPADDR : Repair Page Address
bits : 1 - 15 (15 bit)
access : read-write
No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAW : Write Data
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : Erase/Write Busy
bits : 0 - 0 (1 bit)
access : read-only
LOCKED : Access Locked
bits : 1 - 1 (1 bit)
access : read-only
INVADDR : Invalid Write Address or Erase Page
bits : 2 - 2 (1 bit)
access : read-only
WDATAREADY : WDATA Write Ready
bits : 3 - 3 (1 bit)
access : read-only
ERASEABORTED : The Current Flash Erase Operation Aborte
bits : 4 - 4 (1 bit)
access : read-only
PENDING : Write command is in queue
bits : 5 - 5 (1 bit)
access : read-only
TIMEOUT : Write command timeout flag
bits : 6 - 6 (1 bit)
access : read-only
RANGEPARTIAL : EraseRange with skipped locked pages
bits : 7 - 7 (1 bit)
access : read-only
REGLOCK : Register Lock Status
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : UNLOCKED
1 : LOCKED
End of enumeration elements list.
PWRON : Flash power on status
bits : 24 - 24 (1 bit)
access : read-only
WREADY : Flash Write Ready
bits : 27 - 27 (1 bit)
access : read-only
PWRUPCKBDFAILCOUNT : Flash power up checkerboard pattern chec
bits : 28 - 31 (4 bit)
access : read-only
Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x1C4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RATDMSCREADCTRL : READCTRL Protection Bit
bits : 1 - 1 (1 bit)
access : read-write
RATDMSCRDATACTRL : RDATACTRL Protection Bit
bits : 2 - 2 (1 bit)
access : read-write
RATDMSCWRITECTRL : WRITECTRL Protection Bit
bits : 3 - 3 (1 bit)
access : read-write
RATDMSCWRITECMD : WRITECMD Protection Bit
bits : 4 - 4 (1 bit)
access : read-write
RATDMSCADDRB : ADDRB Protection Bit
bits : 5 - 5 (1 bit)
access : read-write
RATDMSCWDATA : WDATA Protection Bit
bits : 6 - 6 (1 bit)
access : read-write
RATDMSCIF : IF Protection Bit
bits : 8 - 8 (1 bit)
access : read-write
RATDMSCIEN : IEN Protection Bit
bits : 9 - 9 (1 bit)
access : read-write
RATDMSCCMD : CMD Protection Bit
bits : 14 - 14 (1 bit)
access : read-write
RATDMSCLOCK : LOCK Protection Bit
bits : 15 - 15 (1 bit)
access : read-write
RATDMSCMISCLOCKWORD : MISCLOCKWORD Protection Bit
bits : 16 - 16 (1 bit)
access : read-write
RATDMSCPWRCTRL : PWRCTRL Protection Bit
bits : 20 - 20 (1 bit)
access : read-write
Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x1C8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RATDMSCSEWRITECTRL : SEWRITECTRL Protection Bit
bits : 0 - 0 (1 bit)
access : read-write
RATDMSCSEWRITECMD : SEWRITECMD Protection Bit
bits : 1 - 1 (1 bit)
access : read-write
RATDMSCSEADDRB : SEADDRB Protection Bit
bits : 2 - 2 (1 bit)
access : read-write
RATDMSCSEWDATA : SEWDATA Protection Bit
bits : 3 - 3 (1 bit)
access : read-write
RATDMSCSEIF : SEIF Protection Bit
bits : 5 - 5 (1 bit)
access : read-write
RATDMSCSEIEN : SEIEN Protection Bit
bits : 6 - 6 (1 bit)
access : read-write
RATDMSCMEMFEATURE : MEMFEATURE Protection Bit
bits : 7 - 7 (1 bit)
access : read-write
RATDMSCSTARTUP : STARTUP Protection Bit
bits : 8 - 8 (1 bit)
access : read-write
RATDMSCSERDATACTRL : SERDATACTRL Protection Bit
bits : 9 - 9 (1 bit)
access : read-write
RATDMSCSEPWRSKIP : SEPWRSKIP Protection Bit
bits : 10 - 10 (1 bit)
access : read-write
RATDMSCMTPCTRL : MTPCTRL Protection Bit
bits : 11 - 11 (1 bit)
access : read-write
RATDMSCMTPSIZE : MTPSIZE Protection Bit
bits : 12 - 12 (1 bit)
access : read-write
RATDMSCOTPERASE : OTPERASE Protection Bit
bits : 13 - 13 (1 bit)
access : read-write
RATDMSCFLASHERASETIME : FLASHERASETIME Protection Bit
bits : 16 - 16 (1 bit)
access : read-write
RATDMSCFLASHPROGTIME : FLASHPROGTIME Protection Bit
bits : 17 - 17 (1 bit)
access : read-write
RATDMSCSELOCK : SELOCK Protection Bit
bits : 18 - 18 (1 bit)
access : read-write
Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x1CC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RATDINSTPAGELOCKWORD0 : PAGELOCKWORD0 Protection Bit
bits : 8 - 8 (1 bit)
access : read-write
RATDINSTPAGELOCKWORD1 : PAGELOCKWORD1 Protection Bit
bits : 9 - 9 (1 bit)
access : read-write
RATDINSTPAGELOCKWORD2 : PAGELOCKWORD2 Protection Bit
bits : 10 - 10 (1 bit)
access : read-write
RATDINSTPAGELOCKWORD3 : PAGELOCKWORD3 Protection Bit
bits : 11 - 11 (1 bit)
access : read-write
RATDINSTPAGELOCKWORD4 : PAGELOCKWORD4 Protection Bit
bits : 12 - 12 (1 bit)
access : read-write
RATDINSTPAGELOCKWORD5 : PAGELOCKWORD5 Protection Bit
bits : 13 - 13 (1 bit)
access : read-write
RATDINSTREPADDR0 : REPADDR0 Protection Bit
bits : 16 - 16 (1 bit)
access : read-write
RATDINSTREPADDR1 : REPADDR1 Protection Bit
bits : 17 - 17 (1 bit)
access : read-write
Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x1D0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RATDMSCTESTCTRL : TESTCTRL Protection Bit
bits : 8 - 8 (1 bit)
access : read-write
RATDMSCPATDIAGCTRL : PATDIAGCTRL Protection Bit
bits : 9 - 9 (1 bit)
access : read-write
RATDMSCPATDONEADDR : PATDONEADDR Protection Bit
bits : 11 - 11 (1 bit)
access : read-write
RATDMSCTESTREDUNDANCY : TESTREDUNDANCY Protection Bit
bits : 15 - 15 (1 bit)
access : read-write
RATDMSCTESTLOCK : TESTLOCK Protection Bit
bits : 16 - 16 (1 bit)
access : read-write
No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERASE : Host Erase Done Interrupt Read Flag
bits : 0 - 0 (1 bit)
access : read-write
WRITE : Host Write Done Interrupt Read Flag
bits : 1 - 1 (1 bit)
access : read-write
WDATAOV : Host write buffer overflow
bits : 2 - 2 (1 bit)
access : read-write
PWRUPF : Flash Power Up Sequence Complete Flag
bits : 8 - 8 (1 bit)
access : read-write
PWROFF : Flash Power Off Sequence Complete Flag
bits : 9 - 9 (1 bit)
access : read-write
No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERASE : Erase Done Interrupt enable
bits : 0 - 0 (1 bit)
access : read-write
WRITE : Write Done Interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
WDATAOV : write data buffer overflow irq enable
bits : 2 - 2 (1 bit)
access : read-write
PWRUPF : Flash Power Up Seq done irq enable
bits : 8 - 8 (1 bit)
access : read-write
PWROFF : Flash Power Off Seq done irq enable
bits : 9 - 9 (1 bit)
access : read-write
No Description
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USERDATASIZE : User Data Size
bits : 0 - 5 (6 bit)
access : read-only
No Description
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PWRUP : Flash Power Up Command
bits : 0 - 0 (1 bit)
access : write-only
PWROFF : Flash power off/sleep command
bits : 4 - 4 (1 bit)
access : write-only
No Description
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LOCKKEY : Configuration Lock
bits : 0 - 15 (16 bit)
access : write-only
Enumeration:
0 : LOCK
7025 : UNLOCK
End of enumeration elements list.
No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Read Mode
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : WS0
Zero wait-states inserted in fetch or read transfers
1 : WS1
One wait-state inserted for each fetch or read transfer. See Flash Wait-States table for details
2 : WS2
Two wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details
3 : WS3
Three wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details
End of enumeration elements list.
No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MELOCKBIT : Mass Erase Lock
bits : 0 - 0 (1 bit)
access : read-write
UDLOCKBIT : User Data Lock
bits : 4 - 4 (1 bit)
access : read-write
No Description
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWROFFONEM1ENTRY : Power down Flash macro when enter EM1
bits : 0 - 0 (1 bit)
access : read-write
PWROFFONEM1PENTRY : Power down Flash macro when enter EM1P
bits : 1 - 1 (1 bit)
access : read-write
PWROFFENTRYAGAIN : POWER down flash again in EM1/EM1p
bits : 4 - 4 (1 bit)
access : read-write
PWROFFDLY : Power down delay
bits : 16 - 23 (8 bit)
access : read-write
No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFDIS : Automatic Invalidate Disable
bits : 1 - 1 (1 bit)
access : read-write
DOUTBUFEN : Flash dout pipeline buffer enable
bits : 12 - 12 (1 bit)
access : read-write
This is SE read/write only register. Host will read back zero.
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WREN : Enable Write/Erase Controller
bits : 0 - 0 (1 bit)
access : read-write
IRQERASEABORT : Abort Page Erase on Interrupt
bits : 1 - 1 (1 bit)
access : read-write
LPWRITE : Low-Power Erase
bits : 3 - 3 (1 bit)
access : read-write
RANGECOUNT : ErageRange Count
bits : 16 - 25 (10 bit)
access : read-write
This is SE read/write only register. Host will read back zero.
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ERASEPAGE : Erase Page
bits : 1 - 1 (1 bit)
access : write-only
WRITEEND : End Write Mode
bits : 2 - 2 (1 bit)
access : write-only
ERASERANGE : Erase range of pages
bits : 4 - 4 (1 bit)
access : write-only
ERASEABORT : Abort erase sequence
bits : 5 - 5 (1 bit)
access : write-only
ERASEMAIN0 : Mass erase user area
bits : 8 - 8 (1 bit)
access : write-only
ERASEMAIN1 : Mass erase non-user area
bits : 9 - 9 (1 bit)
access : write-only
ERASEMAINA : Mass erase all main
bits : 10 - 10 (1 bit)
access : write-only
CLEARWDATA : Clear WDATA state
bits : 12 - 12 (1 bit)
access : write-only
This is SE read/write only register. Host will read back zero.
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRB : Page Erase or Write Address Buffer
bits : 0 - 31 (32 bit)
access : read-write
This is SE read/write only register. Host will read back zero.
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAW : Write Data
bits : 0 - 31 (32 bit)
access : read-write
This is SE read/write only register. Host will read back zero.
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : Erase/Write Busy
bits : 0 - 0 (1 bit)
access : read-only
LOCKED : Access Locked
bits : 1 - 1 (1 bit)
access : read-only
INVADDR : Invalid Write Address or Erase Page
bits : 2 - 2 (1 bit)
access : read-only
WDATAREADY : WDATA Write Ready
bits : 3 - 3 (1 bit)
access : read-only
ERASEABORTED : The Current Flash Erase Operation Aborte
bits : 4 - 4 (1 bit)
access : read-only
PENDING : Write command is in queue
bits : 5 - 5 (1 bit)
access : read-only
TIMEOUT : Write command timeout flag
bits : 6 - 6 (1 bit)
access : read-only
RANGEPARTIAL : EraseRange with skipped locked pages
bits : 7 - 7 (1 bit)
access : read-only
ROOTLOCK : Register Lock Status
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : UNLOCKED
1 : LOCKED
End of enumeration elements list.
PWRCKDONE : Flash power up CKBD done flag
bits : 30 - 30 (1 bit)
access : read-only
PWRCKSKIPSTATUS : Flash power up CKBD skip status
bits : 31 - 31 (1 bit)
access : read-only
This is SE read/write only register. Host will read back zero.
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERASEIF : SE Erase Done Interrupt Read Flag
bits : 0 - 0 (1 bit)
access : read-write
WRITEIF : SE Write Done Interrupt Read Flag
bits : 1 - 1 (1 bit)
access : read-write
WDATAOVIF : SE write buffer overflow
bits : 2 - 2 (1 bit)
access : read-write
This is SE read/write only register. Host will read back zero.
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERASEIEN : Erase Done Interrupt enable
bits : 0 - 0 (1 bit)
access : read-write
WRITEIEN : Write Done Interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
WDATAOVIEN : write data buffer overflow irq enable
bits : 2 - 2 (1 bit)
access : read-write
This is SE read/write only register. Host will read back zero.
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STDLY0 : Startup Delay 0
bits : 0 - 9 (10 bit)
access : read-write
STDLY1 : Startup Delay 0
bits : 12 - 21 (10 bit)
access : read-write
ASTWAIT : Active Startup Wait
bits : 24 - 24 (1 bit)
access : read-write
STWSEN : Startup Waitstates Enable
bits : 25 - 25 (1 bit)
access : read-write
STWSAEN : Startup Waitstates Always Enable
bits : 26 - 26 (1 bit)
access : read-write
STWS : Startup Waitstates
bits : 28 - 30 (3 bit)
access : read-write
This is SE read/write only register. Host will read back zero.
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEDOUTBUFEN : Flash dout pipeline buffer enable
bits : 12 - 12 (1 bit)
access : read-write
No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WREN : Enable Write/Erase Controller
bits : 0 - 0 (1 bit)
access : read-write
IRQERASEABORT : Abort Page Erase on Interrupt
bits : 1 - 1 (1 bit)
access : read-write
LPWRITE : Low-Power Erase
bits : 3 - 3 (1 bit)
access : read-write
RANGECOUNT : ErageRange Count
bits : 16 - 25 (10 bit)
access : read-write
This is SE read/write only register. Host will read back zero.
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERASE : Erase Counter
bits : 0 - 14 (15 bit)
access : read-write
TME : Mass Erase Counter
bits : 16 - 30 (15 bit)
access : read-write
This is SE read/write only register. Host will read back zero.
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPROG : Prog Counter
bits : 0 - 3 (4 bit)
access : read-write
TXLPW : Prog Counter
bits : 4 - 7 (4 bit)
access : read-write
TIMEBASE : 1 us time base counter on emuosc
bits : 8 - 12 (5 bit)
access : read-write
THV : Cumulative Program HV Counter
bits : 16 - 30 (15 bit)
access : read-write
This is SE read/write only register. Host will read back zero.
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SELOCKKEY : Configuration Lock
bits : 0 - 15 (16 bit)
access : write-only
Enumeration:
0 : LOCK
41950 : UNLOCK
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.