\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IPVERSION
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SYNCSWSET : DMA SYNC Software Trigger Set
bits : 0 - 7 (8 bit)
access : write-only
No Description
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.
1 : RELATIVE
The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor.
End of enumeration elements list.
LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write
LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write
No Description
address_offset : 0x11C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ONE
One arbitration slot selected
1 : TWO
Two arbitration slots selected
2 : FOUR
Four arbitration slots selected
3 : EIGHT
Eight arbitration slots selected
End of enumeration elements list.
SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : POSITIVE
Increment source address
1 : NEGATIVE
Decrement source address
End of enumeration elements list.
DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : POSITIVE
Increment destination address
1 : NEGATIVE
Decrement destination address
End of enumeration elements list.
No Description
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TRANSFER
DMA transfer structure type selected.
1 : SYNCHRONIZE
Synchronization structure type selected.
2 : WRITE
Write immediate value structure type selected.
End of enumeration elements list.
STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : read-only
XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write
BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write
BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : UNIT1
One unit transfer per arbitration
1 : UNIT2
Two unit transfers per arbitration
2 : UNIT3
Three unit transfers per arbitration
3 : UNIT4
Four unit transfers per arbitration
4 : UNIT6
Six unit transfers per arbitration
5 : UNIT8
Eight unit transfers per arbitration
7 : UNIT16
Sixteen unit transfers per arbitration
9 : UNIT32
32 unit transfers per arbitration
10 : UNIT64
64 unit transfers per arbitration
11 : UNIT128
128 unit transfers per arbitration
12 : UNIT256
256 unit transfers per arbitration
13 : UNIT512
512 unit transfers per arbitration
14 : UNIT1024
1024 unit transfers per arbitration
15 : ALL
Transfer all units as specified by the XFRCNT field
End of enumeration elements list.
DONEIEN : DMA Operation Done Interrupt Flag Set En
bits : 20 - 20 (1 bit)
access : read-write
REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : BLOCK
The LDMA transfers one BLOCKSIZE per transfer request.
1 : ALL
One transfer request transfers all units as defined by the XFRCNT field.
End of enumeration elements list.
DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write
IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write
SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ONE
Increment source address by one unit data size after each read
1 : TWO
Increment source address by two unit data sizes after each read
2 : FOUR
Increment source address by four unit data sizes after each read
3 : NONE
Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
End of enumeration elements list.
SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : BYTE
Each unit transfer is a byte
1 : HALFWORD
Each unit transfer is a half-word
2 : WORD
Each unit transfer is a word
End of enumeration elements list.
DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ONE
Increment destination address by one unit data size after each write
1 : TWO
Increment destination address by two unit data sizes after each write
2 : FOUR
Increment destination address by four unit data sizes after each write
3 : NONE
Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.
End of enumeration elements list.
SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.
1 : RELATIVE
The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.
End of enumeration elements list.
DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.
1 : RELATIVE
The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.
End of enumeration elements list.
No Description
address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x12C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.
1 : RELATIVE
The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor.
End of enumeration elements list.
LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write
LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write
No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SYNCSWCLR : DMA SYNC Software Trigger Clear
bits : 0 - 7 (8 bit)
access : write-only
No Description
address_offset : 0x14C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ONE
One arbitration slot selected
1 : TWO
Two arbitration slots selected
2 : FOUR
Four arbitration slots selected
3 : EIGHT
Eight arbitration slots selected
End of enumeration elements list.
SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : POSITIVE
Increment source address
1 : NEGATIVE
Decrement source address
End of enumeration elements list.
DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : POSITIVE
Increment destination address
1 : NEGATIVE
Decrement destination address
End of enumeration elements list.
No Description
address_offset : 0x150 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0x154 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TRANSFER
DMA transfer structure type selected.
1 : SYNCHRONIZE
Synchronization structure type selected.
2 : WRITE
Write immediate value structure type selected.
End of enumeration elements list.
STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : read-only
XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write
BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write
BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : UNIT1
One unit transfer per arbitration
1 : UNIT2
Two unit transfers per arbitration
2 : UNIT3
Three unit transfers per arbitration
3 : UNIT4
Four unit transfers per arbitration
4 : UNIT6
Six unit transfers per arbitration
5 : UNIT8
Eight unit transfers per arbitration
7 : UNIT16
Sixteen unit transfers per arbitration
9 : UNIT32
32 unit transfers per arbitration
10 : UNIT64
64 unit transfers per arbitration
11 : UNIT128
128 unit transfers per arbitration
12 : UNIT256
256 unit transfers per arbitration
13 : UNIT512
512 unit transfers per arbitration
14 : UNIT1024
1024 unit transfers per arbitration
15 : ALL
Transfer all units as specified by the XFRCNT field
End of enumeration elements list.
DONEIEN : DMA Operation Done Interrupt Flag Set En
bits : 20 - 20 (1 bit)
access : read-write
REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : BLOCK
The LDMA transfers one BLOCKSIZE per transfer request.
1 : ALL
One transfer request transfers all units as defined by the XFRCNT field.
End of enumeration elements list.
DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write
IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write
SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ONE
Increment source address by one unit data size after each read
1 : TWO
Increment source address by two unit data sizes after each read
2 : FOUR
Increment source address by four unit data sizes after each read
3 : NONE
Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
End of enumeration elements list.
SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : BYTE
Each unit transfer is a byte
1 : HALFWORD
Each unit transfer is a half-word
2 : WORD
Each unit transfer is a word
End of enumeration elements list.
DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ONE
Increment destination address by one unit data size after each write
1 : TWO
Increment destination address by two unit data sizes after each write
2 : FOUR
Increment destination address by four unit data sizes after each write
3 : NONE
Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.
End of enumeration elements list.
SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.
1 : RELATIVE
The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.
End of enumeration elements list.
DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.
1 : RELATIVE
The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.
End of enumeration elements list.
No Description
address_offset : 0x158 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x15C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x160 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.
1 : RELATIVE
The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor.
End of enumeration elements list.
LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write
LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write
No Description
address_offset : 0x17C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ONE
One arbitration slot selected
1 : TWO
Two arbitration slots selected
2 : FOUR
Four arbitration slots selected
3 : EIGHT
Eight arbitration slots selected
End of enumeration elements list.
SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : POSITIVE
Increment source address
1 : NEGATIVE
Decrement source address
End of enumeration elements list.
DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : POSITIVE
Increment destination address
1 : NEGATIVE
Decrement destination address
End of enumeration elements list.
No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCSETEN : Hardware Sync Trigger Set Enable
bits : 0 - 7 (8 bit)
access : read-write
SYNCCLREN : Hardware Sync Trigger Clear Enable
bits : 16 - 23 (8 bit)
access : read-write
No Description
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0x184 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TRANSFER
DMA transfer structure type selected.
1 : SYNCHRONIZE
Synchronization structure type selected.
2 : WRITE
Write immediate value structure type selected.
End of enumeration elements list.
STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : read-only
XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write
BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write
BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : UNIT1
One unit transfer per arbitration
1 : UNIT2
Two unit transfers per arbitration
2 : UNIT3
Three unit transfers per arbitration
3 : UNIT4
Four unit transfers per arbitration
4 : UNIT6
Six unit transfers per arbitration
5 : UNIT8
Eight unit transfers per arbitration
7 : UNIT16
Sixteen unit transfers per arbitration
9 : UNIT32
32 unit transfers per arbitration
10 : UNIT64
64 unit transfers per arbitration
11 : UNIT128
128 unit transfers per arbitration
12 : UNIT256
256 unit transfers per arbitration
13 : UNIT512
512 unit transfers per arbitration
14 : UNIT1024
1024 unit transfers per arbitration
15 : ALL
Transfer all units as specified by the XFRCNT field
End of enumeration elements list.
DONEIEN : DMA Operation Done Interrupt Flag Set En
bits : 20 - 20 (1 bit)
access : read-write
REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : BLOCK
The LDMA transfers one BLOCKSIZE per transfer request.
1 : ALL
One transfer request transfers all units as defined by the XFRCNT field.
End of enumeration elements list.
DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write
IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write
SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ONE
Increment source address by one unit data size after each read
1 : TWO
Increment source address by two unit data sizes after each read
2 : FOUR
Increment source address by four unit data sizes after each read
3 : NONE
Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
End of enumeration elements list.
SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : BYTE
Each unit transfer is a byte
1 : HALFWORD
Each unit transfer is a half-word
2 : WORD
Each unit transfer is a word
End of enumeration elements list.
DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ONE
Increment destination address by one unit data size after each write
1 : TWO
Increment destination address by two unit data sizes after each write
2 : FOUR
Increment destination address by four unit data sizes after each write
3 : NONE
Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.
End of enumeration elements list.
SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.
1 : RELATIVE
The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.
End of enumeration elements list.
DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.
1 : RELATIVE
The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.
End of enumeration elements list.
No Description
address_offset : 0x188 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x18C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x190 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.
1 : RELATIVE
The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor.
End of enumeration elements list.
LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write
LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write
No Description
address_offset : 0x1AC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ONE
One arbitration slot selected
1 : TWO
Two arbitration slots selected
2 : FOUR
Four arbitration slots selected
3 : EIGHT
Eight arbitration slots selected
End of enumeration elements list.
SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : POSITIVE
Increment source address
1 : NEGATIVE
Decrement source address
End of enumeration elements list.
DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : POSITIVE
Increment destination address
1 : NEGATIVE
Decrement destination address
End of enumeration elements list.
No Description
address_offset : 0x1B0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0x1B4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TRANSFER
DMA transfer structure type selected.
1 : SYNCHRONIZE
Synchronization structure type selected.
2 : WRITE
Write immediate value structure type selected.
End of enumeration elements list.
STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : read-only
XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write
BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write
BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : UNIT1
One unit transfer per arbitration
1 : UNIT2
Two unit transfers per arbitration
2 : UNIT3
Three unit transfers per arbitration
3 : UNIT4
Four unit transfers per arbitration
4 : UNIT6
Six unit transfers per arbitration
5 : UNIT8
Eight unit transfers per arbitration
7 : UNIT16
Sixteen unit transfers per arbitration
9 : UNIT32
32 unit transfers per arbitration
10 : UNIT64
64 unit transfers per arbitration
11 : UNIT128
128 unit transfers per arbitration
12 : UNIT256
256 unit transfers per arbitration
13 : UNIT512
512 unit transfers per arbitration
14 : UNIT1024
1024 unit transfers per arbitration
15 : ALL
Transfer all units as specified by the XFRCNT field
End of enumeration elements list.
DONEIEN : DMA Operation Done Interrupt Flag Set En
bits : 20 - 20 (1 bit)
access : read-write
REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : BLOCK
The LDMA transfers one BLOCKSIZE per transfer request.
1 : ALL
One transfer request transfers all units as defined by the XFRCNT field.
End of enumeration elements list.
DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write
IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write
SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ONE
Increment source address by one unit data size after each read
1 : TWO
Increment source address by two unit data sizes after each read
2 : FOUR
Increment source address by four unit data sizes after each read
3 : NONE
Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
End of enumeration elements list.
SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : BYTE
Each unit transfer is a byte
1 : HALFWORD
Each unit transfer is a half-word
2 : WORD
Each unit transfer is a word
End of enumeration elements list.
DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ONE
Increment destination address by one unit data size after each write
1 : TWO
Increment destination address by two unit data sizes after each write
2 : FOUR
Increment destination address by four unit data sizes after each write
3 : NONE
Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.
End of enumeration elements list.
SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.
1 : RELATIVE
The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.
End of enumeration elements list.
DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.
1 : RELATIVE
The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.
End of enumeration elements list.
No Description
address_offset : 0x1B8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x1BC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCSETEDGE : Hardware Sync Trigger Set Edge Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : RISE
Use rising edge detection
1 : FALL
Use falling edge detection
End of enumeration elements list.
SYNCCLREDGE : Hardware Sync Trigger Clear Edge Select
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : RISE
Use rising edge detection
1 : FALL
Use falling edge detection
End of enumeration elements list.
No Description
address_offset : 0x1C0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.
1 : RELATIVE
The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor.
End of enumeration elements list.
LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write
LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write
No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYNCTRIG : sync trig status
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enables
bits : 0 - 7 (8 bit)
access : write-only
No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHDIS : DMA Channel disable
bits : 0 - 7 (8 bit)
access : write-only
No Description
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHSTATUS : DMA Channel Status
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : Channels Busy
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHDONE0 : DMA Channel Link done intr flag
bits : 0 - 0 (1 bit)
access : read-write
CHDONE1 : DMA Channel Link done intr flag
bits : 1 - 1 (1 bit)
access : read-write
CHDONE2 : DMA Channel Link done intr flag
bits : 2 - 2 (1 bit)
access : read-write
CHDONE3 : DMA Channel Link done intr flag
bits : 3 - 3 (1 bit)
access : read-write
CHDONE4 : DMA Channel Link done intr flag
bits : 4 - 4 (1 bit)
access : read-write
CHDONE5 : DMA Channel Link done intr flag
bits : 5 - 5 (1 bit)
access : read-write
CHDONE6 : DMA Channel Link done intr flag
bits : 6 - 6 (1 bit)
access : read-write
CHDONE7 : DMA Channel Link done intr flag
bits : 7 - 7 (1 bit)
access : read-write
No Description
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGHALT : DMA Debug Halt
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWREQ : Software Transfer Requests
bits : 0 - 7 (8 bit)
access : write-only
No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : LDMA module enable and disable register
bits : 0 - 0 (1 bit)
access : read-write
No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQDIS : DMA Request Disables
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REQPEND : DMA Requests Pending
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LINKLOAD : DMA Link Loads
bits : 0 - 7 (8 bit)
access : write-only
No Description
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
REQCLEAR : DMA Request Clear
bits : 0 - 7 (8 bit)
access : write-only
No Description
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DONE0 : DMA Structure Operation Done
bits : 0 - 0 (1 bit)
access : read-write
DONE1 : DMA Structure Operation Done
bits : 1 - 1 (1 bit)
access : read-write
DONE2 : DMA Structure Operation Done
bits : 2 - 2 (1 bit)
access : read-write
DONE3 : DMA Structure Operation Done
bits : 3 - 3 (1 bit)
access : read-write
DONE4 : DMA Structure Operation Done
bits : 4 - 4 (1 bit)
access : read-write
DONE5 : DMA Structure Operation Done
bits : 5 - 5 (1 bit)
access : read-write
DONE6 : DMA Structure Operation Done
bits : 6 - 6 (1 bit)
access : read-write
DONE7 : DMA Structure Operation Done
bits : 7 - 7 (1 bit)
access : read-write
ERROR : Error Flag
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHDONE : Enable or disable the done interrupt
bits : 0 - 7 (8 bit)
access : read-write
ERROR : Enable or disable the error interrupt
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ONE
One arbitration slot selected
1 : TWO
Two arbitration slots selected
2 : FOUR
Four arbitration slots selected
3 : EIGHT
Eight arbitration slots selected
End of enumeration elements list.
SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : POSITIVE
Increment source address
1 : NEGATIVE
Decrement source address
End of enumeration elements list.
DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : POSITIVE
Increment destination address
1 : NEGATIVE
Decrement destination address
End of enumeration elements list.
No Description
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TRANSFER
DMA transfer structure type selected.
1 : SYNCHRONIZE
Synchronization structure type selected.
2 : WRITE
Write immediate value structure type selected.
End of enumeration elements list.
STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : read-only
XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write
BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write
BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : UNIT1
One unit transfer per arbitration
1 : UNIT2
Two unit transfers per arbitration
2 : UNIT3
Three unit transfers per arbitration
3 : UNIT4
Four unit transfers per arbitration
4 : UNIT6
Six unit transfers per arbitration
5 : UNIT8
Eight unit transfers per arbitration
7 : UNIT16
Sixteen unit transfers per arbitration
9 : UNIT32
32 unit transfers per arbitration
10 : UNIT64
64 unit transfers per arbitration
11 : UNIT128
128 unit transfers per arbitration
12 : UNIT256
256 unit transfers per arbitration
13 : UNIT512
512 unit transfers per arbitration
14 : UNIT1024
1024 unit transfers per arbitration
15 : ALL
Transfer all units as specified by the XFRCNT field
End of enumeration elements list.
DONEIEN : DMA Operation Done Interrupt Flag Set En
bits : 20 - 20 (1 bit)
access : read-write
REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : BLOCK
The LDMA transfers one BLOCKSIZE per transfer request.
1 : ALL
One transfer request transfers all units as defined by the XFRCNT field.
End of enumeration elements list.
DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write
IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write
SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ONE
Increment source address by one unit data size after each read
1 : TWO
Increment source address by two unit data sizes after each read
2 : FOUR
Increment source address by four unit data sizes after each read
3 : NONE
Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
End of enumeration elements list.
SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : BYTE
Each unit transfer is a byte
1 : HALFWORD
Each unit transfer is a half-word
2 : WORD
Each unit transfer is a word
End of enumeration elements list.
DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ONE
Increment destination address by one unit data size after each write
1 : TWO
Increment destination address by two unit data sizes after each write
2 : FOUR
Increment destination address by four unit data sizes after each write
3 : NONE
Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.
End of enumeration elements list.
SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.
1 : RELATIVE
The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.
End of enumeration elements list.
DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.
1 : RELATIVE
The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.
End of enumeration elements list.
No Description
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.
1 : RELATIVE
The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor.
End of enumeration elements list.
LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write
LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write
No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUMFIXED : Number of Fixed Priority Channels
bits : 24 - 28 (5 bit)
access : read-write
CORERST : Reset DMA controller
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ONE
One arbitration slot selected
1 : TWO
Two arbitration slots selected
2 : FOUR
Four arbitration slots selected
3 : EIGHT
Eight arbitration slots selected
End of enumeration elements list.
SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : POSITIVE
Increment source address
1 : NEGATIVE
Decrement source address
End of enumeration elements list.
DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : POSITIVE
Increment destination address
1 : NEGATIVE
Decrement destination address
End of enumeration elements list.
No Description
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TRANSFER
DMA transfer structure type selected.
1 : SYNCHRONIZE
Synchronization structure type selected.
2 : WRITE
Write immediate value structure type selected.
End of enumeration elements list.
STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : read-only
XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write
BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write
BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : UNIT1
One unit transfer per arbitration
1 : UNIT2
Two unit transfers per arbitration
2 : UNIT3
Three unit transfers per arbitration
3 : UNIT4
Four unit transfers per arbitration
4 : UNIT6
Six unit transfers per arbitration
5 : UNIT8
Eight unit transfers per arbitration
7 : UNIT16
Sixteen unit transfers per arbitration
9 : UNIT32
32 unit transfers per arbitration
10 : UNIT64
64 unit transfers per arbitration
11 : UNIT128
128 unit transfers per arbitration
12 : UNIT256
256 unit transfers per arbitration
13 : UNIT512
512 unit transfers per arbitration
14 : UNIT1024
1024 unit transfers per arbitration
15 : ALL
Transfer all units as specified by the XFRCNT field
End of enumeration elements list.
DONEIEN : DMA Operation Done Interrupt Flag Set En
bits : 20 - 20 (1 bit)
access : read-write
REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : BLOCK
The LDMA transfers one BLOCKSIZE per transfer request.
1 : ALL
One transfer request transfers all units as defined by the XFRCNT field.
End of enumeration elements list.
DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write
IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write
SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ONE
Increment source address by one unit data size after each read
1 : TWO
Increment source address by two unit data sizes after each read
2 : FOUR
Increment source address by four unit data sizes after each read
3 : NONE
Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
End of enumeration elements list.
SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : BYTE
Each unit transfer is a byte
1 : HALFWORD
Each unit transfer is a half-word
2 : WORD
Each unit transfer is a word
End of enumeration elements list.
DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ONE
Increment destination address by one unit data size after each write
1 : TWO
Increment destination address by two unit data sizes after each write
2 : FOUR
Increment destination address by four unit data sizes after each write
3 : NONE
Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.
End of enumeration elements list.
SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.
1 : RELATIVE
The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.
End of enumeration elements list.
DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.
1 : RELATIVE
The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.
End of enumeration elements list.
No Description
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.
1 : RELATIVE
The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor.
End of enumeration elements list.
LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write
LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write
No Description
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ONE
One arbitration slot selected
1 : TWO
Two arbitration slots selected
2 : FOUR
Four arbitration slots selected
3 : EIGHT
Eight arbitration slots selected
End of enumeration elements list.
SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : POSITIVE
Increment source address
1 : NEGATIVE
Decrement source address
End of enumeration elements list.
DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : POSITIVE
Increment destination address
1 : NEGATIVE
Decrement destination address
End of enumeration elements list.
No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ANYBUSY : Any DMA Channel Busy
bits : 0 - 0 (1 bit)
access : read-only
ANYREQ : Any DMA Channel Request Pending
bits : 1 - 1 (1 bit)
access : read-only
CHGRANT : Granted Channel Number
bits : 3 - 7 (5 bit)
access : read-only
CHERROR : Errant Channel Number
bits : 8 - 12 (5 bit)
access : read-only
FIFOLEVEL : FIFO Level
bits : 16 - 20 (5 bit)
access : read-only
CHNUM : Number of Channels
bits : 24 - 28 (5 bit)
access : read-only
No Description
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TRANSFER
DMA transfer structure type selected.
1 : SYNCHRONIZE
Synchronization structure type selected.
2 : WRITE
Write immediate value structure type selected.
End of enumeration elements list.
STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : read-only
XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write
BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write
BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : UNIT1
One unit transfer per arbitration
1 : UNIT2
Two unit transfers per arbitration
2 : UNIT3
Three unit transfers per arbitration
3 : UNIT4
Four unit transfers per arbitration
4 : UNIT6
Six unit transfers per arbitration
5 : UNIT8
Eight unit transfers per arbitration
7 : UNIT16
Sixteen unit transfers per arbitration
9 : UNIT32
32 unit transfers per arbitration
10 : UNIT64
64 unit transfers per arbitration
11 : UNIT128
128 unit transfers per arbitration
12 : UNIT256
256 unit transfers per arbitration
13 : UNIT512
512 unit transfers per arbitration
14 : UNIT1024
1024 unit transfers per arbitration
15 : ALL
Transfer all units as specified by the XFRCNT field
End of enumeration elements list.
DONEIEN : DMA Operation Done Interrupt Flag Set En
bits : 20 - 20 (1 bit)
access : read-write
REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : BLOCK
The LDMA transfers one BLOCKSIZE per transfer request.
1 : ALL
One transfer request transfers all units as defined by the XFRCNT field.
End of enumeration elements list.
DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write
IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write
SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ONE
Increment source address by one unit data size after each read
1 : TWO
Increment source address by two unit data sizes after each read
2 : FOUR
Increment source address by four unit data sizes after each read
3 : NONE
Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
End of enumeration elements list.
SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : BYTE
Each unit transfer is a byte
1 : HALFWORD
Each unit transfer is a half-word
2 : WORD
Each unit transfer is a word
End of enumeration elements list.
DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ONE
Increment destination address by one unit data size after each write
1 : TWO
Increment destination address by two unit data sizes after each write
2 : FOUR
Increment destination address by four unit data sizes after each write
3 : NONE
Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.
End of enumeration elements list.
SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.
1 : RELATIVE
The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.
End of enumeration elements list.
DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.
1 : RELATIVE
The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.
End of enumeration elements list.
No Description
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.
1 : RELATIVE
The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor.
End of enumeration elements list.
LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write
LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write
No Description
address_offset : 0xEC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ONE
One arbitration slot selected
1 : TWO
Two arbitration slots selected
2 : FOUR
Four arbitration slots selected
3 : EIGHT
Eight arbitration slots selected
End of enumeration elements list.
SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : POSITIVE
Increment source address
1 : NEGATIVE
Decrement source address
End of enumeration elements list.
DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : POSITIVE
Increment destination address
1 : NEGATIVE
Decrement destination address
End of enumeration elements list.
No Description
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0xF4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TRANSFER
DMA transfer structure type selected.
1 : SYNCHRONIZE
Synchronization structure type selected.
2 : WRITE
Write immediate value structure type selected.
End of enumeration elements list.
STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : read-only
XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write
BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write
BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : UNIT1
One unit transfer per arbitration
1 : UNIT2
Two unit transfers per arbitration
2 : UNIT3
Three unit transfers per arbitration
3 : UNIT4
Four unit transfers per arbitration
4 : UNIT6
Six unit transfers per arbitration
5 : UNIT8
Eight unit transfers per arbitration
7 : UNIT16
Sixteen unit transfers per arbitration
9 : UNIT32
32 unit transfers per arbitration
10 : UNIT64
64 unit transfers per arbitration
11 : UNIT128
128 unit transfers per arbitration
12 : UNIT256
256 unit transfers per arbitration
13 : UNIT512
512 unit transfers per arbitration
14 : UNIT1024
1024 unit transfers per arbitration
15 : ALL
Transfer all units as specified by the XFRCNT field
End of enumeration elements list.
DONEIEN : DMA Operation Done Interrupt Flag Set En
bits : 20 - 20 (1 bit)
access : read-write
REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : BLOCK
The LDMA transfers one BLOCKSIZE per transfer request.
1 : ALL
One transfer request transfers all units as defined by the XFRCNT field.
End of enumeration elements list.
DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write
IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write
SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ONE
Increment source address by one unit data size after each read
1 : TWO
Increment source address by two unit data sizes after each read
2 : FOUR
Increment source address by four unit data sizes after each read
3 : NONE
Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
End of enumeration elements list.
SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : BYTE
Each unit transfer is a byte
1 : HALFWORD
Each unit transfer is a half-word
2 : WORD
Each unit transfer is a word
End of enumeration elements list.
DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ONE
Increment destination address by one unit data size after each write
1 : TWO
Increment destination address by two unit data sizes after each write
2 : FOUR
Increment destination address by four unit data sizes after each write
3 : NONE
Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.
End of enumeration elements list.
SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.
1 : RELATIVE
The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.
End of enumeration elements list.
DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : ABSOLUTE
The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.
1 : RELATIVE
The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.
End of enumeration elements list.
No Description
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write
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