\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP Version ID
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUNNING : Running
bits : 0 - 0 (1 bit)
access : read-only
DIR : Direction
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : UP
Counting up
1 : DOWN
Counting down
End of enumeration elements list.
TOPBV : TOP Buffer Valid
bits : 2 - 2 (1 bit)
access : read-only
TIMERLOCKSTATUS : Timer lock status
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : UNLOCKED
TIMER registers are unlocked
1 : LOCKED
TIMER registers are locked
End of enumeration elements list.
DTILOCKSTATUS : DTI lock status
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : UNLOCKED
DTI registers are unlocked
1 : LOCKED
DTI registers are locked
End of enumeration elements list.
SYNCBUSY : Sync Busy
bits : 6 - 6 (1 bit)
access : read-only
OCBV0 : Output Compare Buffer Valid
bits : 8 - 8 (1 bit)
access : read-only
OCBV1 : Output Compare Buffer Valid
bits : 9 - 9 (1 bit)
access : read-only
OCBV2 : Output Compare Buffer Valid
bits : 10 - 10 (1 bit)
access : read-only
ICFEMPTY0 : Input capture fifo empty
bits : 16 - 16 (1 bit)
access : read-only
ICFEMPTY1 : Input capture fifo empty
bits : 17 - 17 (1 bit)
access : read-only
ICFEMPTY2 : Input capture fifo empty
bits : 18 - 18 (1 bit)
access : read-only
CCPOL0 : CCn Polarity
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : LOWRISE
CC0 polarity low level/rising edge
1 : HIGHFALL
CC0 polarity high level/falling edge
End of enumeration elements list.
CCPOL1 : CCn Polarity
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : LOWRISE
CC0 polarity low level/rising edge
1 : HIGHFALL
CC0 polarity high level/falling edge
End of enumeration elements list.
CCPOL2 : CCn Polarity
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : LOWRISE
CC0 polarity low level/rising edge
1 : HIGHFALL
CC0 polarity high level/falling edge
End of enumeration elements list.
No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OF : Overflow Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
UF : Underflow Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write
DIRCHG : Direction Change Detect Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write
CC0 : Capture Compare Channel 0 Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write
CC1 : Capture Compare Channel 1 Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write
CC2 : Capture Compare Channel 2 Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write
ICFWLFULL0 : Input Capture Watermark Level Full
bits : 16 - 16 (1 bit)
access : read-write
ICFWLFULL1 : Input Capture Watermark Level Full
bits : 17 - 17 (1 bit)
access : read-write
ICFWLFULL2 : Input Capture Watermark Level Full
bits : 18 - 18 (1 bit)
access : read-write
ICFOF0 : Input Capture FIFO overflow
bits : 20 - 20 (1 bit)
access : read-write
ICFOF1 : Input Capture FIFO overflow
bits : 21 - 21 (1 bit)
access : read-write
ICFOF2 : Input Capture FIFO overflow
bits : 22 - 22 (1 bit)
access : read-write
ICFUF0 : Input capture FIFO underflow
bits : 24 - 24 (1 bit)
access : read-write
ICFUF1 : Input capture FIFO underflow
bits : 25 - 25 (1 bit)
access : read-write
ICFUF2 : Input capture FIFO underflow
bits : 26 - 26 (1 bit)
access : read-write
No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
UF : Underflow Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
DIRCHG : Direction Change Detect Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
CC0 : CC0 Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
CC1 : CC1 Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
CC2 : CC2 Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
ICFWLFULL0 : ICFWLFULL0 Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write
ICFWLFULL1 : ICFWLFULL1 Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
ICFWLFULL2 : ICFWLFULL2 Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write
ICFOF0 : ICFOF0 Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write
ICFOF1 : ICFOF1 Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write
ICFOF2 : ICFOF2 Interrupt Enable
bits : 22 - 22 (1 bit)
access : read-write
ICFUF0 : ICFUF0 Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write
ICFUF1 : ICFUF1 Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-write
ICFUF2 : ICFUF2 Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-write
No Description
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOP : Counter Top Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOPB : Counter Top Buffer Register
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Counter Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LOCKKEY : Timer Lock Key
bits : 0 - 15 (16 bit)
access : write-only
Enumeration:
52864 : UNLOCK
Write to unlock TIMER registers
End of enumeration elements list.
No Description
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Timer Module Enable
bits : 0 - 0 (1 bit)
access : read-write
DISABLING : Disablement busy status
bits : 1 - 1 (1 bit)
access : read-only
No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Timer Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : UP
Up-count mode
1 : DOWN
Down-count mode
2 : UPDOWN
Up/down-count mode
3 : QDEC
Quadrature decoder mode
End of enumeration elements list.
SYNC : Timer Start/Stop/Reload Synchronization
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Timer operation is unaffected by other timers.
1 : ENABLE
Timer may be started, stopped and re-loaded from other timer instances.
End of enumeration elements list.
OSMEN : One-shot Mode Enable
bits : 4 - 4 (1 bit)
access : read-write
QDM : Quadrature Decoder Mode Selection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : X2
X2 mode selected
1 : X4
X4 mode selected
End of enumeration elements list.
DEBUGRUN : Debug Mode Run Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HALT
Timer is halted in debug mode
1 : RUN
Timer is running in debug mode
End of enumeration elements list.
DMACLRACT : DMA Request Clear on Active
bits : 7 - 7 (1 bit)
access : read-write
CLKSEL : Clock Source Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PRESCEM01GRPACLK
Prescaled EM01GRPACLK
1 : CC1
Compare/Capture Channel 1 Input
2 : TIMEROUF
Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer
End of enumeration elements list.
RETIMEEN : PWM output retimed enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
PWM outputs are not re-timed.
1 : ENABLE
PWM outputs are re-timed.
End of enumeration elements list.
DISSYNCOUT : Disable Timer Start/Stop/Reload output
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : EN
Timer can start/stop/reload other timers with SYNC bit set
1 : DIS
Timer cannot start/stop/reload other timers with SYNC bit set
End of enumeration elements list.
RETIMESEL : PWM output retime select
bits : 12 - 12 (1 bit)
access : read-write
ATI : Always Track Inputs
bits : 16 - 16 (1 bit)
access : read-write
RSSCOIST : Reload-Start Sets COIST
bits : 17 - 17 (1 bit)
access : read-write
PRESC : Prescaler Setting
bits : 18 - 27 (10 bit)
access : read-write
Enumeration:
0 : DIV1
No prescaling
1 : DIV2
Prescale by 2
3 : DIV4
Prescale by 4
7 : DIV8
Prescale by 8
15 : DIV16
Prescale by 16
31 : DIV32
Prescale by 32
63 : DIV64
Prescale by 64
127 : DIV128
Prescale by 128
255 : DIV256
Prescale by 256
511 : DIV512
Prescale by 512
1023 : DIV1024
Prescale by 1024
End of enumeration elements list.
No Description
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : CC Channel Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Compare/Capture channel turned off
1 : INPUTCAPTURE
Input Capture
2 : OUTPUTCOMPARE
Output Compare
3 : PWM
Pulse-Width Modulation
End of enumeration elements list.
COIST : Compare Output Initial State
bits : 4 - 4 (1 bit)
access : read-write
INSEL : Input Selection
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0 : PIN
TIMERnCCx pin is selected
1 : PRSSYNC
Synchornous PRS selected
2 : PRSASYNCLEVEL
Asynchronous Level PRS selected
3 : PRSASYNCPULSE
Asynchronous Pulse PRS selected
End of enumeration elements list.
PRSCONF : PRS Configuration
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : PULSE
Each CC event will generate a one EM01GRPACLK cycle high pulse
1 : LEVEL
The PRS channel will follow CC out
End of enumeration elements list.
FILT : Digital Filter
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Digital Filter Disabled
1 : ENABLE
Digital Filter Enabled
End of enumeration elements list.
ICFWL : Input Capture FIFO watermark level
bits : 21 - 21 (1 bit)
access : read-write
No Description
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTINV : Output Invert
bits : 2 - 2 (1 bit)
access : read-write
CMOA : Compare Match Output Action
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : NONE
No action on compare match
1 : TOGGLE
Toggle output on compare match
2 : CLEAR
Clear output on compare match
3 : SET
Set output on compare match
End of enumeration elements list.
COFOA : Counter Overflow Output Action
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : NONE
No action on counter overflow
1 : TOGGLE
Toggle output on counter overflow
2 : CLEAR
Clear output on counter overflow
3 : SET
Set output on counter overflow
End of enumeration elements list.
CUFOA : Counter Underflow Output Action
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : NONE
No action on counter underflow
1 : TOGGLE
Toggle output on counter underflow
2 : CLEAR
Clear output on counter underflow
3 : SET
Set output on counter underflow
End of enumeration elements list.
ICEDGE : Input Capture Edge Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : NONE
No edge detection, signal is left as it is
End of enumeration elements list.
ICEVCTRL : Input Capture Event Control
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : EVERYEDGE
PRS output pulse and interrupt flag set on every capture
1 : EVERYSECONDEDGE
PRS output pulse and interrupt flag set on every second capture
2 : RISING
PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH)
3 : FALLING
PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH)
End of enumeration elements list.
No Description
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OC : Output Compare Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCB : Output Compare Value Buffer
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICF : Input Capture FIFO
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICOF : Input Capture FIFO Overflow
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RISEA : Timer Rising Input Edge Action
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : NONE
No action
1 : START
Start counter without reload
2 : STOP
Stop counter without reload
3 : RELOADSTART
Reload and start counter
End of enumeration elements list.
FALLA : Timer Falling Input Edge Action
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : NONE
No action
1 : START
Start counter without reload
2 : STOP
Stop counter without reload
3 : RELOADSTART
Reload and start counter
End of enumeration elements list.
X2CNT : 2x Count Mode
bits : 4 - 4 (1 bit)
access : read-write
No Description
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : CC Channel Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Compare/Capture channel turned off
1 : INPUTCAPTURE
Input Capture
2 : OUTPUTCOMPARE
Output Compare
3 : PWM
Pulse-Width Modulation
End of enumeration elements list.
COIST : Compare Output Initial State
bits : 4 - 4 (1 bit)
access : read-write
INSEL : Input Selection
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0 : PIN
TIMERnCCx pin is selected
1 : PRSSYNC
Synchornous PRS selected
2 : PRSASYNCLEVEL
Asynchronous Level PRS selected
3 : PRSASYNCPULSE
Asynchronous Pulse PRS selected
End of enumeration elements list.
PRSCONF : PRS Configuration
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : PULSE
Each CC event will generate a one EM01GRPACLK cycle high pulse
1 : LEVEL
The PRS channel will follow CC out
End of enumeration elements list.
FILT : Digital Filter
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Digital Filter Disabled
1 : ENABLE
Digital Filter Enabled
End of enumeration elements list.
ICFWL : Input Capture FIFO watermark level
bits : 21 - 21 (1 bit)
access : read-write
No Description
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTINV : Output Invert
bits : 2 - 2 (1 bit)
access : read-write
CMOA : Compare Match Output Action
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : NONE
No action on compare match
1 : TOGGLE
Toggle output on compare match
2 : CLEAR
Clear output on compare match
3 : SET
Set output on compare match
End of enumeration elements list.
COFOA : Counter Overflow Output Action
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : NONE
No action on counter overflow
1 : TOGGLE
Toggle output on counter overflow
2 : CLEAR
Clear output on counter overflow
3 : SET
Set output on counter overflow
End of enumeration elements list.
CUFOA : Counter Underflow Output Action
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : NONE
No action on counter underflow
1 : TOGGLE
Toggle output on counter underflow
2 : CLEAR
Clear output on counter underflow
3 : SET
Set output on counter underflow
End of enumeration elements list.
ICEDGE : Input Capture Edge Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : NONE
No edge detection, signal is left as it is
End of enumeration elements list.
ICEVCTRL : Input Capture Event Control
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : EVERYEDGE
PRS output pulse and interrupt flag set on every capture
1 : EVERYSECONDEDGE
PRS output pulse and interrupt flag set on every second capture
2 : RISING
PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH)
3 : FALLING
PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH)
End of enumeration elements list.
No Description
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OC : Output Compare Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCB : Output Compare Value Buffer
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICF : Input Capture FIFO
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICOF : Input Capture FIFO Overflow
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : CC Channel Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Compare/Capture channel turned off
1 : INPUTCAPTURE
Input Capture
2 : OUTPUTCOMPARE
Output Compare
3 : PWM
Pulse-Width Modulation
End of enumeration elements list.
COIST : Compare Output Initial State
bits : 4 - 4 (1 bit)
access : read-write
INSEL : Input Selection
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0 : PIN
TIMERnCCx pin is selected
1 : PRSSYNC
Synchornous PRS selected
2 : PRSASYNCLEVEL
Asynchronous Level PRS selected
3 : PRSASYNCPULSE
Asynchronous Pulse PRS selected
End of enumeration elements list.
PRSCONF : PRS Configuration
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : PULSE
Each CC event will generate a one EM01GRPACLK cycle high pulse
1 : LEVEL
The PRS channel will follow CC out
End of enumeration elements list.
FILT : Digital Filter
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Digital Filter Disabled
1 : ENABLE
Digital Filter Enabled
End of enumeration elements list.
ICFWL : Input Capture FIFO watermark level
bits : 21 - 21 (1 bit)
access : read-write
No Description
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTINV : Output Invert
bits : 2 - 2 (1 bit)
access : read-write
CMOA : Compare Match Output Action
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : NONE
No action on compare match
1 : TOGGLE
Toggle output on compare match
2 : CLEAR
Clear output on compare match
3 : SET
Set output on compare match
End of enumeration elements list.
COFOA : Counter Overflow Output Action
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : NONE
No action on counter overflow
1 : TOGGLE
Toggle output on counter overflow
2 : CLEAR
Clear output on counter overflow
3 : SET
Set output on counter overflow
End of enumeration elements list.
CUFOA : Counter Underflow Output Action
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : NONE
No action on counter underflow
1 : TOGGLE
Toggle output on counter underflow
2 : CLEAR
Clear output on counter underflow
3 : SET
Set output on counter underflow
End of enumeration elements list.
ICEDGE : Input Capture Edge Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : NONE
No edge detection, signal is left as it is
End of enumeration elements list.
ICEVCTRL : Input Capture Event Control
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : EVERYEDGE
PRS output pulse and interrupt flag set on every capture
1 : EVERYSECONDEDGE
PRS output pulse and interrupt flag set on every second capture
2 : RISING
PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH)
3 : FALLING
PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH)
End of enumeration elements list.
No Description
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OC : Output Compare Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCB : Output Compare Value Buffer
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICF : Input Capture FIFO
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICOF : Input Capture FIFO Overflow
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
START : Start Timer
bits : 0 - 0 (1 bit)
access : write-only
STOP : Stop Timer
bits : 1 - 1 (1 bit)
access : write-only
No Description
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTEN : DTI Enable
bits : 0 - 0 (1 bit)
access : read-write
DTDAS : DTI Automatic Start-up Functionality
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NORESTART
No DTI restart on debugger exit
1 : RESTART
DTI restart on debugger exit
End of enumeration elements list.
DTAR : DTI Always Run
bits : 9 - 9 (1 bit)
access : read-write
DTFATS : DTI Fault Action on Timer Stop
bits : 10 - 10 (1 bit)
access : read-write
DTPRSEN : DTI PRS Source Enable
bits : 11 - 11 (1 bit)
access : read-write
No Description
address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTPRESC : DTI Prescaler Setting
bits : 0 - 9 (10 bit)
access : read-write
DTRISET : DTI Rise-time
bits : 10 - 15 (6 bit)
access : read-write
DTFALLT : DTI Fall-time
bits : 16 - 21 (6 bit)
access : read-write
No Description
address_offset : 0xE8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTFA : DTI Fault Action
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : NONE
No action on fault
1 : INACTIVE
Set outputs inactive
2 : CLEAR
Clear outputs
3 : TRISTATE
Tristate outputs
End of enumeration elements list.
DTPRS0FEN : DTI PRS 0 Fault Enable
bits : 24 - 24 (1 bit)
access : read-write
DTPRS1FEN : DTI PRS 1 Fault Enable
bits : 25 - 25 (1 bit)
access : read-write
DTDBGFEN : DTI Debugger Fault Enable
bits : 26 - 26 (1 bit)
access : read-write
DTLOCKUPFEN : DTI Lockup Fault Enable
bits : 27 - 27 (1 bit)
access : read-write
DTEM23FEN : DTI EM23 Fault Enable
bits : 28 - 28 (1 bit)
access : read-write
No Description
address_offset : 0xEC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCINV : DTI Complementary Output Invert.
bits : 0 - 0 (1 bit)
access : read-write
DTIPOL : DTI Inactive Polarity
bits : 1 - 1 (1 bit)
access : read-write
No Description
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTOGCC0EN : DTI CCn Output Generation Enable
bits : 0 - 0 (1 bit)
access : read-write
DTOGCC1EN : DTI CCn Output Generation Enable
bits : 1 - 1 (1 bit)
access : read-write
DTOGCC2EN : DTI CCn Output Generation Enable
bits : 2 - 2 (1 bit)
access : read-write
DTOGCDTI0EN : DTI CDTIn Output Generation Enable
bits : 3 - 3 (1 bit)
access : read-write
DTOGCDTI1EN : DTI CDTIn Output Generation Enable
bits : 4 - 4 (1 bit)
access : read-write
DTOGCDTI2EN : DTI CDTIn Output Generation Enable
bits : 5 - 5 (1 bit)
access : read-write
No Description
address_offset : 0xF4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTPRS0F : DTI PRS 0 Fault
bits : 0 - 0 (1 bit)
access : read-only
DTPRS1F : DTI PRS 1 Fault
bits : 1 - 1 (1 bit)
access : read-only
DTDBGF : DTI Debugger Fault
bits : 2 - 2 (1 bit)
access : read-only
DTLOCKUPF : DTI Lockup Fault
bits : 3 - 3 (1 bit)
access : read-only
DTEM23F : DTI EM23 Entry Fault
bits : 4 - 4 (1 bit)
access : read-only
No Description
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTPRS0FC : DTI PRS0 Fault Clear
bits : 0 - 0 (1 bit)
access : write-only
DTPRS1FC : DTI PRS1 Fault Clear
bits : 1 - 1 (1 bit)
access : write-only
DTDBGFC : DTI Debugger Fault Clear
bits : 2 - 2 (1 bit)
access : write-only
DTLOCKUPFC : DTI Lockup Fault Clear
bits : 3 - 3 (1 bit)
access : write-only
DTEM23FC : DTI EM23 Fault Clear
bits : 4 - 4 (1 bit)
access : write-only
No Description
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTILOCKKEY : DTI Lock Key
bits : 0 - 15 (16 bit)
access : write-only
Enumeration:
52864 : UNLOCK
Write to unlock TIMER DTI registers
End of enumeration elements list.
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