Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP Version ID
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COREBIASSTARTUPI : Intermediate Startup Core Bias Current
bits : 0 - 5 (6 bit)
access : read-write
COREBIASSTARTUP : Startup Core Bias Current
bits : 6 - 11 (6 bit)
access : read-write
CTUNEXISTARTUP : Startup Tuning Capacitance on XI
bits : 12 - 15 (4 bit)
access : read-write
CTUNEXOSTARTUP : Startup Tuning Capacitance on XO
bits : 16 - 19 (4 bit)
access : read-write
TIMEOUTSTEADY : Steady State Timeout
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0 : T4US
The steady state timeout is set to 16 us minimum. The maximum can be +40%.
1 : T16US
The steady state timeout is set to 41 us minimum. The maximum can be +40%.
2 : T41US
The steady state timeout is set to 83 us minimum. The maximum can be +40%.
3 : T83US
The steady state timeout is set to 125 us minimum. The maximum can be +40%.
4 : T125US
The steady state timeout is set to 166 us minimum. The maximum can be +40%.
5 : T166US
The steady state timeout is set to 208 us minimum. The maximum can be +40%.
6 : T208US
The steady state timeout is set to 250 us minimum. The maximum can be +40%.
7 : T250US
The steady state timeout is set to 333 us minimum. The maximum can be +40%.
8 : T333US
The steady state timeout is set to 416 us minimum. The maximum can be +40%.
9 : T416US
The steady state timeout is set to 500 us minimum. The maximum can be +40%.
10 : T500US
The steady state timeout is set to 666 us minimum. The maximum can be +40%.
11 : T666US
The steady state timeout is set to 833 us minimum. The maximum can be +40%.
12 : T833US
The steady state timeout is set to 1666 us minimum. The maximum can be +40%.
13 : T1666US
The steady state timeout is set to 2500 us minimum. The maximum can be +40%.
14 : T2500US
The steady state timeout is set to 4166 us minimum. The maximum can be +40%.
15 : T4166US
The steady state timeout is set to 7500 us minimum. The maximum can be +40%.
End of enumeration elements list.
TIMEOUTCBLSB : Core Bias LSB Change Timeout
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : T8US
The core bias LSB change timeout is set to 8 us minimum. The maximum can be +40%.
1 : T20US
The core bias LSB change timeout is set to 20 us minimum. The maximum can be +40%.
2 : T41US
The core bias LSB change timeout is set to 41 us minimum. The maximum can be +40%.
3 : T62US
The core bias LSB change timeout is set to 62 us minimum. The maximum can be +40%.
4 : T83US
The core bias LSB change timeout is set to 83 us minimum. The maximum can be +40%.
5 : T104US
The core bias LSB change timeout is set to 104 us minimum. The maximum can be +40%.
6 : T125US
The core bias LSB change timeout is set to 125 us minimum. The maximum can be +40%.
7 : T166US
The core bias LSB change timeout is set to 166 us minimum. The maximum can be +40%.
8 : T208US
The core bias LSB change timeout is set to 208 us minimum. The maximum can be +40%.
9 : T250US
The core bias LSB change timeout is set to 250 us minimum. The maximum can be +40%.
10 : T333US
The core bias LSB change timeout is set to 333 us minimum. The maximum can be +40%.
11 : T416US
The core bias LSB change timeout is set to 416 us minimum. The maximum can be +40%.
12 : T833US
The core bias LSB change timeout is set to 833 us minimum. The maximum can be +40%.
13 : T1250US
The core bias LSB change timeout is set to 1250 us minimum. The maximum can be +40%.
14 : T2083US
The core bias LSB change timeout is set to 2083 us minimum. The maximum can be +40%.
15 : T3750US
The core bias LSB change timeout is set to 3750 us minimum. The maximum can be +40%.
End of enumeration elements list.
No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COREBIASANA : Core Bias Current
bits : 0 - 7 (8 bit)
access : read-write
CTUNEXIANA : Tuning Capacitance on XI
bits : 8 - 15 (8 bit)
access : read-write
CTUNEXOANA : Tuning Capacitance on XO
bits : 16 - 23 (8 bit)
access : read-write
CTUNEFIXANA : Fixed Tuning Capacitance
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : NONE
Remove fixed capacitance on XI and XO nodes
1 : XI
Adds fixed capacitance on XI node
2 : XO
Adds fixed capacitance on XO node
3 : BOTH
Adds fixed capacitance on both XI and XO nodes
End of enumeration elements list.
COREDGENANA : Core Degeneration
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : NONE
Do not apply core degeneration resistence
1 : DGEN33
Apply 33 ohm core degeneration resistence
2 : DGEN50
Apply 50 ohm core degeneration resistence
3 : DGEN100
Apply 100 ohm core degeneration resistence
End of enumeration elements list.
SKIPCOREBIASOPT : Skip Core Bias Optimization
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTUNEXIBUFOUTANA : BUFOUT Tuning Capacitance on XI
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Crystal Oscillator Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : XTAL
crystal oscillator
1 : EXTCLK
external sinusoidal clock can be supplied on XI pin.
2 : EXTCLKPKDET
external sinusoidal clock can be supplied on XI pin (peak detector used).
End of enumeration elements list.
ENXIDCBIASANA : Enable XI Internal DC Bias
bits : 2 - 2 (1 bit)
access : read-write
SQBUFSCHTRGANA : Squaring Buffer Schmitt Trigger
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Squaring buffer schmitt trigger is disabled
1 : ENABLE
Squaring buffer schmitt trigger is enabled
End of enumeration elements list.
FORCELFTIMEOUT : Force Low Frequency Timeout
bits : 28 - 28 (1 bit)
access : read-write
No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFOUTFREEZE : Freeze BUFOUT Controls
bits : 0 - 0 (1 bit)
access : read-write
KEEPWARM : Keep Warm
bits : 2 - 2 (1 bit)
access : read-write
EM23ONDEMAND : On-demand During EM23
bits : 3 - 3 (1 bit)
access : read-write
FORCEXI2GNDANA : Force XI Pin to Ground
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled (not pulled)
1 : ENABLE
Enabled (pulled)
End of enumeration elements list.
FORCEXO2GNDANA : Force XO Pin to Ground
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled (not pulled)
1 : ENABLE
Enabled (pulled)
End of enumeration elements list.
FORCECTUNEMAX : Force Tuning Cap to Max Value
bits : 6 - 6 (1 bit)
access : read-write
PRSSTATUSSEL0 : PRS Status 0 Output Select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : DISABLED
PRS mux outputs 0
1 : ENS
PRS mux outputs enabled status
2 : COREBIASOPTRDY
PRS mux outputs core bias optimization ready status
3 : RDY
PRS mux outputs ready status
4 : PRSRDY
PRS mux outputs PRS ready status
5 : BUFOUTRDY
PRS mux outputs BUFOUT ready status
8 : HWREQ
PRS mux outputs oscillator requested by digital clock status
9 : PRSHWREQ
PRS mux outputs oscillator requested by PRS request status
10 : BUFOUTHWREQ
PRS mux outputs oscillator requested by BUFOUT request status
End of enumeration elements list.
PRSSTATUSSEL1 : PRS Status 1 Output Select
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : DISABLED
PRS mux outputs 0
1 : ENS
PRS mux outputs enabled status
2 : COREBIASOPTRDY
PRS mux outputs core bias optimization ready status
3 : RDY
PRS mux outputs ready status
4 : PRSRDY
PRS mux outputs PRS ready status
5 : BUFOUTRDY
PRS mux outputs BUFOUT ready status
8 : HWREQ
PRS mux outputs oscillator requested by digital clock status
9 : PRSHWREQ
PRS mux outputs oscillator requested by PRS request status
10 : BUFOUTHWREQ
PRS mux outputs oscillator requested by BUFOUT request status
End of enumeration elements list.
FORCEEN : Force Digital Clock Request
bits : 16 - 16 (1 bit)
access : read-write
FORCEENPRS : Force PRS Oscillator Request
bits : 17 - 17 (1 bit)
access : read-write
FORCEENBUFOUT : Force BUFOUT Request
bits : 18 - 18 (1 bit)
access : read-write
DISONDEMAND : Disable On-demand For Digital Clock
bits : 24 - 24 (1 bit)
access : read-write
DISONDEMANDPRS : Disable On-demand For PRS
bits : 25 - 25 (1 bit)
access : read-write
DISONDEMANDBUFOUT : Disable On-demand For BUFOUT
bits : 26 - 26 (1 bit)
access : read-write
No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRTRIMANA : BUFOUT Reference Trim
bits : 0 - 3 (4 bit)
access : read-write
No Description
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XOUTBIASANA : Driver Bias Current
bits : 0 - 3 (4 bit)
access : read-write
XOUTCFANA : Buffer Gain
bits : 4 - 7 (4 bit)
access : read-write
XOUTGMANA :
bits : 8 - 11 (4 bit)
access : read-write
PEAKDETTHRESANA : Peak Detector Threshold for XOUT
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : V105MV
1 : V132MV
2 : V157MV
3 : V184MV
4 : V210MV
5 : V236MV
6 : V262MV
7 : V289MV
8 : V315MV
9 : V341MV
10 : V367MV
11 : V394MV
12 : V420MV
13 : V446MV
14 : V472MV
15 : V499MV
End of enumeration elements list.
TIMEOUTCTUNE : Tuning Cap Change Timeout
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : T2US
The tuning cap change timeout is set to 2 us minimum. The maximum can be +40%.
1 : T5US
The tuning cap change timeout is set to 5 us minimum. The maximum can be +40%.
2 : T10US
The tuning cap change timeout is set to 10 us minimum. The maximum can be +40%.
3 : T16US
The tuning cap change timeout is set to 16 us minimum. The maximum can be +40%.
4 : T21US
The tuning cap change timeout is set to 21 us minimum. The maximum can be +40%.
5 : T26US
The tuning cap change timeout is set to 26 us minimum. The maximum can be +40%.
6 : T31US
The tuning cap change timeout is set to 31 us minimum. The maximum can be +40%.
7 : T42US
The tuning cap change timeout is set to 42 us minimum. The maximum can be +40%.
8 : T52US
The tuning cap change timeout is set to 52 us minimum. The maximum can be +40%.
9 : T63US
The tuning cap change timeout is set to 63 us minimum. The maximum can be +40%.
10 : T83US
The tuning cap change timeout is set to 83 us minimum. The maximum can be +40%.
11 : T104US
The tuning cap change timeout is set to 104 us minimum. The maximum can be +40%.
12 : T208US
The tuning cap change timeout is set to 208 us minimum. The maximum can be +40%.
13 : T313US
The tuning cap change timeout is set to 313 us minimum. The maximum can be +40%.
14 : T521US
The tuning cap change timeout is set to 521 us minimum. The maximum can be +40%.
15 : T938US
The tuning cap change timeout is set to 938 us minimum. The maximum can be +40%.
End of enumeration elements list.
TIMEOUTSTARTUP : Oscillator Startup Timeout
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0 : T42US
The oscillator startup timeout is set to 42 us minimum. The maximum can be +40%.
1 : T83US
The oscillator startup timeout is set to 83 us minimum. The maximum can be +40%.
2 : T108US
The oscillator startup timeout is set to 108 us minimum. The maximum can be +40%.
3 : T133US
The oscillator startup timeout is set to 133 us minimum. The maximum can be +40%.
4 : T158US
The oscillator startup timeout is set to 158 us minimum. The maximum can be +40%.
5 : T183US
The oscillator startup timeout is set to 183 us minimum. The maximum can be +40%.
6 : T208US
The oscillator startup timeout is set to 208 us minimum. The maximum can be +40%.
7 : T233US
The oscillator startup timeout is set to 233 us minimum. The maximum can be +40%.
8 : T258US
The oscillator startup timeout is set to 258 us minimum. The maximum can be +40%.
9 : T283US
The oscillator startup timeout is set to 283 us minimum. The maximum can be +40%.
10 : T333US
The oscillator startup timeout is set to 333 us minimum. The maximum can be +40%.
11 : T375US
The oscillator startup timeout is set to 375 us minimum. The maximum can be +40%.
12 : T417US
The oscillator startup timeout is set to 417 us minimum. The maximum can be +40%.
13 : T458US
The oscillator startup timeout is set to 458 us minimum. The maximum can be +40%.
14 : T500US
The oscillator startup timeout is set to 500 us minimum. The maximum can be +40%.
15 : T667US
The oscillator startup timeout is set to 667 us minimum. The maximum can be +40%.
End of enumeration elements list.
MINIMUMSTARTUPDELAY : Minimum Startup Delay
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COREBIASOPT : Core Bias Optimizaton
bits : 0 - 0 (1 bit)
access : write-only
No Description
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDY : Ready Status
bits : 0 - 0 (1 bit)
access : read-only
COREBIASOPTRDY : Core Bias Optimization Ready
bits : 1 - 1 (1 bit)
access : read-only
PRSRDY : PRS Ready Status
bits : 2 - 2 (1 bit)
access : read-only
BUFOUTRDY : BUFOUT Ready Status
bits : 3 - 3 (1 bit)
access : read-only
BUFOUTFROZEN : BUFOUT Frozen
bits : 15 - 15 (1 bit)
access : read-only
ENS : Enabled Status
bits : 16 - 16 (1 bit)
access : read-only
HWREQ : Oscillator Requested by Digital Clock
bits : 17 - 17 (1 bit)
access : read-only
ISWARM : Oscillator Is Kept Warm
bits : 19 - 19 (1 bit)
access : read-only
PRSHWREQ : Oscillator Requested by PRS Request
bits : 20 - 20 (1 bit)
access : read-only
BUFOUTHWREQ : Oscillator Requested by BUFOUT Request
bits : 21 - 21 (1 bit)
access : read-only
SYNCBUSY : Sync Busy
bits : 30 - 30 (1 bit)
access : read-only
LOCK : Configuration Lock Status
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : UNLOCKED
Configuration lock is unlocked
1 : LOCKED
Configuration lock is locked
End of enumeration elements list.
No Description
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDY : Digital Clock Ready Interrupt
bits : 0 - 0 (1 bit)
access : read-write
COREBIASOPTRDY : Core Bias Optimization Ready Interrupt
bits : 1 - 1 (1 bit)
access : read-write
PRSRDY : PRS Ready Interrupt
bits : 2 - 2 (1 bit)
access : read-write
BUFOUTRDY : BUFOUT Ready Interrupt
bits : 3 - 3 (1 bit)
access : read-write
BUFOUTFROZEN : BUFOUT FROZEN Interrupt
bits : 15 - 15 (1 bit)
access : read-write
PRSERR : PRS Requset Error Interrupt
bits : 20 - 20 (1 bit)
access : read-write
BUFOUTERR : BUFOUT Request Error Interrupt
bits : 21 - 21 (1 bit)
access : read-write
BUFOUTFREEZEERR : BUFOUT Freeze Error Interrupt
bits : 27 - 27 (1 bit)
access : read-write
BUFOUTDNSERR : BUFOUT Did Not Start Error Interrupt
bits : 28 - 28 (1 bit)
access : read-write
DNSERR : Did Not Start Error Interrupt
bits : 29 - 29 (1 bit)
access : read-write
LFTIMEOUTERR : Low Frequency Timeout Error Interrupt
bits : 30 - 30 (1 bit)
access : read-write
COREBIASOPTERR : Core Bias Optimization Error Interrupt
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDY : Digital Clock Ready Interrupt
bits : 0 - 0 (1 bit)
access : read-write
COREBIASOPTRDY : Core Bias Optimization Ready Interrupt
bits : 1 - 1 (1 bit)
access : read-write
PRSRDY : PRS Ready Interrupt
bits : 2 - 2 (1 bit)
access : read-write
BUFOUTRDY : BUFOUT Ready Interrupt
bits : 3 - 3 (1 bit)
access : read-write
BUFOUTFROZEN : BUFOUT FROZEN Interrupt
bits : 15 - 15 (1 bit)
access : read-write
PRSERR : PRS Requset Error Interrupt
bits : 20 - 20 (1 bit)
access : read-write
BUFOUTERR : BUFOUT Request Error Interrupt
bits : 21 - 21 (1 bit)
access : read-write
BUFOUTFREEZEERR : BUFOUT Freeze Error Interrupt
bits : 27 - 27 (1 bit)
access : read-write
BUFOUTDNSERR : BUFOUT Did Not Start Error Interrupt
bits : 28 - 28 (1 bit)
access : read-write
DNSERR : Did Not Start Error Interrupt
bits : 29 - 29 (1 bit)
access : read-write
LFTIMEOUTERR : Low Frequency Timeout Error Interrupt
bits : 30 - 30 (1 bit)
access : read-write
COREBIASOPTERR : Core Bias Optimization Error Interrupt
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LOCKKEY : Configuration Lock Key
bits : 0 - 15 (16 bit)
access : write-only
Enumeration:
22542 : UNLOCK
Write this value to unlock
End of enumeration elements list.
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