Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP Version
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFMODE : Buffer Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SINGLE
Single buffer is used
1 : DUAL
Dual buffers are used
End of enumeration elements list.
QCHANNELMODE : Q-Channel Mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ACCEPT
ECA immediately stops current operation and asserts QACCEPTn after completing the last outstanding DMA bus transaction
1 : DENY
ECA responds to any QREQn request with a QDENY response if ECA is active currenly
End of enumeration elements list.
No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUNMODE : Run Mode
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : DISABLED
ECA is disabled
1 : CAPTURE
Capture mode is running
2 : PLAYBACK
Playback mode is running
End of enumeration elements list.
SYNCBUSY : Sync Busy
bits : 2 - 2 (1 bit)
access : read-only
EVENTCNTRSTARTED : Event Counter Started
bits : 3 - 3 (1 bit)
access : read-only
No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUF0WMIND : BUF0 Watermark Indication
bits : 0 - 0 (1 bit)
access : read-write
BUF1WMIND : BUF1 Watermark Indication
bits : 1 - 1 (1 bit)
access : read-write
BUF0FULLIND : BUF0 Full Indication
bits : 2 - 2 (1 bit)
access : read-write
BUF1FULLIND : BUF1 Full Indication
bits : 3 - 3 (1 bit)
access : read-write
STARTTRIG : Start Trigger
bits : 4 - 4 (1 bit)
access : read-write
STOPTRIG : Stop Trigger
bits : 5 - 5 (1 bit)
access : read-write
CAPTURESTART : Capture Start
bits : 6 - 6 (1 bit)
access : read-write
CAPTUREEND : Capture End
bits : 7 - 7 (1 bit)
access : read-write
PLAYBACKSTART : Playback Start
bits : 8 - 8 (1 bit)
access : read-write
PLAYBACKEND : Playback End
bits : 9 - 9 (1 bit)
access : read-write
EVENTCNTRCOMP : Event Counter Compare
bits : 10 - 10 (1 bit)
access : read-write
FIFOORERROR : FIFO Overrun Error
bits : 11 - 11 (1 bit)
access : read-write
FIFOURERROR : FIFO Underrun Error
bits : 12 - 12 (1 bit)
access : read-write
DMABUSERROR : DMA Bus Error
bits : 13 - 13 (1 bit)
access : read-write
No Description
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUF0WMIND : New BitField
bits : 0 - 0 (1 bit)
access : read-write
BUF1WMIND : New BitField
bits : 1 - 1 (1 bit)
access : read-write
BUF0FULLIND : New BitField
bits : 2 - 2 (1 bit)
access : read-write
BUF1FULLIND : New BitField
bits : 3 - 3 (1 bit)
access : read-write
STARTTRIG : New BitField
bits : 4 - 4 (1 bit)
access : read-write
STOPTRIG : New BitField
bits : 5 - 5 (1 bit)
access : read-write
CAPTURESTART : New BitField
bits : 6 - 6 (1 bit)
access : read-write
CAPTUREEND : New BitField
bits : 7 - 7 (1 bit)
access : read-write
PLAYBACKSTART : New BitField
bits : 8 - 8 (1 bit)
access : read-write
PLAYBACKEND : New BitField
bits : 9 - 9 (1 bit)
access : read-write
EVENTCNTRCOMP : New BitField
bits : 10 - 10 (1 bit)
access : read-write
FIFOORERROR : New BitField
bits : 11 - 11 (1 bit)
access : read-write
FIFOURERROR : New BitField
bits : 12 - 12 (1 bit)
access : read-write
DMABUSERROR : New BitField
bits : 13 - 13 (1 bit)
access : read-write
No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : DMA BUS ERROR ADDRESS
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : Base Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET : Limit Offset
bits : 2 - 18 (17 bit)
access : read-write
No Description
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET : Watermark Offset
bits : 2 - 18 (17 bit)
access : read-write
No Description
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : Base Address
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET : Limit Offset
bits : 2 - 18 (17 bit)
access : read-write
No Description
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET : Watermark Offset
bits : 2 - 18 (17 bit)
access : read-write
No Description
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATUS : Buffer Pointer Status
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Module Enable
bits : 0 - 0 (1 bit)
access : read-write
DISABLING : Disablement Busy Status
bits : 1 - 1 (1 bit)
access : read-only
No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRACESEL : Trace Select
bits : 0 - 2 (3 bit)
access : read-write
ENABLE : Enable
bits : 3 - 3 (1 bit)
access : read-write
COMBMODE : Combination Mode
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : AND
1 : OR
End of enumeration elements list.
No Description
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRACESEL : Trace Select
bits : 0 - 2 (3 bit)
access : read-write
ENABLE : Enable
bits : 3 - 3 (1 bit)
access : read-write
COMBMODE : Combination Mode
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : AND
1 : OR
End of enumeration elements list.
No Description
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENMASK : Enable Mask
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REDMASK : Rising Edge Mask
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEDMASK : Falling Edge Mask
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVL0MASK : Level 0 Mask
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVL1MASK : Level 1 Mask
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENMASK : Enable Mask
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REDMASK : Rising Edge Mask
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEDMASK : Falling Edge Mask
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVL0MASK : Level 0 Mask
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVL1MASK : Level 1 Mask
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRACESEL : Trace Select
bits : 0 - 7 (8 bit)
access : read-write
DATAWIDTH : Data Width
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : BIT1
1 bit
1 : BIT2
2 bits
2 : BIT4
4 bits
3 : BIT8
8 bits
4 : BIT16
16 bits
5 : BIT32
32 bits
End of enumeration elements list.
DATAROTATESIZE : Data Rotate Size
bits : 11 - 15 (5 bit)
access : read-write
STARTMODE : Start Mode
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : MANUAL
In this mode, setting CMD.MODE=CAPTURE would start the capture
1 : START_TRIGGER
In this mode, a start-trigger(via STARTTRIGCTRL) would start the capture
End of enumeration elements list.
STOPMODE : Stop Mode
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0 : CONTINUOUS
Capture will continue to occur until another mode is configured
1 : BUF_FULL
Capture will stop when the memory buffer is full. In this mode CAPTURESTOPDELAY has no effect
2 : STOP_TRIGGER
Capture will stop when the stop-trigger event occurs or optionally after a CAPTURESTOPDELAY number of cycles/capture-events if configured
3 : STOP_TRIGGER_FULL
Capture stops when either of the following conditions is met (in either of these conditions, CAPTURESTOPDELAY has no effect): BUF_FULL condition or STOP_TRIGGER condition
End of enumeration elements list.
COND : Condition
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : TIMED
Capture condition is based on the rate specified in CAPTURERATECTRL register within the active capture window
1 : START_TRIGGER
Capture condition is every start-trigger event in the active capture windo
2 : SLAVE
Capture condition is every cycle when cap_event_in input is high
End of enumeration elements list.
STOPCONDPRI : Stop Condition Priority
bits : 22 - 22 (1 bit)
access : read-write
WRITEDIS : Write Memory Disable
bits : 23 - 23 (1 bit)
access : read-write
DATAOUTEN : Port Interface Enable
bits : 24 - 24 (1 bit)
access : read-write
DATAOUTDSHIFT : Port Interface Shift
bits : 25 - 30 (6 bit)
access : read-write
No Description
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELAY : Start Delay
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELAY : Stop Delay
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RATE : Capture Rate
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset Command
bits : 0 - 0 (1 bit)
access : write-only
RESETTING : Software Reset Busy Status
bits : 1 - 1 (1 bit)
access : read-only
No Description
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Playback Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SINGLE
Playback starts at BUF0_BASE and stops at BUF1_BASE + BUF1_LIMITOFFSET
1 : LOOP
Playback starts at BUF0_BASE and loops/wraps continuously until CTRL.MODE != PLAYBACK (this can be supported in single or double-buffer modes)
End of enumeration elements list.
COND : Playback Condition
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : START_TRIGGER
Playback event occurs at every start-trigger event
1 : TIMED
Playback event occurs based on rate defined in PLAYBACL_RATE_CTRL
End of enumeration elements list.
DATAWIDTH : Playback Data Width
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : BIT1
1 bit
1 : BIT2
2 bits
2 : BIT4
4 bits
3 : BIT8
8 bits
4 : BIT16
16 bits
5 : BIT32
32 bits
End of enumeration elements list.
No Description
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RATE : Playback Rate
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTMODE : Start Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MANUAL
Counting starts as soon as ENABLE=1
1 : START_TRIGGER
Counting starts when the start-trigger event occurs
End of enumeration elements list.
STOPMODE : Stop Mode
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : MANUAL
When writing a 1, stops the counter advancing
1 : STOP_TRIGGER
When stop trigger is active, stops the counter advancing
2 : COMPARE
When the count reaches the value programmed in EVENTCNTRCOMPARE, stops the counter advancing
End of enumeration elements list.
COUNTMODE : Count Mode
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : ALWAYS
Increment on every clock cycle
1 : START_TRIGGER
Increment on every start-trigger event
2 : STOP_TRIGGER
Increment on every stop-trigger event
3 : ALL_TRIGGER
Increment on either every start- or stop-trigger event
End of enumeration elements list.
No Description
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPARE : Compare Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATUS : Event Count Value
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MODE : Running Mode
bits : 0 - 1 (2 bit)
access : write-only
Enumeration:
1 : DISABLED
Set to make ECA idle
2 : CAPTURE
Set to enable capture mode
3 : PLAYBACK
Set to enable playback mode
End of enumeration elements list.
STARTEVENTCNTR : Start Event Counter
bits : 2 - 2 (1 bit)
access : write-only
STOPEVENTCNTR : Stop Event Counter
bits : 3 - 3 (1 bit)
access : write-only
CLEAREVENTCNTR : Clear Event Counter
bits : 4 - 4 (1 bit)
access : write-only
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