\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
OTG_HS control and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRQSCS : Session request success
bits : 0 - 0 (1 bit)
access : read-only
SRQ : Session request
bits : 1 - 1 (1 bit)
access : read-write
HNGSCS : Host negotiation success
bits : 8 - 8 (1 bit)
access : read-only
HNPRQ : HNP request
bits : 9 - 9 (1 bit)
access : read-write
HSHNPEN : Host set HNP enable
bits : 10 - 10 (1 bit)
access : read-write
DHNPEN : Device HNP enabled
bits : 11 - 11 (1 bit)
access : read-write
CIDSTS : Connector ID status
bits : 16 - 16 (1 bit)
access : read-only
DBCT : Long/short debounce time
bits : 17 - 17 (1 bit)
access : read-only
ASVLD : A-session valid
bits : 18 - 18 (1 bit)
access : read-only
BSVLD : B-session valid
bits : 19 - 19 (1 bit)
access : read-only
OTG_HS reset register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSRST : Core soft reset
bits : 0 - 0 (1 bit)
access : read-write
HSRST : HCLK soft reset
bits : 1 - 1 (1 bit)
access : read-write
FCRST : Host frame counter reset
bits : 2 - 2 (1 bit)
access : read-write
RXFFLSH : RxFIFO flush
bits : 4 - 4 (1 bit)
access : read-write
TXFFLSH : TxFIFO flush
bits : 5 - 5 (1 bit)
access : read-write
TXFNUM : TxFIFO number
bits : 6 - 10 (5 bit)
access : read-write
DMAREQ : DMA request signal
bits : 30 - 30 (1 bit)
access : read-only
AHBIDL : AHB master idle
bits : 31 - 31 (1 bit)
access : read-only
OTG_HS Host periodic transmit FIFO size register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTXSA : Host periodic TxFIFO start address
bits : 0 - 15 (16 bit)
PTXFD : Host periodic TxFIFO depth
bits : 16 - 31 (16 bit)
OTG_HS device IN endpoint transmit FIFO size register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPTXSA : IN endpoint FIFOx transmit RAM start address
bits : 0 - 15 (16 bit)
INEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)
OTG_HS device IN endpoint transmit FIFO size register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPTXSA : IN endpoint FIFOx transmit RAM start address
bits : 0 - 15 (16 bit)
INEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)
OTG_HS device IN endpoint transmit FIFO size register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPTXSA : IN endpoint FIFOx transmit RAM start address
bits : 0 - 15 (16 bit)
INEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)
OTG_HS device IN endpoint transmit FIFO size register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPTXSA : IN endpoint FIFOx transmit RAM start address
bits : 0 - 15 (16 bit)
INEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)
OTG_HS device IN endpoint transmit FIFO size register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPTXSA : IN endpoint FIFOx transmit RAM start address
bits : 0 - 15 (16 bit)
INEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)
OTG_HS device IN endpoint transmit FIFO size register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPTXSA : IN endpoint FIFOx transmit RAM start address
bits : 0 - 15 (16 bit)
INEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)
OTG_HS device IN endpoint transmit FIFO size register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPTXSA : IN endpoint FIFOx transmit RAM start address
bits : 0 - 15 (16 bit)
INEPTXFD : IN endpoint TxFIFO depth
bits : 16 - 31 (16 bit)
OTG_HS core interrupt register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMOD : Current mode of operation
bits : 0 - 0 (1 bit)
access : read-only
MMIS : Mode mismatch interrupt
bits : 1 - 1 (1 bit)
access : read-write
OTGINT : OTG interrupt
bits : 2 - 2 (1 bit)
access : read-only
SOF : Start of frame
bits : 3 - 3 (1 bit)
access : read-write
RXFLVL : RxFIFO nonempty
bits : 4 - 4 (1 bit)
access : read-only
NPTXFE : Nonperiodic TxFIFO empty
bits : 5 - 5 (1 bit)
access : read-only
GINAKEFF : Global IN nonperiodic NAK effective
bits : 6 - 6 (1 bit)
access : read-only
BOUTNAKEFF : Global OUT NAK effective
bits : 7 - 7 (1 bit)
access : read-only
ESUSP : Early suspend
bits : 10 - 10 (1 bit)
access : read-write
USBSUSP : USB suspend
bits : 11 - 11 (1 bit)
access : read-write
USBRST : USB reset
bits : 12 - 12 (1 bit)
access : read-write
ENUMDNE : Enumeration done
bits : 13 - 13 (1 bit)
access : read-write
ISOODRP : Isochronous OUT packet dropped interrupt
bits : 14 - 14 (1 bit)
access : read-write
EOPF : End of periodic frame interrupt
bits : 15 - 15 (1 bit)
access : read-write
IEPINT : IN endpoint interrupt
bits : 18 - 18 (1 bit)
access : read-only
OEPINT : OUT endpoint interrupt
bits : 19 - 19 (1 bit)
access : read-only
IISOIXFR : Incomplete isochronous IN transfer
bits : 20 - 20 (1 bit)
access : read-write
PXFR_INCOMPISOOUT : Incomplete periodic transfer
bits : 21 - 21 (1 bit)
access : read-write
DATAFSUSP : Data fetch suspended
bits : 22 - 22 (1 bit)
access : read-write
HPRTINT : Host port interrupt
bits : 24 - 24 (1 bit)
access : read-only
HCINT : Host channels interrupt
bits : 25 - 25 (1 bit)
access : read-only
PTXFE : Periodic TxFIFO empty
bits : 26 - 26 (1 bit)
access : read-only
CIDSCHG : Connector ID status change
bits : 28 - 28 (1 bit)
access : read-write
DISCINT : Disconnect detected interrupt
bits : 29 - 29 (1 bit)
access : read-write
SRQINT : Session request/new session detected interrupt
bits : 30 - 30 (1 bit)
access : read-write
WKUINT : Resume/remote wakeup detected interrupt
bits : 31 - 31 (1 bit)
access : read-write
OTG_HS interrupt mask register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MMISM : Mode mismatch interrupt mask
bits : 1 - 1 (1 bit)
access : read-write
OTGINT : OTG interrupt mask
bits : 2 - 2 (1 bit)
access : read-write
SOFM : Start of frame mask
bits : 3 - 3 (1 bit)
access : read-write
RXFLVLM : Receive FIFO nonempty mask
bits : 4 - 4 (1 bit)
access : read-write
NPTXFEM : Nonperiodic TxFIFO empty mask
bits : 5 - 5 (1 bit)
access : read-write
GINAKEFFM : Global nonperiodic IN NAK effective mask
bits : 6 - 6 (1 bit)
access : read-write
GONAKEFFM : Global OUT NAK effective mask
bits : 7 - 7 (1 bit)
access : read-write
ESUSPM : Early suspend mask
bits : 10 - 10 (1 bit)
access : read-write
USBSUSPM : USB suspend mask
bits : 11 - 11 (1 bit)
access : read-write
USBRST : USB reset mask
bits : 12 - 12 (1 bit)
access : read-write
ENUMDNEM : Enumeration done mask
bits : 13 - 13 (1 bit)
access : read-write
ISOODRPM : Isochronous OUT packet dropped interrupt mask
bits : 14 - 14 (1 bit)
access : read-write
EOPFM : End of periodic frame interrupt mask
bits : 15 - 15 (1 bit)
access : read-write
EPMISM : Endpoint mismatch interrupt mask
bits : 17 - 17 (1 bit)
access : read-write
IEPINT : IN endpoints interrupt mask
bits : 18 - 18 (1 bit)
access : read-write
OEPINT : OUT endpoints interrupt mask
bits : 19 - 19 (1 bit)
access : read-write
IISOIXFRM : Incomplete isochronous IN transfer mask
bits : 20 - 20 (1 bit)
access : read-write
PXFRM_IISOOXFRM : Incomplete periodic transfer mask
bits : 21 - 21 (1 bit)
access : read-write
FSUSPM : Data fetch suspended mask
bits : 22 - 22 (1 bit)
access : read-write
PRTIM : Host port interrupt mask
bits : 24 - 24 (1 bit)
access : read-only
HCIM : Host channels interrupt mask
bits : 25 - 25 (1 bit)
access : read-write
PTXFEM : Periodic TxFIFO empty mask
bits : 26 - 26 (1 bit)
access : read-write
CIDSCHGM : Connector ID status change mask
bits : 28 - 28 (1 bit)
access : read-write
DISCINT : Disconnect detected interrupt mask
bits : 29 - 29 (1 bit)
access : read-write
SRQIM : Session request/new session detected interrupt mask
bits : 30 - 30 (1 bit)
access : read-write
WUIM : Resume/remote wakeup detected interrupt mask
bits : 31 - 31 (1 bit)
access : read-write
OTG_HS Receive status debug read register (host mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHNUM : Channel number
bits : 0 - 3 (4 bit)
BCNT : Byte count
bits : 4 - 14 (11 bit)
DPID : Data PID
bits : 15 - 16 (2 bit)
PKTSTS : Packet status
bits : 17 - 20 (4 bit)
OTG_HS Receive status debug read register (peripheral mode mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : OTG_HS_GRXSTSR_Host
reset_Mask : 0x0
EPNUM : Endpoint number
bits : 0 - 3 (4 bit)
BCNT : Byte count
bits : 4 - 14 (11 bit)
DPID : Data PID
bits : 15 - 16 (2 bit)
PKTSTS : Packet status
bits : 17 - 20 (4 bit)
FRMNUM : Frame number
bits : 21 - 24 (4 bit)
OTG_HS status read and pop register (host mode)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHNUM : Channel number
bits : 0 - 3 (4 bit)
BCNT : Byte count
bits : 4 - 14 (11 bit)
DPID : Data PID
bits : 15 - 16 (2 bit)
PKTSTS : Packet status
bits : 17 - 20 (4 bit)
OTG_HS status read and pop register (peripheral mode)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : OTG_HS_GRXSTSP_Host
reset_Mask : 0x0
EPNUM : Endpoint number
bits : 0 - 3 (4 bit)
BCNT : Byte count
bits : 4 - 14 (11 bit)
DPID : Data PID
bits : 15 - 16 (2 bit)
PKTSTS : Packet status
bits : 17 - 20 (4 bit)
FRMNUM : Frame number
bits : 21 - 24 (4 bit)
OTG_HS Receive FIFO size register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFD : RxFIFO depth
bits : 0 - 15 (16 bit)
OTG_HS nonperiodic transmit FIFO size register (host mode)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NPTXFSA : Nonperiodic transmit RAM start address
bits : 0 - 15 (16 bit)
NPTXFD : Nonperiodic TxFIFO depth
bits : 16 - 31 (16 bit)
Endpoint 0 transmit FIFO size (peripheral mode)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : OTG_HS_GNPTXFSIZ_Host
reset_Mask : 0x0
TX0FSA : Endpoint 0 transmit RAM start address
bits : 0 - 15 (16 bit)
TX0FD : Endpoint 0 TxFIFO depth
bits : 16 - 31 (16 bit)
OTG_HS nonperiodic transmit FIFO/queue status register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NPTXFSAV : Nonperiodic TxFIFO space available
bits : 0 - 15 (16 bit)
NPTQXSAV : Nonperiodic transmit request queue space available
bits : 16 - 23 (8 bit)
NPTXQTOP : Top of the nonperiodic transmit request queue
bits : 24 - 30 (7 bit)
OTG_HS general core configuration register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWRDWN : Power down
bits : 16 - 16 (1 bit)
I2CPADEN : Enable I2C bus connection for the external I2C PHY interface
bits : 17 - 17 (1 bit)
VBUSASEN : Enable the VBUS sensing device
bits : 18 - 18 (1 bit)
VBUSBSEN : Enable the VBUS sensing device
bits : 19 - 19 (1 bit)
SOFOUTEN : SOF output enable
bits : 20 - 20 (1 bit)
NOVBUSSENS : VBUS sensing disable option
bits : 21 - 21 (1 bit)
OTG_HS core ID register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRODUCT_ID : Product ID field
bits : 0 - 31 (32 bit)
OTG_HS interrupt register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEDET : Session end detected
bits : 2 - 2 (1 bit)
SRSSCHG : Session request success status change
bits : 8 - 8 (1 bit)
HNSSCHG : Host negotiation success status change
bits : 9 - 9 (1 bit)
HNGDET : Host negotiation detected
bits : 17 - 17 (1 bit)
ADTOCHG : A-device timeout change
bits : 18 - 18 (1 bit)
DBCDNE : Debounce done
bits : 19 - 19 (1 bit)
OTG_HS AHB configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GINT : Global interrupt mask
bits : 0 - 0 (1 bit)
HBSTLEN : Burst length/type
bits : 1 - 4 (4 bit)
DMAEN : DMA enable
bits : 5 - 5 (1 bit)
TXFELVL : TxFIFO empty level
bits : 7 - 7 (1 bit)
PTXFELVL : Periodic TxFIFO empty level
bits : 8 - 8 (1 bit)
OTG_HS USB configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOCAL : FS timeout calibration
bits : 0 - 2 (3 bit)
access : read-write
PHYSEL : USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
bits : 6 - 6 (1 bit)
access : write-only
SRPCAP : SRP-capable
bits : 8 - 8 (1 bit)
access : read-write
HNPCAP : HNP-capable
bits : 9 - 9 (1 bit)
access : read-write
TRDT : USB turnaround time
bits : 10 - 13 (4 bit)
access : read-write
PHYLPCS : PHY Low-power clock select
bits : 15 - 15 (1 bit)
access : read-write
ULPIFSLS : ULPI FS/LS select
bits : 17 - 17 (1 bit)
access : read-write
ULPIAR : ULPI Auto-resume
bits : 18 - 18 (1 bit)
access : read-write
ULPICSM : ULPI Clock SuspendM
bits : 19 - 19 (1 bit)
access : read-write
ULPIEVBUSD : ULPI External VBUS Drive
bits : 20 - 20 (1 bit)
access : read-write
ULPIEVBUSI : ULPI external VBUS indicator
bits : 21 - 21 (1 bit)
access : read-write
TSDPS : TermSel DLine pulsing selection
bits : 22 - 22 (1 bit)
access : read-write
PCCI : Indicator complement
bits : 23 - 23 (1 bit)
access : read-write
PTCI : Indicator pass through
bits : 24 - 24 (1 bit)
access : read-write
ULPIIPD : ULPI interface protect disable
bits : 25 - 25 (1 bit)
access : read-write
FHMOD : Forced host mode
bits : 29 - 29 (1 bit)
access : read-write
FDMOD : Forced peripheral mode
bits : 30 - 30 (1 bit)
access : read-write
CTXPKT : Corrupt Tx packet
bits : 31 - 31 (1 bit)
access : read-write
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