\n

PRS_S

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

IPVERSION

ASYNC_PEEK

CONSUMER_RAC_RXEN

CONSUMER_RAC_TXEN

CONSUMER_SETAMPER_TAMPERSRC25

CONSUMER_SETAMPER_TAMPERSRC26

CONSUMER_SETAMPER_TAMPERSRC27

CONSUMER_SETAMPER_TAMPERSRC28

CONSUMER_SETAMPER_TAMPERSRC29

CONSUMER_SETAMPER_TAMPERSRC30

CONSUMER_SETAMPER_TAMPERSRC31

CONSUMER_SYSRTC0_IN0

CONSUMER_SYSRTC0_IN1

CONSUMER_HFXO0_OSCREQ

CONSUMER_HFXO0_TIMEOUT

CONSUMER_CORE_CTIIN0

CONSUMER_CORE_CTIIN1

CONSUMER_CORE_CTIIN2

SYNC_PEEK

CONSUMER_CORE_CTIIN3

CONSUMER_CORE_M33RXEV

CONSUMER_TIMER0_CC0

CONSUMER_TIMER0_CC1

CONSUMER_TIMER0_CC2

CONSUMER_TIMER0_DTI

CONSUMER_TIMER0_DTIFS1

CONSUMER_TIMER0_DTIFS2

CONSUMER_TIMER1_CC0

CONSUMER_TIMER1_CC1

CONSUMER_TIMER1_CC2

CONSUMER_TIMER1_DTI

CONSUMER_TIMER1_DTIFS1

CONSUMER_TIMER1_DTIFS2

CONSUMER_TIMER2_CC0

CONSUMER_TIMER2_CC1

ASYNC_CH0_CTRL

CONSUMER_TIMER2_CC2

CONSUMER_TIMER2_DTI

CONSUMER_TIMER2_DTIFS1

CONSUMER_TIMER2_DTIFS2

CONSUMER_TIMER3_CC0

CONSUMER_TIMER3_CC1

CONSUMER_TIMER3_CC2

CONSUMER_TIMER3_DTI

CONSUMER_TIMER3_DTIFS1

CONSUMER_TIMER3_DTIFS2

CONSUMER_TIMER4_CC0

CONSUMER_TIMER4_CC1

CONSUMER_TIMER4_CC2

CONSUMER_TIMER4_DTI

CONSUMER_TIMER4_DTIFS1

CONSUMER_TIMER4_DTIFS2

ASYNC_CH1_CTRL

CONSUMER_USART0_CLK

CONSUMER_USART0_IR

CONSUMER_USART0_RX

CONSUMER_USART0_TRIGGER

CONSUMER_VDAC0_ASYNCTRIGCH0

CONSUMER_VDAC0_ASYNCTRIGCH1

CONSUMER_VDAC0_SYNCTRIGCH0

CONSUMER_VDAC0_SYNCTRIGCH1

CONSUMER_VDAC1_ASYNCTRIGCH0

CONSUMER_VDAC1_ASYNCTRIGCH1

CONSUMER_VDAC1_SYNCTRIGCH0

CONSUMER_VDAC1_SYNCTRIGCH1

CONSUMER_WDOG0_SRC0

ASYNC_CH2_CTRL

CONSUMER_WDOG0_SRC1

CONSUMER_WDOG1_SRC0

CONSUMER_WDOG1_SRC1

RPURATD0

RPURATD1

RPURATD2

RPURATD3

RPURATD4

ASYNC_CH3_CTRL

ASYNC_CH4_CTRL

ASYNC_CH5_CTRL

ASYNC_CH6_CTRL

ASYNC_CH7_CTRL

ASYNC_CH8_CTRL

ASYNC_CH9_CTRL

ASYNC_CH10_CTRL

ASYNC_CH11_CTRL

ASYNC_CH12_CTRL

ASYNC_CH13_CTRL

ASYNC_CH14_CTRL

ASYNC_CH15_CTRL

SYNC_CH0_CTRL

SYNC_CH1_CTRL

SYNC_CH2_CTRL

SYNC_CH3_CTRL

CONSUMER_CMU_CALDN

CONSUMER_CMU_CALUP

CONSUMER_EUSART0_CLK

CONSUMER_EUSART0_RX

CONSUMER_EUSART0_TRIGGER

CONSUMER_EUSART1_CLK

ASYNC_SWPULSE

CONSUMER_EUSART1_RX

CONSUMER_EUSART1_TRIGGER

CONSUMER_FRC_RXRAW

CONSUMER_IADC0_SCANTRIGGER

CONSUMER_IADC0_SINGLETRIGGER

CONSUMER_LDMAXBAR_DMAREQ0

CONSUMER_LDMAXBAR_DMAREQ1

CONSUMER_LETIMER0_CLEAR

CONSUMER_LETIMER0_START

CONSUMER_LETIMER0_STOP

CONSUMER_MODEM_DIN

CONSUMER_MODEM_PAEN

CONSUMER_PCNT0_S0IN

CONSUMER_PCNT0_S1IN

CONSUMER_PROTIMER_CC0

CONSUMER_PROTIMER_CC1

ASYNC_SWLEVEL

CONSUMER_PROTIMER_CC2

CONSUMER_PROTIMER_CC3

CONSUMER_PROTIMER_CC4

CONSUMER_PROTIMER_LBTPAUSE

CONSUMER_PROTIMER_LBTSTART

CONSUMER_PROTIMER_LBTSTOP

CONSUMER_PROTIMER_RTCCTRIGGER

CONSUMER_PROTIMER_START

CONSUMER_PROTIMER_STOP

CONSUMER_RAC_CLR

CONSUMER_RAC_CTIIN0

CONSUMER_RAC_CTIIN1

CONSUMER_RAC_CTIIN2

CONSUMER_RAC_CTIIN3

CONSUMER_RAC_FORCETX

CONSUMER_RAC_RXDIS


IPVERSION

No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : New BitField
bits : 0 - 31 (32 bit)
access : read-only


ASYNC_PEEK

No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ASYNC_PEEK ASYNC_PEEK read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0VAL CH1VAL CH2VAL CH3VAL CH4VAL CH5VAL CH6VAL CH7VAL CH8VAL CH9VAL CH10VAL CH11VAL CH12VAL CH13VAL CH14VAL CH15VAL

CH0VAL : Channel 0 Current Value
bits : 0 - 0 (1 bit)
access : read-only

CH1VAL : Channel 1 Current Value
bits : 1 - 1 (1 bit)
access : read-only

CH2VAL : Channel 2 Current Value
bits : 2 - 2 (1 bit)
access : read-only

CH3VAL : Channel 3 Current Value
bits : 3 - 3 (1 bit)
access : read-only

CH4VAL : Channel 4 Current Value
bits : 4 - 4 (1 bit)
access : read-only

CH5VAL : Channel 5 Current Value
bits : 5 - 5 (1 bit)
access : read-only

CH6VAL : Channel 6 Current Value
bits : 6 - 6 (1 bit)
access : read-only

CH7VAL : Channel 7 Current Value
bits : 7 - 7 (1 bit)
access : read-only

CH8VAL : Channel 8 Current Value
bits : 8 - 8 (1 bit)
access : read-only

CH9VAL : Channel 9 Current Value
bits : 9 - 9 (1 bit)
access : read-only

CH10VAL : Channel 10 Current Value
bits : 10 - 10 (1 bit)
access : read-only

CH11VAL : Channel 11 Current Value
bits : 11 - 11 (1 bit)
access : read-only

CH12VAL : Channel 12 Current Value
bits : 12 - 12 (1 bit)
access : read-only

CH13VAL : Channel 13 current value
bits : 13 - 13 (1 bit)
access : read-only

CH14VAL : Channel 14 current value
bits : 14 - 14 (1 bit)
access : read-only

CH15VAL : Channel 15 current value
bits : 15 - 15 (1 bit)
access : read-only


CONSUMER_RAC_RXEN

RXEN Consumer register
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RAC_RXEN CONSUMER_RAC_RXEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : RXEN async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_RAC_TXEN

TXEN Consumer register
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RAC_TXEN CONSUMER_RAC_TXEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : TXEN async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SETAMPER_TAMPERSRC25

TAMPERSRC25 consumer register
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SETAMPER_TAMPERSRC25 CONSUMER_SETAMPER_TAMPERSRC25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : TAMPERSRC25 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SETAMPER_TAMPERSRC26

TAMPERSRC26 Consumer register
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SETAMPER_TAMPERSRC26 CONSUMER_SETAMPER_TAMPERSRC26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : TAMPERSRC26 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SETAMPER_TAMPERSRC27

TAMPERSRC27 Consumer register
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SETAMPER_TAMPERSRC27 CONSUMER_SETAMPER_TAMPERSRC27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : TAMPERSRC27 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SETAMPER_TAMPERSRC28

TAMPERSRC28 Consumer register
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SETAMPER_TAMPERSRC28 CONSUMER_SETAMPER_TAMPERSRC28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : TAMPERSRC28 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SETAMPER_TAMPERSRC29

TAMPERSRC29 Consumer register
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SETAMPER_TAMPERSRC29 CONSUMER_SETAMPER_TAMPERSRC29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : TAMPERSRC29 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SETAMPER_TAMPERSRC30

TAMPERSRC30 Consumer register
address_offset : 0x11C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SETAMPER_TAMPERSRC30 CONSUMER_SETAMPER_TAMPERSRC30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : TAMPERSRC30 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SETAMPER_TAMPERSRC31

TAMPERSRC31 Consumer register
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SETAMPER_TAMPERSRC31 CONSUMER_SETAMPER_TAMPERSRC31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : TAMPERSRC31 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SYSRTC0_IN0

IN0 consumer register
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SYSRTC0_IN0 CONSUMER_SYSRTC0_IN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : IN0 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SYSRTC0_IN1

IN1 Consumer register
address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SYSRTC0_IN1 CONSUMER_SYSRTC0_IN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : IN1 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_HFXO0_OSCREQ

OSCREQ consumer register
address_offset : 0x12C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_HFXO0_OSCREQ CONSUMER_HFXO0_OSCREQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : OSC async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_HFXO0_TIMEOUT

TIMEOUT Consumer register
address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_HFXO0_TIMEOUT CONSUMER_HFXO0_TIMEOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : TIMEOUT async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_CORE_CTIIN0

CTI consumer register
address_offset : 0x134 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_CORE_CTIIN0 CONSUMER_CORE_CTIIN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_CORE_CTIIN1

CTI Consumer register
address_offset : 0x138 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_CORE_CTIIN1 CONSUMER_CORE_CTIIN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_CORE_CTIIN2

CTI Consumer register
address_offset : 0x13C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_CORE_CTIIN2 CONSUMER_CORE_CTIIN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


SYNC_PEEK

No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNC_PEEK SYNC_PEEK read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0VAL CH1VAL CH2VAL CH3VAL

CH0VAL : Channel Value
bits : 0 - 0 (1 bit)
access : read-only

CH1VAL : Channel Value
bits : 1 - 1 (1 bit)
access : read-only

CH2VAL : Channel Value
bits : 2 - 2 (1 bit)
access : read-only

CH3VAL : Channel Value
bits : 3 - 3 (1 bit)
access : read-only


CONSUMER_CORE_CTIIN3

CTI Consumer register
address_offset : 0x140 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_CORE_CTIIN3 CONSUMER_CORE_CTIIN3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_CORE_M33RXEV

M33 Consumer register
address_offset : 0x144 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_CORE_M33RXEV CONSUMER_CORE_M33RXEV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : M33 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER0_CC0

CC0 consumer register
address_offset : 0x148 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER0_CC0 CONSUMER_TIMER0_CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : CC0 async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : CC0 sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER0_CC1

CC1 Consumer register
address_offset : 0x14C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER0_CC1 CONSUMER_TIMER0_CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : CC1 async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : CC1 sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER0_CC2

CC2 Consumer register
address_offset : 0x150 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER0_CC2 CONSUMER_TIMER0_CC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : CC2 async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : CC2 sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER0_DTI

DTI Consumer register
address_offset : 0x154 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER0_DTI CONSUMER_TIMER0_DTI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER0_DTIFS1

DTI Consumer register
address_offset : 0x158 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER0_DTIFS1 CONSUMER_TIMER0_DTIFS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER0_DTIFS2

DTI Consumer register
address_offset : 0x15C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER0_DTIFS2 CONSUMER_TIMER0_DTIFS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER1_CC0

CC0 consumer register
address_offset : 0x160 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER1_CC0 CONSUMER_TIMER1_CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : CC0 async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : CC0 sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER1_CC1

CC1 Consumer register
address_offset : 0x164 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER1_CC1 CONSUMER_TIMER1_CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : CC1 async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : CC1 sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER1_CC2

CC2 Consumer register
address_offset : 0x168 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER1_CC2 CONSUMER_TIMER1_CC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : CC2 async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : CC2 sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER1_DTI

DTI Consumer register
address_offset : 0x16C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER1_DTI CONSUMER_TIMER1_DTI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER1_DTIFS1

DTI Consumer register
address_offset : 0x170 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER1_DTIFS1 CONSUMER_TIMER1_DTIFS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER1_DTIFS2

DTI Consumer register
address_offset : 0x174 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER1_DTIFS2 CONSUMER_TIMER1_DTIFS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER2_CC0

CC0 consumer register
address_offset : 0x178 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER2_CC0 CONSUMER_TIMER2_CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : CC0 async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : CC0 sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER2_CC1

CC1 Consumer register
address_offset : 0x17C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER2_CC1 CONSUMER_TIMER2_CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : CC1 async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : CC1 sync channel select
bits : 8 - 9 (2 bit)
access : read-write


ASYNC_CH0_CTRL

No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH0_CTRL ASYNC_CH0_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL AUXSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.

AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write


CONSUMER_TIMER2_CC2

CC2 Consumer register
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER2_CC2 CONSUMER_TIMER2_CC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : CC2 async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : CC2 sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER2_DTI

DTI Consumer register
address_offset : 0x184 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER2_DTI CONSUMER_TIMER2_DTI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER2_DTIFS1

DTI Consumer register
address_offset : 0x188 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER2_DTIFS1 CONSUMER_TIMER2_DTIFS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER2_DTIFS2

DTI Consumer register
address_offset : 0x18C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER2_DTIFS2 CONSUMER_TIMER2_DTIFS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER3_CC0

CC0 consumer register
address_offset : 0x190 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER3_CC0 CONSUMER_TIMER3_CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : CC0 async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : CC0 sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER3_CC1

CC1 Consumer register
address_offset : 0x194 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER3_CC1 CONSUMER_TIMER3_CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : CC1 async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : CC1 sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER3_CC2

CC2 Consumer register
address_offset : 0x198 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER3_CC2 CONSUMER_TIMER3_CC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : CC2 async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : CC2 sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER3_DTI

DTI Consumer register
address_offset : 0x19C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER3_DTI CONSUMER_TIMER3_DTI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER3_DTIFS1

DTI Consumer register
address_offset : 0x1A0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER3_DTIFS1 CONSUMER_TIMER3_DTIFS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER3_DTIFS2

DTI Consumer register
address_offset : 0x1A4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER3_DTIFS2 CONSUMER_TIMER3_DTIFS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER4_CC0

CC0 consumer register
address_offset : 0x1A8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER4_CC0 CONSUMER_TIMER4_CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : CC0 async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : CC0 sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER4_CC1

CC1 Consumer register
address_offset : 0x1AC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER4_CC1 CONSUMER_TIMER4_CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : CC1 async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : CC1 sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER4_CC2

CC2 Consumer register
address_offset : 0x1B0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER4_CC2 CONSUMER_TIMER4_CC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : CC2 async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : CC2 sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER4_DTI

DTI Consumer register
address_offset : 0x1B4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER4_DTI CONSUMER_TIMER4_DTI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER4_DTIFS1

DTI Consumer register
address_offset : 0x1B8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER4_DTIFS1 CONSUMER_TIMER4_DTIFS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER4_DTIFS2

DTI Consumer register
address_offset : 0x1BC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER4_DTIFS2 CONSUMER_TIMER4_DTIFS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


ASYNC_CH1_CTRL

No Description
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH1_CTRL ASYNC_CH1_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL AUXSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.

AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write


CONSUMER_USART0_CLK

CLK consumer register
address_offset : 0x1C0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_USART0_CLK CONSUMER_USART0_CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CLK async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_USART0_IR

IR Consumer register
address_offset : 0x1C4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_USART0_IR CONSUMER_USART0_IR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : IR async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_USART0_RX

RX Consumer register
address_offset : 0x1C8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_USART0_RX CONSUMER_USART0_RX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : RX async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_USART0_TRIGGER

TRIGGER Consumer register
address_offset : 0x1CC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_USART0_TRIGGER CONSUMER_USART0_TRIGGER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : TRIGGER async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_VDAC0_ASYNCTRIGCH0

ASYNCTRIG consumer register
address_offset : 0x1DC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_VDAC0_ASYNCTRIGCH0 CONSUMER_VDAC0_ASYNCTRIGCH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : ASYNCTRIG async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_VDAC0_ASYNCTRIGCH1

ASYNCTRIG Consumer register
address_offset : 0x1E0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_VDAC0_ASYNCTRIGCH1 CONSUMER_VDAC0_ASYNCTRIGCH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : ASYNCTRIG async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_VDAC0_SYNCTRIGCH0

SYNCTRIG Consumer register
address_offset : 0x1E4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_VDAC0_SYNCTRIGCH0 CONSUMER_VDAC0_SYNCTRIGCH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPRSSEL

SPRSSEL : SYNCTRIG sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_VDAC0_SYNCTRIGCH1

SYNCTRIG Consumer register
address_offset : 0x1E8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_VDAC0_SYNCTRIGCH1 CONSUMER_VDAC0_SYNCTRIGCH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPRSSEL

SPRSSEL : SYNCTRIG sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_VDAC1_ASYNCTRIGCH0

ASYNCTRIG consumer register
address_offset : 0x1EC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_VDAC1_ASYNCTRIGCH0 CONSUMER_VDAC1_ASYNCTRIGCH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : ASYNCTRIG async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_VDAC1_ASYNCTRIGCH1

ASYNCTRIG Consumer register
address_offset : 0x1F0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_VDAC1_ASYNCTRIGCH1 CONSUMER_VDAC1_ASYNCTRIGCH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : ASYNCTRIG async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_VDAC1_SYNCTRIGCH0

SYNCTRIG Consumer register
address_offset : 0x1F4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_VDAC1_SYNCTRIGCH0 CONSUMER_VDAC1_SYNCTRIGCH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPRSSEL

SPRSSEL : SYNCTRIG sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_VDAC1_SYNCTRIGCH1

SYNCTRIG Consumer register
address_offset : 0x1F8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_VDAC1_SYNCTRIGCH1 CONSUMER_VDAC1_SYNCTRIGCH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPRSSEL

SPRSSEL : SYNCTRIG sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_WDOG0_SRC0

SRC0 consumer register
address_offset : 0x1FC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_WDOG0_SRC0 CONSUMER_WDOG0_SRC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : SRC0 async channel select
bits : 0 - 3 (4 bit)
access : read-write


ASYNC_CH2_CTRL

No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH2_CTRL ASYNC_CH2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL AUXSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.

AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write


CONSUMER_WDOG0_SRC1

SRC1 Consumer register
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_WDOG0_SRC1 CONSUMER_WDOG0_SRC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : SRC1 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_WDOG1_SRC0

SRC0 consumer register
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_WDOG1_SRC0 CONSUMER_WDOG1_SRC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : SRC0 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_WDOG1_SRC1

SRC1 Consumer register
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_WDOG1_SRC1 CONSUMER_WDOG1_SRC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : SRC1 async channel select
bits : 0 - 3 (4 bit)
access : read-write


RPURATD0

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x20C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPURATD0 RPURATD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDENABLE RATDASYNCSWPULSE RATDASYNCSWLEVEL RATDASYNCH0CTRL RATDASYNCH1CTRL RATDASYNCH2CTRL RATDASYNCH3CTRL RATDASYNCH4CTRL RATDASYNCH5CTRL RATDASYNCH6CTRL RATDASYNCH7CTRL RATDASYNCH8CTRL RATDASYNCH9CTRL RATDASYNCH10CTRL RATDASYNCH11CTRL RATDASYNCH12CTRL RATDASYNCH13CTRL RATDASYNCH14CTRL RATDASYNCH15CTRL RATDSYNCH0CTRL RATDSYNCH1CTRL RATDSYNCH2CTRL RATDSYNCH3CTRL RATDCMUCALDN RATDCMUCALUP RATDEUSART0CLK RATDEUSART0RX RATDEUSART0TRIGGER RATDEUSART1CLK

RATDENABLE : ENABLE Protection Bit
bits : 1 - 1 (1 bit)
access : read-write

RATDASYNCSWPULSE : ASYNC_SWPULSE Protection Bit
bits : 2 - 2 (1 bit)
access : read-write

RATDASYNCSWLEVEL : ASYNC_SWLEVEL Protection Bit
bits : 3 - 3 (1 bit)
access : read-write

RATDASYNCH0CTRL : CTRL Protection Bit
bits : 6 - 6 (1 bit)
access : read-write

RATDASYNCH1CTRL : CTRL Protection Bit
bits : 7 - 7 (1 bit)
access : read-write

RATDASYNCH2CTRL : CTRL Protection Bit
bits : 8 - 8 (1 bit)
access : read-write

RATDASYNCH3CTRL : CTRL Protection Bit
bits : 9 - 9 (1 bit)
access : read-write

RATDASYNCH4CTRL : CTRL Protection Bit
bits : 10 - 10 (1 bit)
access : read-write

RATDASYNCH5CTRL : CTRL Protection Bit
bits : 11 - 11 (1 bit)
access : read-write

RATDASYNCH6CTRL : CTRL Protection Bit
bits : 12 - 12 (1 bit)
access : read-write

RATDASYNCH7CTRL : CTRL Protection Bit
bits : 13 - 13 (1 bit)
access : read-write

RATDASYNCH8CTRL : CTRL Protection Bit
bits : 14 - 14 (1 bit)
access : read-write

RATDASYNCH9CTRL : CTRL Protection Bit
bits : 15 - 15 (1 bit)
access : read-write

RATDASYNCH10CTRL : CTRL Protection Bit
bits : 16 - 16 (1 bit)
access : read-write

RATDASYNCH11CTRL : CTRL Protection Bit
bits : 17 - 17 (1 bit)
access : read-write

RATDASYNCH12CTRL : CTRL Protection Bit
bits : 18 - 18 (1 bit)
access : read-write

RATDASYNCH13CTRL : CTRL Protection Bit
bits : 19 - 19 (1 bit)
access : read-write

RATDASYNCH14CTRL : CTRL Protection Bit
bits : 20 - 20 (1 bit)
access : read-write

RATDASYNCH15CTRL : CTRL Protection Bit
bits : 21 - 21 (1 bit)
access : read-write

RATDSYNCH0CTRL : CTRL Protection Bit
bits : 22 - 22 (1 bit)
access : read-write

RATDSYNCH1CTRL : CTRL Protection Bit
bits : 23 - 23 (1 bit)
access : read-write

RATDSYNCH2CTRL : CTRL Protection Bit
bits : 24 - 24 (1 bit)
access : read-write

RATDSYNCH3CTRL : CTRL Protection Bit
bits : 25 - 25 (1 bit)
access : read-write

RATDCMUCALDN : CMU_CALDN Protection Bit
bits : 26 - 26 (1 bit)
access : read-write

RATDCMUCALUP : CMU_CALUP Protection Bit
bits : 27 - 27 (1 bit)
access : read-write

RATDEUSART0CLK : EUSART0_CLK Protection Bit
bits : 28 - 28 (1 bit)
access : read-write

RATDEUSART0RX : EUSART0_RX Protection Bit
bits : 29 - 29 (1 bit)
access : read-write

RATDEUSART0TRIGGER : EUSART0_TRIGGER Protection Bit
bits : 30 - 30 (1 bit)
access : read-write

RATDEUSART1CLK : EUSART1_CLK Protection Bit
bits : 31 - 31 (1 bit)
access : read-write


RPURATD1

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x210 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPURATD1 RPURATD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDEUSART1RX RATDEUSART1TRIGGER RATDFRCRXRAW RATDIADC0SCANTRIGGER RATDIADC0SINGLETRIGGER RATDLDMAXBARDMAREQ0 RATDLDMAXBARDMAREQ1 RATDLETIMERCLEAR RATDLETIMERSTART RATDLETIMERSTOP RATDMODEMDIN RATDMODEMPAEN RATDPCNT0S0IN RATDPCNT0S1IN RATDPROTIMERCC0 RATDPROTIMERCC1 RATDPROTIMERCC2 RATDPROTIMERCC3 RATDPROTIMERCC4 RATDPROTIMERLBTPAUSE RATDPROTIMERLBTSTART RATDPROTIMERLBTSTOP RATDPROTIMERRTCCTRIGGER RATDPROTIMERSTART RATDPROTIMERSTOP RATDRACCLR RATDRACCTIIN0 RATDRACCTIIN1 RATDRACCTIIN2 RATDRACCTIIN3 RATDRACFORCETX RATDRACRXDIS

RATDEUSART1RX : EUSART1_RX Protection Bit
bits : 0 - 0 (1 bit)
access : read-write

RATDEUSART1TRIGGER : EUSART1_TRIGGER Protection Bit
bits : 1 - 1 (1 bit)
access : read-write

RATDFRCRXRAW : FRC_RXRAW Protection Bit
bits : 2 - 2 (1 bit)
access : read-write

RATDIADC0SCANTRIGGER : IADC0_SCANTRIGGER Protection Bit
bits : 3 - 3 (1 bit)
access : read-write

RATDIADC0SINGLETRIGGER : IADC0_SINGLETRIGGER Protection Bit
bits : 4 - 4 (1 bit)
access : read-write

RATDLDMAXBARDMAREQ0 : LDMAXBAR_DMAREQ0 Protection Bit
bits : 5 - 5 (1 bit)
access : read-write

RATDLDMAXBARDMAREQ1 : LDMAXBAR_DMAREQ1 Protection Bit
bits : 6 - 6 (1 bit)
access : read-write

RATDLETIMERCLEAR : LETIMER_CLEAR Protection Bit
bits : 7 - 7 (1 bit)
access : read-write

RATDLETIMERSTART : LETIMER_START Protection Bit
bits : 8 - 8 (1 bit)
access : read-write

RATDLETIMERSTOP : LETIMER_STOP Protection Bit
bits : 9 - 9 (1 bit)
access : read-write

RATDMODEMDIN : MODEM_DIN Protection Bit
bits : 10 - 10 (1 bit)
access : read-write

RATDMODEMPAEN : MODEM_PAEN Protection Bit
bits : 11 - 11 (1 bit)
access : read-write

RATDPCNT0S0IN : PCNT0_S0IN Protection Bit
bits : 12 - 12 (1 bit)
access : read-write

RATDPCNT0S1IN : PCNT0_S1IN Protection Bit
bits : 13 - 13 (1 bit)
access : read-write

RATDPROTIMERCC0 : PROTIMER_CC0 Protection Bit
bits : 14 - 14 (1 bit)
access : read-write

RATDPROTIMERCC1 : PROTIMER_CC1 Protection Bit
bits : 15 - 15 (1 bit)
access : read-write

RATDPROTIMERCC2 : PROTIMER_CC2 Protection Bit
bits : 16 - 16 (1 bit)
access : read-write

RATDPROTIMERCC3 : PROTIMER_CC3 Protection Bit
bits : 17 - 17 (1 bit)
access : read-write

RATDPROTIMERCC4 : PROTIMER_CC4 Protection Bit
bits : 18 - 18 (1 bit)
access : read-write

RATDPROTIMERLBTPAUSE : PROTIMER_LBTPAUSE Protection Bit
bits : 19 - 19 (1 bit)
access : read-write

RATDPROTIMERLBTSTART : PROTIMER_LBTSTART Protection Bit
bits : 20 - 20 (1 bit)
access : read-write

RATDPROTIMERLBTSTOP : PROTIMER_LBTSTOP Protection Bit
bits : 21 - 21 (1 bit)
access : read-write

RATDPROTIMERRTCCTRIGGER : PROTIMER_RTCCTRIGGER Protection Bit
bits : 22 - 22 (1 bit)
access : read-write

RATDPROTIMERSTART : PROTIMER_START Protection Bit
bits : 23 - 23 (1 bit)
access : read-write

RATDPROTIMERSTOP : PROTIMER_STOP Protection Bit
bits : 24 - 24 (1 bit)
access : read-write

RATDRACCLR : RAC_CLR Protection Bit
bits : 25 - 25 (1 bit)
access : read-write

RATDRACCTIIN0 : RAC_CTIIN0 Protection Bit
bits : 26 - 26 (1 bit)
access : read-write

RATDRACCTIIN1 : RAC_CTIIN1 Protection Bit
bits : 27 - 27 (1 bit)
access : read-write

RATDRACCTIIN2 : RAC_CTIIN2 Protection Bit
bits : 28 - 28 (1 bit)
access : read-write

RATDRACCTIIN3 : RAC_CTIIN3 Protection Bit
bits : 29 - 29 (1 bit)
access : read-write

RATDRACFORCETX : RAC_FORCETX Protection Bit
bits : 30 - 30 (1 bit)
access : read-write

RATDRACRXDIS : RAC_RXDIS Protection Bit
bits : 31 - 31 (1 bit)
access : read-write


RPURATD2

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x214 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPURATD2 RPURATD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDRACRXEN RATDRACTXEN RATDSETAMPERTAMPERSRC25 RATDSETAMPERTAMPERSRC26 RATDSETAMPERTAMPERSRC27 RATDSETAMPERTAMPERSRC28 RATDSETAMPERTAMPERSRC29 RATDSETAMPERTAMPERSRC30 RATDSETAMPERTAMPERSRC31 RATDSYSRTC0IN0 RATDSYSRTC0IN1 RATDSYXO0OSCREQ RATDSYXO0TIMEOUT RATDCORECTIIN0 RATDCORECTIIN1 RATDCORECTIIN2 RATDCORECTIIN3 RATDCOREM33RXEV RATDTIMER0CC0 RATDTIMER0CC1 RATDTIMER0CC2 RATDTIMER0DTI RATDTIMER0DTIFS1 RATDTIMER0DTIFS2 RATDTIMER1CC0 RATDTIMER1CC1 RATDTIMER1CC2 RATDTIMER1DTI RATDTIMER1DTIFS1 RATDTIMER1DTIFS2 RATDTIMER2CC0 RATDTIMER2CC1

RATDRACRXEN : RAC_RXEN Protection Bit
bits : 0 - 0 (1 bit)
access : read-write

RATDRACTXEN : RAC_TXEN Protection Bit
bits : 1 - 1 (1 bit)
access : read-write

RATDSETAMPERTAMPERSRC25 : SETAMPER_TAMPERSRC25 Protection Bit
bits : 2 - 2 (1 bit)
access : read-write

RATDSETAMPERTAMPERSRC26 : SETAMPER_TAMPERSRC26 Protection Bit
bits : 3 - 3 (1 bit)
access : read-write

RATDSETAMPERTAMPERSRC27 : SETAMPER_TAMPERSRC27 Protection Bit
bits : 4 - 4 (1 bit)
access : read-write

RATDSETAMPERTAMPERSRC28 : SETAMPER_TAMPERSRC28 Protection Bit
bits : 5 - 5 (1 bit)
access : read-write

RATDSETAMPERTAMPERSRC29 : SETAMPER_TAMPERSRC29 Protection Bit
bits : 6 - 6 (1 bit)
access : read-write

RATDSETAMPERTAMPERSRC30 : SETAMPER_TAMPERSRC30 Protection Bit
bits : 7 - 7 (1 bit)
access : read-write

RATDSETAMPERTAMPERSRC31 : SETAMPER_TAMPERSRC31 Protection Bit
bits : 8 - 8 (1 bit)
access : read-write

RATDSYSRTC0IN0 : SYSRTC0_IN0 Protection Bit
bits : 9 - 9 (1 bit)
access : read-write

RATDSYSRTC0IN1 : SYSRTC0_IN1 Protection Bit
bits : 10 - 10 (1 bit)
access : read-write

RATDSYXO0OSCREQ : SYXO0_OSCREQ Protection Bit
bits : 11 - 11 (1 bit)
access : read-write

RATDSYXO0TIMEOUT : SYXO0_TIMEOUT Protection Bit
bits : 12 - 12 (1 bit)
access : read-write

RATDCORECTIIN0 : CORE_CTIIN0 Protection Bit
bits : 13 - 13 (1 bit)
access : read-write

RATDCORECTIIN1 : CORE_CTIIN1 Protection Bit
bits : 14 - 14 (1 bit)
access : read-write

RATDCORECTIIN2 : CORE_CTIIN2 Protection Bit
bits : 15 - 15 (1 bit)
access : read-write

RATDCORECTIIN3 : CORE_CTIIN3 Protection Bit
bits : 16 - 16 (1 bit)
access : read-write

RATDCOREM33RXEV : CORE_M33RXEV Protection Bit
bits : 17 - 17 (1 bit)
access : read-write

RATDTIMER0CC0 : TIMER0_CC0 Protection Bit
bits : 18 - 18 (1 bit)
access : read-write

RATDTIMER0CC1 : TIMER0_CC1 Protection Bit
bits : 19 - 19 (1 bit)
access : read-write

RATDTIMER0CC2 : TIMER0_CC2 Protection Bit
bits : 20 - 20 (1 bit)
access : read-write

RATDTIMER0DTI : TIMER0_DTI Protection Bit
bits : 21 - 21 (1 bit)
access : read-write

RATDTIMER0DTIFS1 : TIMER0_DTIFS1 Protection Bit
bits : 22 - 22 (1 bit)
access : read-write

RATDTIMER0DTIFS2 : TIMER0_DTIFS2 Protection Bit
bits : 23 - 23 (1 bit)
access : read-write

RATDTIMER1CC0 : TIMER1_CC0 Protection Bit
bits : 24 - 24 (1 bit)
access : read-write

RATDTIMER1CC1 : TIMER1_CC1 Protection Bit
bits : 25 - 25 (1 bit)
access : read-write

RATDTIMER1CC2 : TIMER1_CC2 Protection Bit
bits : 26 - 26 (1 bit)
access : read-write

RATDTIMER1DTI : TIMER1_DTI Protection Bit
bits : 27 - 27 (1 bit)
access : read-write

RATDTIMER1DTIFS1 : TIMER1_DTIFS1 Protection Bit
bits : 28 - 28 (1 bit)
access : read-write

RATDTIMER1DTIFS2 : TIMER1_DTIFS2 Protection Bit
bits : 29 - 29 (1 bit)
access : read-write

RATDTIMER2CC0 : TIMER2_CC0 Protection Bit
bits : 30 - 30 (1 bit)
access : read-write

RATDTIMER2CC1 : TIMER2_CC1 Protection Bit
bits : 31 - 31 (1 bit)
access : read-write


RPURATD3

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x218 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPURATD3 RPURATD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDTIMER2CC2 RATDTIMER2DTI RATDTIMER2DTIFS1 RATDTIMER2DTIFS2 RATDTIMER3CC0 RATDTIMER3CC1 RATDTIMER3CC2 RATDTIMER3DTI RATDTIMER3DTIFS1 RATDTIMER3DTIFS2 RATDTIMER4CC0 RATDTIMER4CC1 RATDTIMER4CC2 RATDTIMER4DTI RATDTIMER4DTIFS1 RATDTIMER4DTIFS2 RATDUSART0CLK RATDUSART0IR RATDUSART0RX RATDUSART0TRIGGER RATDVDAC0ASYNCTRIGCH0 RATDVDAC0ASYNCTRIGCH1 RATDVDAC0SYNCTRIGCH0 RATDVDAC0SYNCTRIGCH1 RATDVDAC1ASYNCTRIGCH0 RATDVDAC1ASYNCTRIGCH1 RATDVDAC1SYNCTRIGCH0 RATDVDAC1SYNCTRIGCH1 RATDWDOG0SRC0

RATDTIMER2CC2 : TIMER2_CC2 Protection Bit
bits : 0 - 0 (1 bit)
access : read-write

RATDTIMER2DTI : TIMER2_DTI Protection Bit
bits : 1 - 1 (1 bit)
access : read-write

RATDTIMER2DTIFS1 : TIMER2_DTIFS1 Protection Bit
bits : 2 - 2 (1 bit)
access : read-write

RATDTIMER2DTIFS2 : TIMER2_DTIFS2 Protection Bit
bits : 3 - 3 (1 bit)
access : read-write

RATDTIMER3CC0 : TIMER3_CC0 Protection Bit
bits : 4 - 4 (1 bit)
access : read-write

RATDTIMER3CC1 : TIMER3_CC1 Protection Bit
bits : 5 - 5 (1 bit)
access : read-write

RATDTIMER3CC2 : TIMER3_CC2 Protection Bit
bits : 6 - 6 (1 bit)
access : read-write

RATDTIMER3DTI : TIMER3_DTI Protection Bit
bits : 7 - 7 (1 bit)
access : read-write

RATDTIMER3DTIFS1 : TIMER3_DTIFS1 Protection Bit
bits : 8 - 8 (1 bit)
access : read-write

RATDTIMER3DTIFS2 : TIMER3_DTIFS2 Protection Bit
bits : 9 - 9 (1 bit)
access : read-write

RATDTIMER4CC0 : TIMER4_CC0 Protection Bit
bits : 10 - 10 (1 bit)
access : read-write

RATDTIMER4CC1 : TIMER4_CC1 Protection Bit
bits : 11 - 11 (1 bit)
access : read-write

RATDTIMER4CC2 : TIMER4_CC2 Protection Bit
bits : 12 - 12 (1 bit)
access : read-write

RATDTIMER4DTI : TIMER4_DTI Protection Bit
bits : 13 - 13 (1 bit)
access : read-write

RATDTIMER4DTIFS1 : TIMER4_DTIFS1 Protection Bit
bits : 14 - 14 (1 bit)
access : read-write

RATDTIMER4DTIFS2 : TIMER4_DTIFS2 Protection Bit
bits : 15 - 15 (1 bit)
access : read-write

RATDUSART0CLK : USART0_CLK Protection Bit
bits : 16 - 16 (1 bit)
access : read-write

RATDUSART0IR : USART0_IR Protection Bit
bits : 17 - 17 (1 bit)
access : read-write

RATDUSART0RX : USART0_RX Protection Bit
bits : 18 - 18 (1 bit)
access : read-write

RATDUSART0TRIGGER : USART0_TRIGGER Protection Bit
bits : 19 - 19 (1 bit)
access : read-write

RATDVDAC0ASYNCTRIGCH0 : VDAC0_ASYNCTRIGCH0 Protection Bit
bits : 23 - 23 (1 bit)
access : read-write

RATDVDAC0ASYNCTRIGCH1 : VDAC0_ASYNCTRIGCH1 Protection Bit
bits : 24 - 24 (1 bit)
access : read-write

RATDVDAC0SYNCTRIGCH0 : VDAC0_SYNCTRIGCH0 Protection Bit
bits : 25 - 25 (1 bit)
access : read-write

RATDVDAC0SYNCTRIGCH1 : VDAC0_SYNCTRIGCH1 Protection Bit
bits : 26 - 26 (1 bit)
access : read-write

RATDVDAC1ASYNCTRIGCH0 : VDAC1_ASYNCTRIGCH0 Protection Bit
bits : 27 - 27 (1 bit)
access : read-write

RATDVDAC1ASYNCTRIGCH1 : VDAC1_ASYNCTRIGCH1 Protection Bit
bits : 28 - 28 (1 bit)
access : read-write

RATDVDAC1SYNCTRIGCH0 : VDAC1_SYNCTRIGCH0 Protection Bit
bits : 29 - 29 (1 bit)
access : read-write

RATDVDAC1SYNCTRIGCH1 : VDAC1_SYNCTRIGCH1 Protection Bit
bits : 30 - 30 (1 bit)
access : read-write

RATDWDOG0SRC0 : WDOG0_SRC0 Protection Bit
bits : 31 - 31 (1 bit)
access : read-write


RPURATD4

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x21C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPURATD4 RPURATD4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDWDOG0SRC1 RATDWDOG1SRC0 RATDWDOG1SRC1

RATDWDOG0SRC1 : WDOG0_SRC1 Protection Bit
bits : 0 - 0 (1 bit)
access : read-write

RATDWDOG1SRC0 : WDOG1_SRC0 Protection Bit
bits : 1 - 1 (1 bit)
access : read-write

RATDWDOG1SRC1 : WDOG1_SRC1 Protection Bit
bits : 2 - 2 (1 bit)
access : read-write


ASYNC_CH3_CTRL

No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH3_CTRL ASYNC_CH3_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL AUXSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.

AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write


ASYNC_CH4_CTRL

No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH4_CTRL ASYNC_CH4_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL AUXSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.

AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write


ASYNC_CH5_CTRL

No Description
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH5_CTRL ASYNC_CH5_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL AUXSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.

AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write


ASYNC_CH6_CTRL

No Description
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH6_CTRL ASYNC_CH6_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL AUXSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.

AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write


ASYNC_CH7_CTRL

No Description
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH7_CTRL ASYNC_CH7_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL AUXSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.

AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write


ASYNC_CH8_CTRL

No Description
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH8_CTRL ASYNC_CH8_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL AUXSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.

AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write


ASYNC_CH9_CTRL

No Description
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH9_CTRL ASYNC_CH9_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL AUXSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.

AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write


ASYNC_CH10_CTRL

No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH10_CTRL ASYNC_CH10_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL AUXSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.

AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write


ASYNC_CH11_CTRL

No Description
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH11_CTRL ASYNC_CH11_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL AUXSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.

AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write


ASYNC_CH12_CTRL

No Description
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH12_CTRL ASYNC_CH12_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL AUXSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.

AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write


ASYNC_CH13_CTRL

No Description
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH13_CTRL ASYNC_CH13_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL AUXSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.

AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write


ASYNC_CH14_CTRL

No Description
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH14_CTRL ASYNC_CH14_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL AUXSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.

AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write


ASYNC_CH15_CTRL

No Description
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH15_CTRL ASYNC_CH15_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL AUXSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.

AUXSEL : Aux Select
bits : 24 - 27 (4 bit)
access : read-write


SYNC_CH0_CTRL

No Description
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNC_CH0_CTRL SYNC_CH0_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write


SYNC_CH1_CTRL

No Description
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNC_CH1_CTRL SYNC_CH1_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write


SYNC_CH2_CTRL

No Description
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNC_CH2_CTRL SYNC_CH2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write


SYNC_CH3_CTRL

No Description
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNC_CH3_CTRL SYNC_CH3_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write


CONSUMER_CMU_CALDN

CALDN consumer register
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_CMU_CALDN CONSUMER_CMU_CALDN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CALDN async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_CMU_CALUP

CALUP Consumer register
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_CMU_CALUP CONSUMER_CMU_CALUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CALUP async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_EUSART0_CLK

CLK consumer register
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_EUSART0_CLK CONSUMER_EUSART0_CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CLK async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_EUSART0_RX

RX Consumer register
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_EUSART0_RX CONSUMER_EUSART0_RX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : RX async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_EUSART0_TRIGGER

TRIGGER Consumer register
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_EUSART0_TRIGGER CONSUMER_EUSART0_TRIGGER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : TRIGGER async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_EUSART1_CLK

CLK consumer register
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_EUSART1_CLK CONSUMER_EUSART1_CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CLK async channel select
bits : 0 - 3 (4 bit)
access : read-write


ASYNC_SWPULSE

No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ASYNC_SWPULSE ASYNC_SWPULSE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0PULSE CH1PULSE CH2PULSE CH3PULSE CH4PULSE CH5PULSE CH6PULSE CH7PULSE CH8PULSE CH9PULSE CH10PULSE CH11PULSE CH12PULSE CH13PULSE CH14PULSE CH15PULSE

CH0PULSE : Channel pulse
bits : 0 - 0 (1 bit)
access : write-only

CH1PULSE : Channel pulse
bits : 1 - 1 (1 bit)
access : write-only

CH2PULSE : Channel pulse
bits : 2 - 2 (1 bit)
access : write-only

CH3PULSE : Channel pulse
bits : 3 - 3 (1 bit)
access : write-only

CH4PULSE : Channel pulse
bits : 4 - 4 (1 bit)
access : write-only

CH5PULSE : Channel pulse
bits : 5 - 5 (1 bit)
access : write-only

CH6PULSE : Channel pulse
bits : 6 - 6 (1 bit)
access : write-only

CH7PULSE : Channel pulse
bits : 7 - 7 (1 bit)
access : write-only

CH8PULSE : Channel pulse
bits : 8 - 8 (1 bit)
access : write-only

CH9PULSE : Channel pulse
bits : 9 - 9 (1 bit)
access : write-only

CH10PULSE : Channel pulse
bits : 10 - 10 (1 bit)
access : write-only

CH11PULSE : Channel pulse
bits : 11 - 11 (1 bit)
access : write-only

CH12PULSE : Channel pulse
bits : 12 - 12 (1 bit)
access : write-only

CH13PULSE : Channel pulse
bits : 13 - 13 (1 bit)
access : write-only

CH14PULSE : Channel pulse
bits : 14 - 14 (1 bit)
access : write-only

CH15PULSE : Channel pulse
bits : 15 - 15 (1 bit)
access : write-only


CONSUMER_EUSART1_RX

RX Consumer register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_EUSART1_RX CONSUMER_EUSART1_RX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : RX async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_EUSART1_TRIGGER

TRIGGER Consumer register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_EUSART1_TRIGGER CONSUMER_EUSART1_TRIGGER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : TRIGGER async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_FRC_RXRAW

RXRAW consumer register
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_FRC_RXRAW CONSUMER_FRC_RXRAW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : RXRAW async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_IADC0_SCANTRIGGER

SCAN consumer register
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_IADC0_SCANTRIGGER CONSUMER_IADC0_SCANTRIGGER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : SCAN async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : SCAN sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_IADC0_SINGLETRIGGER

SINGLE Consumer register
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_IADC0_SINGLETRIGGER CONSUMER_IADC0_SINGLETRIGGER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : SINGLE async channel select
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : SINGLE sync channel select
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_LDMAXBAR_DMAREQ0

DMAREQ0 consumer register
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_LDMAXBAR_DMAREQ0 CONSUMER_LDMAXBAR_DMAREQ0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DMAREQ0 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_LDMAXBAR_DMAREQ1

DMAREQ1 Consumer register
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_LDMAXBAR_DMAREQ1 CONSUMER_LDMAXBAR_DMAREQ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DMAREQ1 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_LETIMER0_CLEAR

CLEAR consumer register
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_LETIMER0_CLEAR CONSUMER_LETIMER0_CLEAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CLEAR async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_LETIMER0_START

START Consumer register
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_LETIMER0_START CONSUMER_LETIMER0_START read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : START async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_LETIMER0_STOP

STOP Consumer register
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_LETIMER0_STOP CONSUMER_LETIMER0_STOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : STOP async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_MODEM_DIN

DIN consumer register
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_MODEM_DIN CONSUMER_MODEM_DIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DIN async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_MODEM_PAEN

PAEN Consumer register
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_MODEM_PAEN CONSUMER_MODEM_PAEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : PAEN async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_PCNT0_S0IN

S0IN consumer register
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_PCNT0_S0IN CONSUMER_PCNT0_S0IN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : S0IN async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_PCNT0_S1IN

S1IN Consumer register
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_PCNT0_S1IN CONSUMER_PCNT0_S1IN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : S1IN async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_PROTIMER_CC0

CC0 consumer register
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_PROTIMER_CC0 CONSUMER_PROTIMER_CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CC0 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_PROTIMER_CC1

CC1 Consumer register
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_PROTIMER_CC1 CONSUMER_PROTIMER_CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CC1 async channel select
bits : 0 - 3 (4 bit)
access : read-write


ASYNC_SWLEVEL

No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_SWLEVEL ASYNC_SWLEVEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0LEVEL CH1LEVEL CH2LEVEL CH3LEVEL CH4LEVEL CH5LEVEL CH6LEVEL CH7LEVEL CH8LEVEL CH9LEVEL CH10LEVEL CH11LEVEL CH12LEVEL CH13LEVEL CH14LEVEL CH15LEVEL

CH0LEVEL : Channel Level
bits : 0 - 0 (1 bit)
access : read-write

CH1LEVEL : Channel Level
bits : 1 - 1 (1 bit)
access : read-write

CH2LEVEL : Channel Level
bits : 2 - 2 (1 bit)
access : read-write

CH3LEVEL : Channel Level
bits : 3 - 3 (1 bit)
access : read-write

CH4LEVEL : Channel Level
bits : 4 - 4 (1 bit)
access : read-write

CH5LEVEL : Channel Level
bits : 5 - 5 (1 bit)
access : read-write

CH6LEVEL : Channel Level
bits : 6 - 6 (1 bit)
access : read-write

CH7LEVEL : Channel Level
bits : 7 - 7 (1 bit)
access : read-write

CH8LEVEL : Channel Level
bits : 8 - 8 (1 bit)
access : read-write

CH9LEVEL : Channel Level
bits : 9 - 9 (1 bit)
access : read-write

CH10LEVEL : Channel Level
bits : 10 - 10 (1 bit)
access : read-write

CH11LEVEL : Channel Level
bits : 11 - 11 (1 bit)
access : read-write

CH12LEVEL : Channel Level
bits : 12 - 12 (1 bit)
access : read-write

CH13LEVEL : Channel Level
bits : 13 - 13 (1 bit)
access : read-write

CH14LEVEL : Channel Level
bits : 14 - 14 (1 bit)
access : read-write

CH15LEVEL : Channel Level
bits : 15 - 15 (1 bit)
access : read-write


CONSUMER_PROTIMER_CC2

CC2 Consumer register
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_PROTIMER_CC2 CONSUMER_PROTIMER_CC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CC2 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_PROTIMER_CC3

CC3 Consumer register
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_PROTIMER_CC3 CONSUMER_PROTIMER_CC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CC3 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_PROTIMER_CC4

CC4 Consumer register
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_PROTIMER_CC4 CONSUMER_PROTIMER_CC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CC4 async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_PROTIMER_LBTPAUSE

LBTPAUSE Consumer register
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_PROTIMER_LBTPAUSE CONSUMER_PROTIMER_LBTPAUSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : LBTPAUSE async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_PROTIMER_LBTSTART

LBTSTART Consumer register
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_PROTIMER_LBTSTART CONSUMER_PROTIMER_LBTSTART read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : LBTSTART async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_PROTIMER_LBTSTOP

LBTSTOP Consumer register
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_PROTIMER_LBTSTOP CONSUMER_PROTIMER_LBTSTOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : LBTSTOP async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_PROTIMER_RTCCTRIGGER

RTCCTRIGGER Consumer register
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_PROTIMER_RTCCTRIGGER CONSUMER_PROTIMER_RTCCTRIGGER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : RTCCTRIGGER async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_PROTIMER_START

START Consumer register
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_PROTIMER_START CONSUMER_PROTIMER_START read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : START async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_PROTIMER_STOP

STOP Consumer register
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_PROTIMER_STOP CONSUMER_PROTIMER_STOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : STOP async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_RAC_CLR

CLR consumer register
address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RAC_CLR CONSUMER_RAC_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CLR async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_RAC_CTIIN0

CTI Consumer register
address_offset : 0xE8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RAC_CTIIN0 CONSUMER_RAC_CTIIN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_RAC_CTIIN1

CTI Consumer register
address_offset : 0xEC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RAC_CTIIN1 CONSUMER_RAC_CTIIN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_RAC_CTIIN2

CTI Consumer register
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RAC_CTIIN2 CONSUMER_RAC_CTIIN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_RAC_CTIIN3

CTI Consumer register
address_offset : 0xF4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RAC_CTIIN3 CONSUMER_RAC_CTIIN3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : CTI async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_RAC_FORCETX

FORCETX Consumer register
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RAC_FORCETX CONSUMER_RAC_FORCETX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : FORCETX async channel select
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_RAC_RXDIS

RXDIS Consumer register
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RAC_RXDIS CONSUMER_RAC_RXDIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : RXDIS async channel select
bits : 0 - 3 (4 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.