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SYSCFG_S

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

CHIPREVHW

CHIPREV

INSTANCEID

CTRL

DMEM0RETNCTRL

CFGSYSTIC

RAMBIASCONF

IPVERSION

RADIORAMRETNCTRL

RADIOECCCTRL

SEQRAMECCADDR

FRCRAMECCADDR

ICACHERAMRETNCTRL

DMEM0PORTMAPSEL

ROOTDATA0

ROOTDATA1

ROOTLOCKSTATUS

ROOTSESWVERSION

CFGRPURATD0

CFGRPURATD2

CFGRPURATD4

CFGRPURATD6

CFGRPURATD8

CFGRPURATD12

IF

IEN


CHIPREVHW

Read to get the hard-wired chip revision.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIPREVHW CHIPREVHW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAJOR FAMILY MINOR

MAJOR : Hardwired Chip Revision Major value
bits : 0 - 5 (6 bit)
access : read-write

FAMILY : Hardwired Chip Family value
bits : 6 - 11 (6 bit)
access : read-write

MINOR : Hardwired Chip Revision Minor value
bits : 12 - 19 (8 bit)
access : read-write


CHIPREV

Read to get the chip revision programmed by feature configuration.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIPREV CHIPREV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAJOR FAMILY MINOR

MAJOR : Chip Revision Major value
bits : 0 - 5 (6 bit)
access : read-write

FAMILY : Chip Family value
bits : 6 - 11 (6 bit)
access : read-write

MINOR : Chip Revision Minor value
bits : 12 - 19 (8 bit)
access : read-write


INSTANCEID

Serial wire instance ID used to differentiate different devices.
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INSTANCEID INSTANCEID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTANCEID

INSTANCEID : Instance ID
bits : 0 - 3 (4 bit)
access : read-write


CTRL

Configure to provide general RAM configuration.
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRFAULTEN CLKDISFAULTEN RAMECCERRFAULTEN

ADDRFAULTEN : Invalid Address Bus Fault Response Enabl
bits : 0 - 0 (1 bit)
access : read-write

CLKDISFAULTEN : Disabled Clkbus Bus Fault Enable
bits : 1 - 1 (1 bit)
access : read-write

RAMECCERRFAULTEN : Two bit ECC error bus fault response ena
bits : 5 - 5 (1 bit)
access : read-write


DMEM0RETNCTRL

Configure to provide general RAM retention configuration.
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMEM0RETNCTRL DMEM0RETNCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMRETNCTRL

RAMRETNCTRL : DMEM0 blockset retention control
bits : 0 - 14 (15 bit)
access : read-write

Enumeration:

0 : ALLON

None of the RAM blocks powered down

16384 : BLK15

Power down RAM block 15 (address range 0x2003C000-0x20040000)

24576 : BLK14TO15

Power down RAM blocks 14 and above (address range 0x20038000-0x20040000)

28672 : BLK13TO15

Power down RAM blocks 13 and above (address range 0x20034000-0x20040000)

30720 : BLK12TO15

Power down RAM blocks 12 and above (address range 0x20030000-0x20040000)

31744 : BLK11TO15

Power down RAM blocks 11 and above (address range 0x2002C000-0x20040000)

32256 : BLK10TO15

Power down RAM blocks 10 and above (address range 0x20028000-0x20040000)

32512 : BLK9TO15

Power down RAM blocks 9 and above (address range 0x20024000-0x20040000)

32640 : BLK8TO15

Power down RAM blocks 8 and above (address range 0x20020000-0x20040000)

32704 : BLK7TO15

Power down RAM blocks 7 and above (address range 0x2001C000-0x20040000)

32736 : BLK6TO15

Power down RAM blocks 6 and above (address range 0x20018000-0x20040000)

32752 : BLK5TO15

Power down RAM blocks 5 and above (address range 0x20014000-0x20040000)

32760 : BLK4TO15

Power down RAM blocks 4 and above (address range 0x20010000-0x20040000)

32764 : BLK3TO15

Power down RAM blocks 3 and above (address range 0x2000C000-0x20040000)

32766 : BLK2TO15

Power down RAM blocks 2 and above (address range 0x20008000-0x20040000)

32767 : BLK1TO15

Power down RAM blocks 1 and above (address range 0x20004000-0x20040000)

End of enumeration elements list.


CFGSYSTIC

Configure the source of the system tick for the M33.
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGSYSTIC CFGSYSTIC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSTICEXTCLKEN

SYSTICEXTCLKEN : SysTick External Clock Enable
bits : 0 - 0 (1 bit)
access : read-write


RAMBIASCONF

Configure RAM bias configure bits.
address_offset : 0x30C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAMBIASCONF RAMBIASCONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMBIASCTRL

RAMBIASCTRL : RAM Bias Control
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : No

None

1 : VSB100

Voltage Source Bias 100mV

2 : VSB200

Voltage Source Bias 200mV

4 : VSB300

Voltage Source Bias 300mV

8 : VSB400

Voltage Source Bias 400mV

End of enumeration elements list.


IPVERSION

No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : New BitField
bits : 0 - 31 (32 bit)
access : read-only


RADIORAMRETNCTRL

Configure SEQRAM Retention controls.
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RADIORAMRETNCTRL RADIORAMRETNCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEQRAMRETNCTRL FRCRAMRETNCTRL

SEQRAMRETNCTRL : SEQRAM Retention Control
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : ALLON

SEQRAM not powered down

1 : BLK0

Power down SEQRAM block 0

2 : BLK1

Power down SEQRAM block 1

3 : ALLOFF

Power down all SEQRAM blocks

End of enumeration elements list.

FRCRAMRETNCTRL : FRCRAM Retention Control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : ALLON

FRCRAM not powered down

1 : ALLOFF

Power down FRCRAM

End of enumeration elements list.


RADIOECCCTRL

Configure to set RAM ECC control.
address_offset : 0x408 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RADIOECCCTRL RADIOECCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEQRAMECCEN SEQRAMECCEWEN FRCRAMECCEN FRCRAMECCEWEN

SEQRAMECCEN : SEQRAM ECC Enable
bits : 0 - 0 (1 bit)
access : read-write

SEQRAMECCEWEN : SEQRAM ECC Error Writeback Enable
bits : 1 - 1 (1 bit)
access : read-write

FRCRAMECCEN : FRCRAM ECC Enable
bits : 8 - 8 (1 bit)
access : read-write

FRCRAMECCEWEN : FRCRAM ECC Error Writeback Enable
bits : 9 - 9 (1 bit)
access : read-write


SEQRAMECCADDR

Read to get status of the SEQRAM ECC error address.
address_offset : 0x410 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SEQRAMECCADDR SEQRAMECCADDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEQRAMECCADDR

SEQRAMECCADDR : SEQRAM ECC Address
bits : 0 - 31 (32 bit)
access : read-only


FRCRAMECCADDR

Read to get status of the FRCRAM ECC error address.
address_offset : 0x414 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FRCRAMECCADDR FRCRAMECCADDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCRAMECCADDR

FRCRAMECCADDR : FRCRAM ECC Error Address
bits : 0 - 31 (32 bit)
access : read-only


ICACHERAMRETNCTRL

Configure Host ICACHERAM retention configuration.
address_offset : 0x418 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACHERAMRETNCTRL ICACHERAMRETNCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMRETNCTRL

RAMRETNCTRL : ICACHERAM Retention control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : ALLON

None of the Host ICACHE RAM blocks powered down

1 : ALLOFF

Power down all Host ICACHE RAM blocks

End of enumeration elements list.


DMEM0PORTMAPSEL

Configure DMEM0 port remap selection.
address_offset : 0x41C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMEM0PORTMAPSEL DMEM0PORTMAPSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDMAPORTSEL SRWAESPORTSEL AHBSRWPORTSEL SRWECA0PORTSEL SRWECA1PORTSEL MVPAHBDATA0PORTSEL MVPAHBDATA1PORTSEL MVPAHBDATA2PORTSEL

LDMAPORTSEL : LDMA portmap selection
bits : 0 - 1 (2 bit)
access : read-write

SRWAESPORTSEL : SRWAES portmap selection
bits : 2 - 3 (2 bit)
access : read-write

AHBSRWPORTSEL : AHBSRW portmap selection
bits : 4 - 5 (2 bit)
access : read-write

SRWECA0PORTSEL : SRWECA0 portmap selection
bits : 6 - 7 (2 bit)
access : read-write

SRWECA1PORTSEL : SRWECA1 portmap selection
bits : 8 - 9 (2 bit)
access : read-write

MVPAHBDATA0PORTSEL : MVPAHBDATA0 portmap selection
bits : 10 - 11 (2 bit)
access : read-write

MVPAHBDATA1PORTSEL : MVPAHBDATA1 portmap selection
bits : 12 - 13 (2 bit)
access : read-write

MVPAHBDATA2PORTSEL : MVPAHBDATA2 portmap selection
bits : 14 - 15 (2 bit)
access : read-write


ROOTDATA0

Generic data space for user to pass to root, e.g., address of struct in mem
address_offset : 0x600 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROOTDATA0 ROOTDATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 31 (32 bit)
access : read-write


ROOTDATA1

Generic data space for user to pass to root, e.g., address of struct in mem
address_offset : 0x604 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROOTDATA1 ROOTDATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 31 (32 bit)
access : read-write


ROOTLOCKSTATUS

This register returns the status of the SE managed locks.
address_offset : 0x608 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ROOTLOCKSTATUS ROOTLOCKSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSLOCK REGLOCK MFRLOCK ROOTDBGLOCK USERDBGAPLOCK USERDBGLOCK USERNIDLOCK USERSPIDLOCK USERSPNIDLOCK RADIOIDBGLOCK RADIONIDBGLOCK EFUSEUNLOCKED

BUSLOCK : Bus Lock
bits : 0 - 0 (1 bit)
access : read-only

REGLOCK : Register Lock
bits : 1 - 1 (1 bit)
access : read-only

MFRLOCK : Manufacture Lock
bits : 2 - 2 (1 bit)
access : read-only

ROOTDBGLOCK : Root Debug Lock
bits : 8 - 8 (1 bit)
access : read-only

USERDBGAPLOCK : User Debug Access Port Lock
bits : 16 - 16 (1 bit)
access : read-only

USERDBGLOCK : User Invasive Debug Lock
bits : 17 - 17 (1 bit)
access : read-only

USERNIDLOCK : User Non-invasive Debug Lock
bits : 18 - 18 (1 bit)
access : read-only

USERSPIDLOCK : User Secure Invasive Debug Lock
bits : 19 - 19 (1 bit)
access : read-only

USERSPNIDLOCK : User Secure Non-invasive Debug Lock
bits : 20 - 20 (1 bit)
access : read-only

RADIOIDBGLOCK : Radio Invasive Debug Lock
bits : 21 - 21 (1 bit)
access : read-only

RADIONIDBGLOCK : Radio Non-invasive Debug Lock
bits : 22 - 22 (1 bit)
access : read-only

EFUSEUNLOCKED : E-Fuse Unlocked
bits : 31 - 31 (1 bit)
access : read-only


ROOTSESWVERSION

SE Software version
address_offset : 0x60C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROOTSESWVERSION ROOTSESWVERSION read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWVERSION

SWVERSION : SW Version
bits : 0 - 31 (32 bit)
access : read-write


CFGRPURATD0

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x610 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGRPURATD0 CFGRPURATD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDIF RATDIEN RATDCHIPREV RATDINSTANCEID RATDCFGSSTCALIB RATDCFGSSYSTIC RATDCFGAHBINTERCNCT

RATDIF : IF Protection Bit
bits : 2 - 2 (1 bit)
access : read-write

RATDIEN : IEN Protection Bit
bits : 3 - 3 (1 bit)
access : read-write

RATDCHIPREV : CHIPREV Protection Bit
bits : 6 - 6 (1 bit)
access : read-write

RATDINSTANCEID : INSTANCEID Protection Bit
bits : 7 - 7 (1 bit)
access : read-write

RATDCFGSSTCALIB : CFGSSTCALIB Protection Bit
bits : 8 - 8 (1 bit)
access : read-write

RATDCFGSSYSTIC : CFGSSYSTIC Protection Bit
bits : 9 - 9 (1 bit)
access : read-write

RATDCFGAHBINTERCNCT : CFGAHBINTERCNCT Protection Bit
bits : 13 - 13 (1 bit)
access : read-write


CFGRPURATD2

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x618 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGRPURATD2 CFGRPURATD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDSESYSROMRM RATDSEPKEROMRM RATDSESYSCTRL RATDSEPKECTRL

RATDSESYSROMRM : SESYSROMRM Protection Bit
bits : 0 - 0 (1 bit)
access : read-write

RATDSEPKEROMRM : SEPKEROMRM Protection Bit
bits : 1 - 1 (1 bit)
access : read-write

RATDSESYSCTRL : SESYSCTRL Protection Bit
bits : 2 - 2 (1 bit)
access : read-write

RATDSEPKECTRL : SEPKECTRL Protection Bit
bits : 3 - 3 (1 bit)
access : read-write


CFGRPURATD4

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x620 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGRPURATD4 CFGRPURATD4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDCTRL RATDDMEM0RETNCTRL

RATDCTRL : CTRL Protection Bit
bits : 0 - 0 (1 bit)
access : read-write

RATDDMEM0RETNCTRL : DMEM0RETNCTRL Protection Bit
bits : 2 - 2 (1 bit)
access : read-write


CFGRPURATD6

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x628 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGRPURATD6 CFGRPURATD6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDRAMRM RATDRAMWM RATDRAMRA RATDRAMBIASCONF RATDRAMLVTEST

RATDRAMRM : RAMRM Protection Bit
bits : 0 - 0 (1 bit)
access : read-write

RATDRAMWM : RAMWM Protection Bit
bits : 1 - 1 (1 bit)
access : read-write

RATDRAMRA : RAMRA Protection Bit
bits : 2 - 2 (1 bit)
access : read-write

RATDRAMBIASCONF : RAMBIASCONF Protection Bit
bits : 3 - 3 (1 bit)
access : read-write

RATDRAMLVTEST : RAMLVTEST Protection Bit
bits : 4 - 4 (1 bit)
access : read-write


CFGRPURATD8

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x630 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGRPURATD8 CFGRPURATD8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDRADIORAMRETNCTRL RATDRADIORAMFEATURE RATDRADIOECCCTRL RATDICACHERAMRETNCTRL RATDDMEM0PORTMAPSEL

RATDRADIORAMRETNCTRL : RADIORAMRETNCTRL Protection Bit
bits : 0 - 0 (1 bit)
access : read-write

RATDRADIORAMFEATURE : RADIORAMFEATURE Protection Bit
bits : 1 - 1 (1 bit)
access : read-write

RATDRADIOECCCTRL : RADIOECCCTRL Protection Bit
bits : 2 - 2 (1 bit)
access : read-write

RATDICACHERAMRETNCTRL : ICACHERAMRETNCTRL Protection Bit
bits : 6 - 6 (1 bit)
access : read-write

RATDDMEM0PORTMAPSEL : DMEM0PORTMAPSEL Protection Bit
bits : 7 - 7 (1 bit)
access : read-write


CFGRPURATD12

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x640 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGRPURATD12 CFGRPURATD12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDROOTDATA0 RATDROOTDATA1 RATDROOTSESWVERSION

RATDROOTDATA0 : DATA0 Protection Bit
bits : 0 - 0 (1 bit)
access : read-write

RATDROOTDATA1 : DATA1 Protection Bit
bits : 1 - 1 (1 bit)
access : read-write

RATDROOTSESWVERSION : SESWVERSION Protection Bit
bits : 3 - 3 (1 bit)
access : read-write


IF

Read to get system status.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW0 SW1 SW2 SW3 FPIOC FPDZC FPUFC FPOFC FPIDC FPIXC HOST2SRWBUSERR SRW2HOSTBUSERR SEQRAMERR1B SEQRAMERR2B FRCRAMERR1B FRCRAMERR2B

SW0 : Software Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

SW1 : Software Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write

SW2 : Software Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write

SW3 : Software Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write

FPIOC : FPU Invalid Operation interrupt flag
bits : 8 - 8 (1 bit)
access : read-write

FPDZC : FPU Divide by zero interrupt flag
bits : 9 - 9 (1 bit)
access : read-write

FPUFC : FPU Underflow interrupt flag
bits : 10 - 10 (1 bit)
access : read-write

FPOFC : FPU Overflow interrupt flag
bits : 11 - 11 (1 bit)
access : read-write

FPIDC : FPU Input denormal interrupt flag
bits : 12 - 12 (1 bit)
access : read-write

FPIXC : FPU Inexact interrupt flag
bits : 13 - 13 (1 bit)
access : read-write

HOST2SRWBUSERR : HOST2SRWBUSERRIF Interrupt Flag
bits : 16 - 16 (1 bit)
access : read-write

SRW2HOSTBUSERR : SRW2HOSTBUSERRIF Interrupt Flag
bits : 17 - 17 (1 bit)
access : read-write

SEQRAMERR1B : SEQRAM Error 1-bit Interrupt Flag
bits : 24 - 24 (1 bit)
access : read-write

SEQRAMERR2B : SEQRAM Error 2-bit Interrupt Flag
bits : 25 - 25 (1 bit)
access : read-write

FRCRAMERR1B : FRCRAM Error 1-bit Interrupt Flag
bits : 28 - 28 (1 bit)
access : read-write

FRCRAMERR2B : FRCRAM Error 2-bit Interrupt Flag
bits : 29 - 29 (1 bit)
access : read-write


IEN

Write to enable interrupts.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW0 SW1 SW2 SW3 FPIOC FPDZC FPUFC FPOFC FPIDC FPIXC HOST2SRWBUSERR SRW2HOSTBUSERR SEQRAMERR1B SEQRAMERR2B FRCRAMERR1B FRCRAMERR2B

SW0 : Software Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

SW1 : Software Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

SW2 : Software Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

SW3 : Software Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

FPIOC : FPU Invalid Operation Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

FPDZC : FPU Divide by zero Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

FPUFC : FPU Underflow Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

FPOFC : FPU Overflow Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

FPIDC : FPU Input denormal Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

FPIXC : FPU Inexact Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write

HOST2SRWBUSERR : HOST2SRWBUSERRIEN Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write

SRW2HOSTBUSERR : SRW2HOSTBUSERRIEN Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write

SEQRAMERR1B : SEQRAM Error 1-bit Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write

SEQRAMERR2B : SEQRAM Error 2-bit Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-write

FRCRAMERR1B : FRCRAM Error 1-bit Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-write

FRCRAMERR2B : FRCRAM Error 2-bit Interrupt Enable
bits : 29 - 29 (1 bit)
access : read-write



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