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DCDC_S

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

IPVERSION

EM23CTRL0

PFMXCTRL

IF

IEN

STATUS

SYNCBUSY

CTRL

LOCK

LOCKSTATUS

EM01CTRL0

RPURATD0

RPURATD1


IPVERSION

IPVERSION
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : IPVERSION
bits : 0 - 31 (32 bit)
access : read-only


EM23CTRL0

EM23 Configurations
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EM23CTRL0 EM23CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPKVAL DRVSPEED

IPKVAL : EM23 Peak Current Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

3 : Load36mA

Ipeak = 90mA, IL = 36mA

4 : Load40mA

Ipeak = 100mA, IL = 40mA

5 : Load44mA

Ipeak = 110mA, IL = 44mA

6 : Load48mA

Ipeak = 120mA, IL = 48mA

7 : Load52mA

Ipeak = 130mA, IL = 52mA

8 : Load56mA

Ipeak = 140mA, IL = 56mA

9 : Load60mA

Ipeak = 150mA, IL = 60mA

End of enumeration elements list.

DRVSPEED : EM23 Drive Speed Setting
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : BEST_EMI

Lowest Efficiency, Lowest EMI.. Small decrease in efficiency from default setting

1 : DEFAULT_SETTING

Default Efficiency, Acceptable EMI level

2 : INTERMEDIATE

Small increase in efficiency from the default setting

3 : BEST_EFFICIENCY

Highest Efficiency, Highest EMI.. Small increase in efficiency from INTERMEDIATE setting

End of enumeration elements list.


PFMXCTRL

PFMX Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFMXCTRL PFMXCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPKVAL IPKTMAXCTRL

IPKVAL : PFMX mode Peak Current Setting
bits : 0 - 3 (4 bit)
access : read-write

IPKTMAXCTRL : Ton_max timeout control
bits : 8 - 12 (5 bit)
access : read-write


IF

Interrupt Flags
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYPSW WARM RUNNING VREGINLOW VREGINHIGH REGULATION TMAX EM4ERR PPMODE PFMXMODE

BYPSW : Bypass Switch Enabled
bits : 0 - 0 (1 bit)
access : read-write

WARM : DCDC Warmup Time Done
bits : 1 - 1 (1 bit)
access : read-write

RUNNING : DCDC Running
bits : 2 - 2 (1 bit)
access : read-write

VREGINLOW : VREGIN below threshold
bits : 3 - 3 (1 bit)
access : read-write

VREGINHIGH : VREGIN above threshold
bits : 4 - 4 (1 bit)
access : read-write

REGULATION : DCDC in regulation
bits : 5 - 5 (1 bit)
access : read-write

TMAX : Ton_max Timeout Reached
bits : 6 - 6 (1 bit)
access : read-write

EM4ERR : EM4 Entry Request Error
bits : 7 - 7 (1 bit)
access : read-write

PPMODE : Entered Pulse Pairing mode
bits : 8 - 8 (1 bit)
access : read-write

PFMXMODE : Entered PFMX mode
bits : 9 - 9 (1 bit)
access : read-write


IEN

Interrupt Enable
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYPSW WARM RUNNING VREGINLOW VREGINHIGH REGULATION TMAX EM4ERR PPMODE PFMXMODE

BYPSW : Bypass Switch Enabled Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

WARM : DCDC Warmup Time Done Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

RUNNING : DCDC Running Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

VREGINLOW : VREGIN below threshold Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

VREGINHIGH : VREGIN above threshold Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

REGULATION : DCDC in Regulation Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

TMAX : Ton_max Timeout Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

EM4ERR : EM4 Entry Req Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

PPMODE : Pulse Pairing Mode Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

PFMXMODE : PFMX Mode Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write


STATUS

DCDC Status Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYPSW WARM RUNNING VREGIN BYPCMPOUT PPMODE PFMXMODE

BYPSW : Bypass Switch is currently enabled
bits : 0 - 0 (1 bit)
access : read-only

WARM : DCDC Warmup Done
bits : 1 - 1 (1 bit)
access : read-only

RUNNING : DCDC is running
bits : 2 - 2 (1 bit)
access : read-only

VREGIN : VREGIN comparator status
bits : 3 - 3 (1 bit)
access : read-only

BYPCMPOUT : Bypass Comparator Output
bits : 4 - 4 (1 bit)
access : read-only

PPMODE : DCDC in pulse-pairing mode
bits : 8 - 8 (1 bit)
access : read-only

PFMXMODE : DCDC in PFMX mode
bits : 9 - 9 (1 bit)
access : read-only


SYNCBUSY

Syncbusy Status Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTRL EM01CTRL0 EM01CTRL1 EM23CTRL0 PFMXCTRL

CTRL : CTRL Sync Busy Status
bits : 0 - 0 (1 bit)
access : read-only

EM01CTRL0 : EM01CTRL0 Sync Busy Status
bits : 1 - 1 (1 bit)
access : read-only

EM01CTRL1 : EM01CTRL1 Sync Bust Status
bits : 2 - 2 (1 bit)
access : read-only

EM23CTRL0 : EM23CTRL0 Sync Busy Status
bits : 3 - 3 (1 bit)
access : read-only

PFMXCTRL : PFMXCTRL Sync Busy Status
bits : 7 - 7 (1 bit)
access : read-only


CTRL

Control
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE IPKTMAXCTRL

MODE : DCDC/Bypass Mode Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : BYPASS

DCDC is OFF, bypass switch is enabled

1 : DCDCREGULATION

Request DCDC regulation, bypass switch disabled

End of enumeration elements list.

IPKTMAXCTRL : Ton_max timeout control
bits : 4 - 8 (5 bit)
access : read-write


LOCK

No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : Configuration Lock Key
bits : 0 - 15 (16 bit)
access : write-only

Enumeration:

43981 : UNLOCKKEY


End of enumeration elements list.


LOCKSTATUS

No Description
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LOCKSTATUS LOCKSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK

LOCK : Lock Status
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

Unlocked State

1 : LOCKED

LOCKED STATE

End of enumeration elements list.


EM01CTRL0

EM01 Configurations
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EM01CTRL0 EM01CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPKVAL DRVSPEED

IPKVAL : EM01 Peak Current Setting
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

3 : Load36mA

Ipeak = 90mA, IL = 36mA

4 : Load40mA

Ipeak = 100mA, IL = 40mA

5 : Load44mA

Ipeak = 110mA, IL = 44mA

6 : Load48mA

Ipeak = 120mA, IL = 48mA

7 : Load52mA

Ipeak = 130mA, IL = 52mA

8 : Load56mA

Ipeak = 140mA, IL = 56mA

9 : Load60mA

Ipeak = 150mA, IL = 60mA

End of enumeration elements list.

DRVSPEED : EM01 Drive Speed Setting
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : BEST_EMI

Lowest Efficiency, Lowest EMI.. Small decrease in efficiency from default setting

1 : DEFAULT_SETTING

Default Efficiency, Acceptable EMI level

2 : INTERMEDIATE

Small increase in efficiency from the default setting

3 : BEST_EFFICIENCY

Highest Efficiency, Highest EMI.. Small increase in efficiency from INTERMEDIATE setting

End of enumeration elements list.


RPURATD0

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPURATD0 RPURATD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDCTRL RATDEM01CTRL0 RATDIZCTRL RATDEM23CTRL0 RATDEM01CTRL1 RATDEM23CTRL1 RATDPPCFG RATDPFMXCTRL RATDTRANSCFG RATDIF RATDIEN RATDLOCK RATDTRIM0 RATDTRIM1 RATDTRIM2 RATDCFG RATDDCDCFORCE RATDDBUSTEST RATDDCDCVCMPTEST RATDIZCTEST

RATDCTRL : CTRL Protection Bit
bits : 1 - 1 (1 bit)
access : read-write

RATDEM01CTRL0 : EM01CTRL0 Protection Bit
bits : 2 - 2 (1 bit)
access : read-write

RATDIZCTRL : IZCTRL Protection Bit
bits : 3 - 3 (1 bit)
access : read-write

RATDEM23CTRL0 : EM23CTRL0 Protection Bit
bits : 4 - 4 (1 bit)
access : read-write

RATDEM01CTRL1 : EM01CTRL1 Protection Bit
bits : 5 - 5 (1 bit)
access : read-write

RATDEM23CTRL1 : EM23CTRL1 Protection Bit
bits : 6 - 6 (1 bit)
access : read-write

RATDPPCFG : PPCFG Protection Bit
bits : 7 - 7 (1 bit)
access : read-write

RATDPFMXCTRL : PFMXCTRL Protection Bit
bits : 8 - 8 (1 bit)
access : read-write

RATDTRANSCFG : TRANSCFG Protection Bit
bits : 9 - 9 (1 bit)
access : read-write

RATDIF : IF Protection Bit
bits : 10 - 10 (1 bit)
access : read-write

RATDIEN : IEN Protection Bit
bits : 11 - 11 (1 bit)
access : read-write

RATDLOCK : LOCK Protection Bit
bits : 16 - 16 (1 bit)
access : read-write

RATDTRIM0 : TRIM0 Protection Bit
bits : 20 - 20 (1 bit)
access : read-write

RATDTRIM1 : TRIM1 Protection Bit
bits : 21 - 21 (1 bit)
access : read-write

RATDTRIM2 : TRIM2 Protection Bit
bits : 22 - 22 (1 bit)
access : read-write

RATDCFG : CFG Protection Bit
bits : 23 - 23 (1 bit)
access : read-write

RATDDCDCFORCE : DCDCFORCE Protection Bit
bits : 28 - 28 (1 bit)
access : read-write

RATDDBUSTEST : DBUSTEST Protection Bit
bits : 29 - 29 (1 bit)
access : read-write

RATDDCDCVCMPTEST : DCDCVCMPTEST Protection Bit
bits : 30 - 30 (1 bit)
access : read-write

RATDIZCTEST : IZCTEST Protection Bit
bits : 31 - 31 (1 bit)
access : read-write


RPURATD1

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPURATD1 RPURATD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDDCDCTEST

RATDDCDCTEST : DCDCTEST Protection Bit
bits : 0 - 0 (1 bit)
access : read-write



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