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EMU_NS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

DECBOD

EFPIF

EFPIEN

RPURATD0

RPURATD1

RPURATD2

RPURATD3

BOD3SENSE

VREGVDDCMPCTRL

PD1PARETCTRL

IPVERSION

LOCK

IF

IEN

EM4CTRL

CMD

CTRL

TEMPLIMITS

STATUS

TEMP

RSTCTRL

RSTCAUSE

DGIF

DGIEN

SEQIF

SEQIEN


DECBOD

No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DECBOD DECBOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DECBODEN DECBODMASK DECOVMBODEN DECOVMBODMASK

DECBODEN : DECBOD enable
bits : 0 - 0 (1 bit)
access : read-write

DECBODMASK : DECBOD Mask
bits : 1 - 1 (1 bit)
access : read-write

DECOVMBODEN : Over Voltage Monitor enable
bits : 4 - 4 (1 bit)
access : read-write

DECOVMBODMASK : Over Voltage Monitor Mask
bits : 5 - 5 (1 bit)
access : read-write


EFPIF

No Description
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EFPIF EFPIF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFPIF

EFPIF : EFP Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write


EFPIEN

No Description
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EFPIEN EFPIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFPIEN

EFPIEN : EFP Interrupt enable
bits : 0 - 0 (1 bit)
access : read-write


RPURATD0

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x18C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPURATD0 RPURATD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDLDREG RATDDVDDLEBOD RATDVLMTHV RATDDVDDBOD RATDDECBOD RATDHDREG RATDRETREG RATDBOD3SENSETRIM RATDBOD3SENSE RATDISBIAS RATDISBIASTRIM RATDISBIASVREFREGTRIM RATDISBIASVREFLVBODTRIM RATDPFMBYP RATDPFMBYPCTRL RATDPD1PARETCTRL RATDPD0PWRCTRL RATDPD0PWREM2CTRL RATDLOCK RATDIF RATDIEN RATDEM4CTRL RATDCMD RATDCTRL RATDTEMPLIMITS RATDTEMPLIMITSDG

RATDLDREG : LDREG Protection Bit
bits : 0 - 0 (1 bit)
access : read-write

RATDDVDDLEBOD : DVDDLEBOD Protection Bit
bits : 1 - 1 (1 bit)
access : read-write

RATDVLMTHV : VLMTHV Protection Bit
bits : 2 - 2 (1 bit)
access : read-write

RATDDVDDBOD : DVDDBOD Protection Bit
bits : 3 - 3 (1 bit)
access : read-write

RATDDECBOD : DECBOD Protection Bit
bits : 4 - 4 (1 bit)
access : read-write

RATDHDREG : HDREG Protection Bit
bits : 5 - 5 (1 bit)
access : read-write

RATDRETREG : RETREG Protection Bit
bits : 6 - 6 (1 bit)
access : read-write

RATDBOD3SENSETRIM : BOD3SENSETRIM Protection Bit
bits : 7 - 7 (1 bit)
access : read-write

RATDBOD3SENSE : BOD3SENSE Protection Bit
bits : 8 - 8 (1 bit)
access : read-write

RATDISBIAS : ISBIAS Protection Bit
bits : 9 - 9 (1 bit)
access : read-write

RATDISBIASTRIM : ISBIASTRIM Protection Bit
bits : 10 - 10 (1 bit)
access : read-write

RATDISBIASVREFREGTRIM : ISBIASVREFREGTRIM Protection Bit
bits : 11 - 11 (1 bit)
access : read-write

RATDISBIASVREFLVBODTRIM : ISBIASVREFLVBODTRIM Protection Bit
bits : 12 - 12 (1 bit)
access : read-write

RATDPFMBYP : PFMBYP Protection Bit
bits : 14 - 14 (1 bit)
access : read-write

RATDPFMBYPCTRL : PFMBYPCTRL Protection Bit
bits : 15 - 15 (1 bit)
access : read-write

RATDPD1PARETCTRL : PD1PARETCTRL Protection Bit
bits : 16 - 16 (1 bit)
access : read-write

RATDPD0PWRCTRL : PD0PWRCTRL Protection Bit
bits : 17 - 17 (1 bit)
access : read-write

RATDPD0PWREM2CTRL : PD0PWREM2CTRL Protection Bit
bits : 18 - 18 (1 bit)
access : read-write

RATDLOCK : LOCK Protection Bit
bits : 24 - 24 (1 bit)
access : read-write

RATDIF : IF Protection Bit
bits : 25 - 25 (1 bit)
access : read-write

RATDIEN : IEN Protection Bit
bits : 26 - 26 (1 bit)
access : read-write

RATDEM4CTRL : EM4CTRL Protection Bit
bits : 27 - 27 (1 bit)
access : read-write

RATDCMD : CMD Protection Bit
bits : 28 - 28 (1 bit)
access : read-write

RATDCTRL : CTRL Protection Bit
bits : 29 - 29 (1 bit)
access : read-write

RATDTEMPLIMITS : TEMPLIMITS Protection Bit
bits : 30 - 30 (1 bit)
access : read-write

RATDTEMPLIMITSDG : TEMPLIMITSDG Protection Bit
bits : 31 - 31 (1 bit)
access : read-write


RPURATD1

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x190 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPURATD1 RPURATD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDTEMPLIMITSSE RATDTESTCTRL RATDRMUCTRL RATDDGIF RATDDGIEN RATDSEQIF RATDSEQIEN RATDDELAYCFG RATDTESTLOCK RATDAUXCTRL RATDISBIASCONF RATDISBIASCALOVR RATDISBIASPERIOD RATDISBIASTEMPCOMPRATE RATDISBIASTEMPCOMPTHR RATDISBIASPFMREFRESHCFG RATDISBIASREFRESHCFG RATDISBIASTEMPCONST RATDVSBTEMPCOMP RATDVSBTEMPCOMPTHR RATDRETREGTEMPCOMP

RATDTEMPLIMITSSE : TEMPLIMITSSE Protection Bit
bits : 0 - 0 (1 bit)
access : read-write

RATDTESTCTRL : TESTCTRL Protection Bit
bits : 3 - 3 (1 bit)
access : read-write

RATDRMUCTRL : RMUCTRL Protection Bit
bits : 4 - 4 (1 bit)
access : read-write

RATDDGIF : DGIF Protection Bit
bits : 8 - 8 (1 bit)
access : read-write

RATDDGIEN : DGIEN Protection Bit
bits : 9 - 9 (1 bit)
access : read-write

RATDSEQIF : SEQIF Protection Bit
bits : 10 - 10 (1 bit)
access : read-write

RATDSEQIEN : SEQIEN Protection Bit
bits : 11 - 11 (1 bit)
access : read-write

RATDDELAYCFG : DELAYCFG Protection Bit
bits : 12 - 12 (1 bit)
access : read-write

RATDTESTLOCK : TESTLOCK Protection Bit
bits : 13 - 13 (1 bit)
access : read-write

RATDAUXCTRL : AUXCTRL Protection Bit
bits : 14 - 14 (1 bit)
access : read-write

RATDISBIASCONF : ISBIASCONF Protection Bit
bits : 16 - 16 (1 bit)
access : read-write

RATDISBIASCALOVR : ISBIASCALOVR Protection Bit
bits : 17 - 17 (1 bit)
access : read-write

RATDISBIASPERIOD : ISBIASPERIOD Protection Bit
bits : 18 - 18 (1 bit)
access : read-write

RATDISBIASTEMPCOMPRATE : ISBIASTEMPCOMPRATE Protection Bit
bits : 19 - 19 (1 bit)
access : read-write

RATDISBIASTEMPCOMPTHR : ISBIASTEMPCOMPTHR Protection Bit
bits : 20 - 20 (1 bit)
access : read-write

RATDISBIASPFMREFRESHCFG : ISBIASPFMREFRESHCFG Protection Bit
bits : 22 - 22 (1 bit)
access : read-write

RATDISBIASREFRESHCFG : ISBIASREFRESHCFG Protection Bit
bits : 23 - 23 (1 bit)
access : read-write

RATDISBIASTEMPCONST : ISBIASTEMPCONST Protection Bit
bits : 24 - 24 (1 bit)
access : read-write

RATDVSBTEMPCOMP : VSBTEMPCOMP Protection Bit
bits : 26 - 26 (1 bit)
access : read-write

RATDVSBTEMPCOMPTHR : VSBTEMPCOMPTHR Protection Bit
bits : 27 - 27 (1 bit)
access : read-write

RATDRETREGTEMPCOMP : RETREGTEMPCOMP Protection Bit
bits : 28 - 28 (1 bit)
access : read-write


RPURATD2

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x194 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPURATD2 RPURATD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDEFPIF RATDEFPIEN RATDEFPCTRL

RATDEFPIF : EFPIF Protection Bit
bits : 0 - 0 (1 bit)
access : read-write

RATDEFPIEN : EFPIEN Protection Bit
bits : 1 - 1 (1 bit)
access : read-write

RATDEFPCTRL : EFPCTRL Protection Bit
bits : 2 - 2 (1 bit)
access : read-write


RPURATD3

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x198 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPURATD3 RPURATD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDROOTCTRL

RATDROOTCTRL : ROOTCTRL Protection Bit
bits : 2 - 2 (1 bit)
access : read-write


BOD3SENSE

No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOD3SENSE BOD3SENSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVDDBODEN VDDIO0BODEN VDDIO1BODEN

AVDDBODEN : AVDD BOD enable
bits : 0 - 0 (1 bit)
access : read-write

VDDIO0BODEN : VDDIO0 BOD enable
bits : 1 - 1 (1 bit)
access : read-write

VDDIO1BODEN : VDDIO1 BOD enable
bits : 2 - 2 (1 bit)
access : read-write


VREGVDDCMPCTRL

No Description
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREGVDDCMPCTRL VREGVDDCMPCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREGINCMPEN THRESSEL

VREGINCMPEN : VREGVDD comparator enable
bits : 0 - 0 (1 bit)
access : read-write

THRESSEL : VREGVDD comparator threshold programming
bits : 1 - 2 (2 bit)
access : read-write


PD1PARETCTRL

No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD1PARETCTRL PD1PARETCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD1PARETDIS

PD1PARETDIS : Disable PD1 Partial Retention
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

1 : PERIPHNORETAIN

Retain associated registers when in EM2/3

2 : RADIONORETAIN

Bit[1]. When set, do not retain RADIO associated registers when in EM2/3

End of enumeration elements list.


IPVERSION

IP Version
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : IP Version
bits : 0 - 31 (32 bit)
access : read-only


LOCK

No Description
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : Lock Key
bits : 0 - 15 (16 bit)
access : write-only

Enumeration:

44520 : UNLOCK

Unlock EMU register

End of enumeration elements list.


IF

No Description
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVDDBOD IOVDD0BOD EM23WAKEUP VSCALEDONE TEMPAVG TEMP TEMPLOW TEMPHIGH

AVDDBOD : AVDD BOD Interrupt flag
bits : 16 - 16 (1 bit)
access : read-write

IOVDD0BOD : VDDIO0 BOD Interrupt flag
bits : 17 - 17 (1 bit)
access : read-write

EM23WAKEUP : EM23 Wake up Interrupt flag
bits : 24 - 24 (1 bit)
access : read-write

VSCALEDONE : Vscale done Interrupt flag
bits : 25 - 25 (1 bit)
access : read-write

TEMPAVG : Temperature Average Interrupt flag
bits : 27 - 27 (1 bit)
access : read-write

TEMP : Temperature Interrupt flag
bits : 29 - 29 (1 bit)
access : read-write

TEMPLOW : Temperature low Interrupt flag
bits : 30 - 30 (1 bit)
access : read-write

TEMPHIGH : Temperature high Interrupt flag
bits : 31 - 31 (1 bit)
access : read-write


IEN

No Description
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVDDBOD IOVDD0BOD EM23WAKEUP VSCALEDONE TEMPAVG TEMP TEMPLOW TEMPHIGH

AVDDBOD : AVDD BOD Interrupt enable
bits : 16 - 16 (1 bit)
access : read-write

IOVDD0BOD : VDDIO0 BOD Interrupt enable
bits : 17 - 17 (1 bit)
access : read-write

EM23WAKEUP : EM23 Wake up Interrupt enable
bits : 24 - 24 (1 bit)
access : read-write

VSCALEDONE : Vscale done Interrupt enable
bits : 25 - 25 (1 bit)
access : read-write

TEMPAVG : Temperature Interrupt enable
bits : 27 - 27 (1 bit)
access : read-write

TEMP : Temperature Interrupt enable
bits : 29 - 29 (1 bit)
access : read-write

TEMPLOW : Temperature low Interrupt enable
bits : 30 - 30 (1 bit)
access : read-write

TEMPHIGH : Temperature high Interrupt enable
bits : 31 - 31 (1 bit)
access : read-write


EM4CTRL

No Description
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EM4CTRL EM4CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM4ENTRY EM4IORETMODE BOD3SENSEEM4WU

EM4ENTRY : EM4 entry request
bits : 0 - 1 (2 bit)
access : read-write

EM4IORETMODE : EM4 IO retention mode
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : DISABLE

No Retention: Pads enter reset state when entering EM4

1 : EM4EXIT

Retention through EM4: Pads enter reset state when exiting EM4

2 : SWUNLATCH

Retention through EM4 and Wakeup: software writes UNLATCH register to remove retention

End of enumeration elements list.

BOD3SENSEEM4WU : Set BOD3SENSE as EM4 wakeup
bits : 8 - 8 (1 bit)
access : read-write


CMD

No Description
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM4UNLATCH TEMPAVGREQ EM01VSCALE1 EM01VSCALE2 RSTCAUSECLR

EM4UNLATCH : EM4 unlatch
bits : 1 - 1 (1 bit)
access : write-only

TEMPAVGREQ : Temperature Average Request
bits : 4 - 4 (1 bit)
access : write-only

EM01VSCALE1 : Scale voltage to Vscale1
bits : 10 - 10 (1 bit)
access : write-only

EM01VSCALE2 : Scale voltage to Vscale2
bits : 11 - 11 (1 bit)
access : write-only

RSTCAUSECLR : Reset Cause Clear
bits : 17 - 17 (1 bit)
access : write-only


CTRL

No Description
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM2DBGEN TEMPAVGNUM EM23VSCALE FLASHPWRUPONDEMAND EFPDIRECTMODEEN EFPDRVDECOUPLE EFPDRVDVDD

EM2DBGEN : Enable debugging in EM2
bits : 0 - 0 (1 bit)
access : read-write

TEMPAVGNUM : Averaged Temperature samples num
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : N16

16 measurements

1 : N64

64 measurements

End of enumeration elements list.

EM23VSCALE : EM2/EM3 Vscale
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : VSCALE0

VSCALE0. 0.9v

1 : VSCALE1

VSCALE1. 1.0v

2 : VSCALE2

VSCALE2. 1.1v

End of enumeration elements list.

FLASHPWRUPONDEMAND : Enable flash on demand wakeup
bits : 16 - 16 (1 bit)
access : read-write

EFPDIRECTMODEEN : EFP Direct Mode Enable
bits : 29 - 29 (1 bit)
access : read-write

EFPDRVDECOUPLE : EFP drives DECOUPLE
bits : 30 - 30 (1 bit)
access : read-write

EFPDRVDVDD : EFP drives DVDD
bits : 31 - 31 (1 bit)
access : read-write


TEMPLIMITS

No Description
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEMPLIMITS TEMPLIMITS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEMPLOW TEMPHIGH

TEMPLOW : Temp Low limit
bits : 0 - 8 (9 bit)
access : read-write

TEMPHIGH : Temp High limit
bits : 16 - 24 (9 bit)
access : read-write


STATUS

No Description
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK FIRSTTEMPDONE TEMPACTIVE TEMPAVGACTIVE VSCALEBUSY VSCALEFAILED VSCALE RACACTIVE EM4IORET EM2ENTERED

LOCK : Lock status
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

All EMU lockable registers are unlocked.

1 : LOCKED

All EMU lockable registers are locked.

End of enumeration elements list.

FIRSTTEMPDONE : First Temp done
bits : 1 - 1 (1 bit)
access : read-only

TEMPACTIVE : Temp active
bits : 2 - 2 (1 bit)
access : read-only

TEMPAVGACTIVE : Temp Average active
bits : 3 - 3 (1 bit)
access : read-only

VSCALEBUSY : Vscale busy
bits : 4 - 4 (1 bit)
access : read-only

VSCALEFAILED : Vscale failed
bits : 5 - 5 (1 bit)
access : read-only

VSCALE : Vscale status
bits : 6 - 7 (2 bit)
access : read-only

Enumeration:

0 : VSCALE0

Voltage scaling set to 0.9v

1 : VSCALE1

Voltage scaling set to 1.0v

2 : VSCALE2

Voltage scaling set to 1.1v

End of enumeration elements list.

RACACTIVE : RAC active
bits : 8 - 8 (1 bit)
access : read-only

EM4IORET : EM4 IO retention status
bits : 9 - 9 (1 bit)
access : read-only

EM2ENTERED : EM2 entered
bits : 10 - 10 (1 bit)
access : read-only


TEMP

No Description
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TEMP TEMP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEMPLSB TEMP TEMPAVG

TEMPLSB : Temperature measured decimal part
bits : 0 - 1 (2 bit)
access : read-only

TEMP : Temperature measured
bits : 2 - 10 (9 bit)
access : read-only

TEMPAVG : Averaged Temperature
bits : 16 - 26 (11 bit)
access : read-only


RSTCTRL

No Description
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTCTRL RSTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOG0RMODE SYSRMODE LOCKUPRMODE AVDDBODRMODE IOVDD0BODRMODE DECBODRMODE

WDOG0RMODE : Enable WDOG0 reset
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Reset request is blocked

1 : ENABLED

The entire device is reset except some EMU registers

End of enumeration elements list.

SYSRMODE : Enable M33 System reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Reset request is blocked

1 : ENABLED

Device is reset except some EMU registers

End of enumeration elements list.

LOCKUPRMODE : Enable M33 Lockup reset
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Reset Request is Block

1 : ENABLED

The entire device is reset except some EMU registers

End of enumeration elements list.

AVDDBODRMODE : Enable AVDD BOD reset
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Reset Request is block

1 : ENABLED

The entire device is reset except some EMU registers

End of enumeration elements list.

IOVDD0BODRMODE : Enable VDDIO0 BOD reset
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Reset request is blocked

1 : ENABLED

The entire device is reset except some EMU registers

End of enumeration elements list.

DECBODRMODE : Enable DECBOD reset
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Reset request is blocked

1 : ENABLED

The entire device is reset

End of enumeration elements list.


RSTCAUSE

No Description
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RSTCAUSE RSTCAUSE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POR PIN EM4 WDOG0 WDOG1 LOCKUP SYSREQ DVDDBOD DVDDLEBOD DECBOD AVDDBOD IOVDD0BOD VREGIN

POR : Power On Reset
bits : 0 - 0 (1 bit)
access : read-only

PIN : Pin Reset
bits : 1 - 1 (1 bit)
access : read-only

EM4 : EM4 Wakeup Reset
bits : 2 - 2 (1 bit)
access : read-only

WDOG0 : Watchdog 0 Reset
bits : 3 - 3 (1 bit)
access : read-only

WDOG1 : Watchdog 1 Reset
bits : 4 - 4 (1 bit)
access : read-only

LOCKUP : M33 Core Lockup Reset
bits : 5 - 5 (1 bit)
access : read-only

SYSREQ : M33 Core Sys Reset
bits : 6 - 6 (1 bit)
access : read-only

DVDDBOD : HVBOD Reset
bits : 7 - 7 (1 bit)
access : read-only

DVDDLEBOD : LEBOD Reset
bits : 8 - 8 (1 bit)
access : read-only

DECBOD : LVBOD Reset
bits : 9 - 9 (1 bit)
access : read-only

AVDDBOD : LEBOD1 Reset
bits : 10 - 10 (1 bit)
access : read-only

IOVDD0BOD : LEBOD2 Reset
bits : 11 - 11 (1 bit)
access : read-only

VREGIN : DCDC VREGIN comparator
bits : 31 - 31 (1 bit)
access : read-only


DGIF

No Description
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGIF DGIF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM23WAKEUPDGIF TEMPDGIF TEMPLOWDGIF TEMPHIGHDGIF

EM23WAKEUPDGIF : EM23 Wake up Interrupt flag
bits : 24 - 24 (1 bit)
access : read-write

TEMPDGIF : Temperature Interrupt flag
bits : 29 - 29 (1 bit)
access : read-write

TEMPLOWDGIF : Temperature low Interrupt flag
bits : 30 - 30 (1 bit)
access : read-write

TEMPHIGHDGIF : Temperature high Interrupt flag
bits : 31 - 31 (1 bit)
access : read-write


DGIEN

No Description
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGIEN DGIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM23WAKEUPDGIEN TEMPDGIEN TEMPLOWDGIEN TEMPHIGHDGIEN

EM23WAKEUPDGIEN : EM23 Wake up Interrupt enable
bits : 24 - 24 (1 bit)
access : read-write

TEMPDGIEN : Temperature Interrupt enable
bits : 29 - 29 (1 bit)
access : read-write

TEMPLOWDGIEN : Temperature low Interrupt enable
bits : 30 - 30 (1 bit)
access : read-write

TEMPHIGHDGIEN : Temperature high Interrupt enable
bits : 31 - 31 (1 bit)
access : read-write


SEQIF

No Description
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQIF SEQIF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEMP TEMPLOW TEMPHIGH

TEMP : Temperature Interrupt flag
bits : 29 - 29 (1 bit)
access : read-write

TEMPLOW : Temperature low Interrupt flag
bits : 30 - 30 (1 bit)
access : read-write

TEMPHIGH : Temperature high Interrupt flag
bits : 31 - 31 (1 bit)
access : read-write


SEQIEN

No Description
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQIEN SEQIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEMP TEMPLOW TEMPHIGH

TEMP : Temperature Interrupt enable
bits : 29 - 29 (1 bit)
access : read-write

TEMPLOW : Temperature low Interrupt enable
bits : 30 - 30 (1 bit)
access : read-write

TEMPHIGH : Temperature high Interrupt enable
bits : 31 - 31 (1 bit)
access : read-write



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