\n

DMEM_NS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

IPVERSION

ECCERRADDR1

ECCERRADDR2

ECCERRADDR3

ECCMERRIND

IF

IEN

RAMBANKSVALID

CFGSRTOP

CFGSRMAP

CFGIU0MAP

CFGIU1MAP

CFGIU2MAP

CMD

CFGIU3MAP

RPURATD0

CTRL

ECCERRADDR0


IPVERSION

No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : New BitField
bits : 0 - 1 (2 bit)
access : read-only


ECCERRADDR1

No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECCERRADDR1 ECCERRADDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : ECC Error Address
bits : 0 - 31 (32 bit)
access : read-only


ECCERRADDR2

No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECCERRADDR2 ECCERRADDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : ECC Error Address
bits : 0 - 31 (32 bit)
access : read-only


ECCERRADDR3

No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECCERRADDR3 ECCERRADDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : ECC Error Address
bits : 0 - 31 (32 bit)
access : read-only


ECCMERRIND

No Description
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECCMERRIND ECCMERRIND read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3

P0 : Multiple ECC errors on AHB port 0
bits : 0 - 0 (1 bit)
access : read-only

P1 : Multiple ECC errors on AHB port 1
bits : 1 - 1 (1 bit)
access : read-only

P2 : Multiple ECC errors on AHB port 2
bits : 2 - 2 (1 bit)
access : read-only

P3 : Multiple ECC errors on AHB port 2
bits : 3 - 3 (1 bit)
access : read-only


IF

No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB0ERR1B AHB1ERR1B AHB2ERR1B AHB3ERR1B AHB0ERR2B AHB1ERR2B AHB2ERR2B AHB3ERR2B

AHB0ERR1B : AHB0 1-bit ECC Error Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

AHB1ERR1B : AHB1 1-bit ECC Error Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write

AHB2ERR1B : AHB2 1-bit ECC Error Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write

AHB3ERR1B : AHB3 1-bit ECC Error Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write

AHB0ERR2B : AHB0 2-bit ECC Error Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write

AHB1ERR2B : AHB1 2-bit ECC Error Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write

AHB2ERR2B : AHB2 2-bit ECC Error Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write

AHB3ERR2B : AHB3 2-bit ECC Error Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write


IEN

No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB0ERR1B AHB1ERR1B AHB2ERR1B AHB3ERR1B AHB0ERR2B AHB1ERR2B AHB2ERR2B AHB3ERR2B

AHB0ERR1B : AHB0 1-bit ECC Error Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

AHB1ERR1B : AHB1 1-bit ECC Error Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

AHB2ERR1B : AHB2 1-bit ECC Error Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

AHB3ERR1B : AHB3 1-bit ECC Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

AHB0ERR2B : AHB0 2-bit ECC Error Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

AHB1ERR2B : AHB1 2-bit ECC Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

AHB2ERR2B : AHB2 2-bit ECC Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

AHB3ERR2B : AHB3 2-bit ECC Error Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write


RAMBANKSVALID

No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAMBANKSVALID RAMBANKSVALID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMBANKSVALID

RAMBANKSVALID : Enable bits for RAM banks 0-31
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

1 : BLK0

Enable RAM block0

3 : BLK0TO1

Enable RAM block0 to block1

7 : BLK0TO2

Enable RAM block0 to block2

15 : BLK0TO3

Enable RAM block0 to block3

31 : BLK0TO4

Enable RAM block0 to block4

63 : BLK0TO5

Enable RAM block0 to block5

127 : BLK0TO6

Enable RAM block0 to block6

255 : BLK0TO7

Enable RAM block0 to block7

511 : BLK0TO8

Enable RAM block0 to block8

1023 : BLK0TO9

Enable RAM block0 to block9

2047 : BLK0TO10

Enable RAM block0 to block10

4095 : BLK0TO11

Enable RAM block0 to block11

8191 : BLK0TO12

Enable RAM block0 to block12

16383 : BLK0TO13

Enable RAM block0 to block13

32767 : BLK0TO14

Enable RAM block0 to block14

65535 : BLK0TO15

Enable RAM block0 to block15

End of enumeration elements list.


CFGSRTOP

No Description
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGSRTOP CFGSRTOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP

SRTOP : Sequential region on top
bits : 0 - 0 (1 bit)
access : read-write


CFGSRMAP

No Description
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGSRMAP CFGSRMAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAP

MAP :
bits : 0 - 15 (16 bit)
access : read-write


CFGIU0MAP

No Description
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGIU0MAP CFGIU0MAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAP

MAP :
bits : 0 - 15 (16 bit)
access : read-write


CFGIU1MAP

No Description
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGIU1MAP CFGIU1MAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAP

MAP :
bits : 0 - 15 (16 bit)
access : read-write


CFGIU2MAP

No Description
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGIU2MAP CFGIU2MAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAP

MAP :
bits : 0 - 15 (16 bit)
access : read-write


CMD

No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLEARECCADDR0 CLEARECCADDR1 CLEARECCADDR2 CLEARECCADDR3

CLEARECCADDR0 : Clear ECCERRADDR0
bits : 0 - 0 (1 bit)
access : write-only

CLEARECCADDR1 : Clear ECCERRADDR1
bits : 1 - 1 (1 bit)
access : write-only

CLEARECCADDR2 : Clear ECCERRADDR2
bits : 2 - 2 (1 bit)
access : write-only

CLEARECCADDR3 : Clear ECCERRADDR3
bits : 3 - 3 (1 bit)
access : write-only


CFGIU3MAP

No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGIU3MAP CFGIU3MAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAP

MAP :
bits : 0 - 15 (16 bit)
access : read-write


RPURATD0

Protected register address = (RPURATD register index X 32 + RPURATD bit index) X 4.
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPURATD0 RPURATD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATDCMD RATDCTRL RATDIF RATDIEN RATDRAMBANKSVALID RATDCFGSRTOP RATDCFGSRMAP RATDCFGIU0MAP RATDCFGIU1MAP RATDCFGIU2MAP RATDCFGIU3MAP

RATDCMD : CMD Protection Bit
bits : 1 - 1 (1 bit)
access : read-write

RATDCTRL : CTRL Protection Bit
bits : 2 - 2 (1 bit)
access : read-write

RATDIF : IF Protection Bit
bits : 8 - 8 (1 bit)
access : read-write

RATDIEN : IEN Protection Bit
bits : 9 - 9 (1 bit)
access : read-write

RATDRAMBANKSVALID : RAMBANKSVALID Protection Bit
bits : 10 - 10 (1 bit)
access : read-write

RATDCFGSRTOP : CFGSRTOP Protection Bit
bits : 11 - 11 (1 bit)
access : read-write

RATDCFGSRMAP : CFGSRMAP Protection Bit
bits : 12 - 12 (1 bit)
access : read-write

RATDCFGIU0MAP : CFGIU0MAP Protection Bit
bits : 13 - 13 (1 bit)
access : read-write

RATDCFGIU1MAP : CFGIU1MAP Protection Bit
bits : 14 - 14 (1 bit)
access : read-write

RATDCFGIU2MAP : CFGIU2MAP Protection Bit
bits : 15 - 15 (1 bit)
access : read-write

RATDCFGIU3MAP : CFGIU3MAP Protection Bit
bits : 16 - 16 (1 bit)
access : read-write


CTRL

No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCEN ECCWEN ECCERRFAULTEN AHBPORTPRIORITY ADDRFAULTEN WAITSTATES

ECCEN : Enable ECC functionality
bits : 0 - 0 (1 bit)
access : read-write

ECCWEN : Enable ECC syndrome writes
bits : 1 - 1 (1 bit)
access : read-write

ECCERRFAULTEN : ECC Error bus fault enable
bits : 2 - 2 (1 bit)
access : read-write

AHBPORTPRIORITY : AHB port arbitration priority
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

0 : NONE

No AHB port have raised priority.

1 : PORT0

AHB port 0 has raised priority.

2 : PORT1

AHB port 1 has raised priority.

3 : PORT2

AHB port 2 has raised priority.

4 : PORT3

AHB port 3 has raised priority.

End of enumeration elements list.

ADDRFAULTEN : Address fault bus fault enable
bits : 6 - 6 (1 bit)
access : read-write

WAITSTATES : RAM read wait states
bits : 7 - 7 (1 bit)
access : read-write


ECCERRADDR0

No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECCERRADDR0 ECCERRADDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : ECC Error Address
bits : 0 - 31 (32 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.