\n

RAC_S

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

IPVERSION

CMD

LNAMIXTRIM0

LNAMIXTRIM1

LNAMIXTRIM2

LNAMIXTRIM3

LNAMIXTRIM4

LNAMIXCAL

LNAMIXEN

PRECTRL

PATRIM0

PATRIM1

PATRIM2

PATRIM3

PATRIM4

PATRIM5

TXPOWER

CTRL

TXRAMP

PGATRIM

PGACAL

PGACTRL

RFBIASCAL

RFBIASCTRL

RADIOEN

RFPATHEN0

RFPATHEN1

RX

TX

SYTRIM0

SYTRIM1

SYCAL

FORCESTATE

SYEN

SYLOEN

SYMMDCTRL

DIGCLKRETIMECTRL

DIGCLKRETIMESTATUS

XORETIMECTRL

XORETIMESTATUS

AGCOVERWRITE0

AGCOVERWRITE1

AGCOVERWRITE2

IF

PACTRL

FENOTCH0

FENOTCH1

IEN

TESTCTRL

SEQIF

SEQIEN

STATUS1

STIMER

STIMERCOMP

SEQCTRL

SCRATCH0

SCRATCH1

SCRATCH2

SCRATCH3

SCRATCH4

SCRATCH5

SCRATCH6

SCRATCH7

EN

PRESC

SR0

SR1

SR2

SR3

STCTRL

FRCTXWORD

FRCRXWORD

EM1PCSR

THMSW

RXENSRCEN

SYNTHENCTRL

SYNTHREGCTRL

VCOCTRL

STATUS2

IFPGACTRL

PAENCTRL

APC

STATUS

ANTDIV

AUXADCTRIM

AUXADCEN

AUXADCCTRL0

AUXADCCTRL1

AUXADCOUT

CLKMULTEN0

CLKMULTEN1

CLKMULTCTRL

CLKMULTSTATUS

IFADCTRIM0

IFADCTRIM1

IFADCCAL

IFADCSTATUS


IPVERSION

No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : IP Version
bits : 0 - 31 (32 bit)
access : read-only


CMD

No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXEN FORCETX TXONCCA CLEARTXEN TXAFTERFRAME TXDIS CLEARRXOVERFLOW RXCAL RXDIS FRCWR FRCRD PAENSET PAENCLEAR LNAENSET LNAENCLEAR

TXEN : Transmitter Enable
bits : 0 - 0 (1 bit)
access : write-only

FORCETX : Force TX Command
bits : 1 - 1 (1 bit)
access : write-only

TXONCCA : Transmit On CCA
bits : 2 - 2 (1 bit)
access : write-only

CLEARTXEN : Clear TX Enable
bits : 3 - 3 (1 bit)
access : write-only

TXAFTERFRAME : TX After Frame
bits : 4 - 4 (1 bit)
access : write-only

TXDIS : TX Disable
bits : 5 - 5 (1 bit)
access : write-only

CLEARRXOVERFLOW : Clear RX Overflow
bits : 6 - 6 (1 bit)
access : write-only

RXCAL : Start an RX Calibration
bits : 7 - 7 (1 bit)
access : write-only

RXDIS : RX Disable
bits : 8 - 8 (1 bit)
access : write-only

FRCWR : FRC write cmd
bits : 10 - 10 (1 bit)
access : write-only

FRCRD : FRC read cmd
bits : 11 - 11 (1 bit)
access : write-only

PAENSET : PAEN Set
bits : 12 - 12 (1 bit)
access : write-only

PAENCLEAR : PAEN Clear
bits : 13 - 13 (1 bit)
access : write-only

LNAENSET : LNAEN Set
bits : 14 - 14 (1 bit)
access : write-only

LNAENCLEAR : LNAEN Clear
bits : 15 - 15 (1 bit)
access : write-only


LNAMIXTRIM0


address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LNAMIXTRIM0 LNAMIXTRIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXCAPSEL0 LNAMIXMXRBIAS0 LNAMIXVOUTADJ0

LNAMIXCAPSEL0 : LNAMIXCAPSEL0
bits : 0 - 2 (3 bit)
access : read-write

LNAMIXMXRBIAS0 : LNAMIXMXRBIAS0
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : bias_1V


1 : unused


2 : bias_900m


3 : bias_800m


End of enumeration elements list.

LNAMIXVOUTADJ0 : LNAMIXVOUTADJ0
bits : 5 - 8 (4 bit)
access : read-write


LNAMIXTRIM1


address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LNAMIXTRIM1 LNAMIXTRIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXCAPSEL1 LNAMIXMXRBIAS1 LNAMIXVOUTADJ1

LNAMIXCAPSEL1 : LNAMIXCAPSEL1
bits : 0 - 2 (3 bit)
access : read-write

LNAMIXMXRBIAS1 : LNAMIXMXRBIAS1
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : bias_1V


1 : unused


2 : bias_900m


3 : bias_800m


End of enumeration elements list.

LNAMIXVOUTADJ1 : LNAMIXVOUTADJ1
bits : 5 - 8 (4 bit)
access : read-write


LNAMIXTRIM2


address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LNAMIXTRIM2 LNAMIXTRIM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXCURCTRL LNAMIXHIGHCUR LNAMIXLOWCUR LNAMIXNCASADJ0 LNAMIXPCASADJ0 LNAMIXTRIMVREG LNAMIXNCASADJ1 LNAMIXPCASADJ1

LNAMIXCURCTRL : LNAMIXCURCTRL
bits : 4 - 9 (6 bit)
access : read-write

LNAMIXHIGHCUR : LNAMIXHIGHCUR
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

0 : current_470uA


1 : current_530uA


2 : unused


3 : current_590uA


End of enumeration elements list.

LNAMIXLOWCUR : LNAMIXLOWCUR
bits : 12 - 15 (4 bit)
access : read-write

LNAMIXNCASADJ0 : LNAMIXNCASADJ0
bits : 19 - 20 (2 bit)
access : read-write

Enumeration:

0 : ncas_1V


1 : unused


2 : ncas_950m


3 : ncas_900m


End of enumeration elements list.

LNAMIXPCASADJ0 : LNAMIXPCASADJ0
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

0 : pcas_250m


1 : unused


2 : pcas_300m


3 : pcas_350m


End of enumeration elements list.

LNAMIXTRIMVREG : LNAMIXTRIMVREG
bits : 23 - 26 (4 bit)
access : read-write

LNAMIXNCASADJ1 : LNAMIXNCASADJ1
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : ncas_1V


1 : unused


2 : ncas_950m


3 : ncas_900m


End of enumeration elements list.

LNAMIXPCASADJ1 : LNAMIXPCASADJ1
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0 : pcas_250m


1 : unused


2 : pcas_300m


3 : pcas_350m


End of enumeration elements list.


LNAMIXTRIM3

No Description
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LNAMIXTRIM3 LNAMIXTRIM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXIBIASADJ0 LNAMIXIBIASADJ1

LNAMIXIBIASADJ0 : LNAMIXIBIASADJ0
bits : 0 - 5 (6 bit)
access : read-write

LNAMIXIBIASADJ1 : LNAMIXIBIASADJ1
bits : 6 - 11 (6 bit)
access : read-write


LNAMIXTRIM4

No Description
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LNAMIXTRIM4 LNAMIXTRIM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXRFPKDBWSEL LNAMIXRFPKDCALCMLO LNAMIXRFPKDCALCMHI LNAMIXRFPKDTHRESHSELLO LNAMIXRFPKDTHRESHSELHI

LNAMIXRFPKDBWSEL : LNAMIXRFPKDBWSEL
bits : 0 - 1 (2 bit)
access : read-write

LNAMIXRFPKDCALCMLO : LNAMIXRFPKDCALCMLO
bits : 8 - 13 (6 bit)
access : read-write

LNAMIXRFPKDCALCMHI : LNAMIXRFPKDCALCMHI
bits : 14 - 19 (6 bit)
access : read-write

LNAMIXRFPKDTHRESHSELLO : LNAMIXRFPKDTHRESHSELLO
bits : 24 - 27 (4 bit)
access : read-write

LNAMIXRFPKDTHRESHSELHI : LNAMIXRFPKDTHRESHSELHI
bits : 28 - 31 (4 bit)
access : read-write


LNAMIXCAL


address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LNAMIXCAL LNAMIXCAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXCALEN LNAMIXCALVMODE LNAMIXENIRCAL0 LNAMIXENIRCAL1 LNAMIXIRCALAMP0 LNAMIXIRCALAMP1

LNAMIXCALEN : LNAMIXCALPMOSEN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : cal_disable


1 : cal_enable


End of enumeration elements list.

LNAMIXCALVMODE : LNAMIXCALVMODE
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : current_mode


1 : voltage_mode


End of enumeration elements list.

LNAMIXENIRCAL0 : LNAMIXENIRCAL0
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

LNAMIXENIRCAL1 : LNAMIXENIRCAL1
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

LNAMIXIRCALAMP0 : LNAMIXIRCALAMP0
bits : 5 - 7 (3 bit)
access : read-write

LNAMIXIRCALAMP1 : LNAMIXIRCALAMP1
bits : 8 - 10 (3 bit)
access : read-write


LNAMIXEN


address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LNAMIXEN LNAMIXEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXENLDO

LNAMIXENLDO : LNAMIXENLDO
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.


PRECTRL


address_offset : 0x11C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRECTRL PRECTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREBYPFORCE PREREGTRIM PREVREFTRIM

PREBYPFORCE : PREBYPFORCE
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : not_forced


1 : forced


End of enumeration elements list.

PREREGTRIM : PREREGTRIM
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

0 : v1p61


1 : v1p68


2 : v1p74


3 : v1p80


4 : v1p86


5 : v1p91


6 : v1p96


7 : v2p00


End of enumeration elements list.

PREVREFTRIM : PREVREFTRIM
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : v0p675


1 : v0p688


2 : v0p700


3 : v0p713


End of enumeration elements list.


PATRIM0

No Description
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATRIM0 PATRIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX0DBMTRIMBIASN TX0DBMTRIMBIASP TXPAAMPCTRL TXPABYPASSREG ENAMPCTRLREG

TX0DBMTRIMBIASN : TX0DBMTRIMBIASN
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : v_367m


1 : v_380m


2 : v_393m


3 : v_406m


4 : v_419m


5 : v_432m


6 : v_445m


7 : v_default_458m


8 : v_483m


9 : v_496m


10 : v_509m


11 : v_522m


12 : v_535m


13 : v_548m


14 : v_561m


15 : v_574m


End of enumeration elements list.

TX0DBMTRIMBIASP : TX0DBMTRIMBIASP
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0 : v_1p186


1 : v_1p173


2 : v_1p16


3 : v_1p147


4 : v_1p134


5 : v_1p121


6 : v_1p108


7 : v_default_1p095


8 : v_1p083


9 : v_1p07


10 : v_1p057


11 : v_1p044


12 : v_1p031


13 : v_1p019


14 : v_1p006


15 : v_0p993


End of enumeration elements list.

TXPAAMPCTRL : TXPAAMPCTRL
bits : 8 - 15 (8 bit)
access : read-write

TXPABYPASSREG : TXPABYPASSREG
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : not_bypass


1 : bypass


End of enumeration elements list.

ENAMPCTRLREG : ENAMPCTRLREG
bits : 24 - 24 (1 bit)
access : read-write


PATRIM1

No Description
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATRIM1 PATRIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX0DBMTRIMPREDRVREGIBCORE TX0DBMTRIMPREDRVREGPSR TX0DBMTRIMPREDRVREGIBNDIO TX0DBMTRIMPREDRVSLOPE TX0DBMTRIMREGFB TX0DBMTRIMREGVREF TX0DBMTRIMTAPCAP100F TX0DBMTRIMTAPCAP200F

TX0DBMTRIMPREDRVREGIBCORE : TX0DBMTRIMPREDRVREGIBCORE
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : i_4u


1 : i_5u


2 : i_6u


3 : i_default_7u


End of enumeration elements list.

TX0DBMTRIMPREDRVREGPSR : TX0DBMTRIMPREDRVREGPSR
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TX0DBMTRIMPREDRVREGIBNDIO : TX0DBMTRIMPREDRVREGIBNDIO
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0 : vreg_1p127


1 : vreg_1p171


2 : vreg_1p209


3 : vreg_1p244


4 : vreg_1p275


5 : vreg_1p305


6 : vreg_1p335


7 : vreg_default_1p362


8 : vreg_1p388


9 : vreg_1p414


10 : vreg_1p439


11 : vreg_1p463


12 : vreg_1p486


13 : vreg_1p509


14 : vreg_1p532


15 : vreg_1p555


End of enumeration elements list.

TX0DBMTRIMPREDRVSLOPE : TX0DBMTRIMPREDRVSLOPE
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : slope_0


1 : slope_1


2 : slope_2


3 : slope_default_max


End of enumeration elements list.

TX0DBMTRIMREGFB : TX0DBMTRIMREGFB
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

0 : v_1p976


1 : v_1p878


2 : v_1p788


3 : v_1p707


4 : v_default_1p633


5 : v_1p565


6 : v_1p503


7 : v_1p445


8 : v_1p392


9 : v_1p342


10 : v_1p296


11 : v_1p253


12 : v_1p213


13 : v_1p175


14 : v_1p14


15 : v_1p106


End of enumeration elements list.

TX0DBMTRIMREGVREF : TX0DBMTRIMREGVREF
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : v_1p572


1 : v_1p593


2 : v_1p613


3 : v_default_1p634


4 : v_1p654


5 : v_1p674


6 : v_1p694


7 : v_1p714


End of enumeration elements list.

TX0DBMTRIMTAPCAP100F : TX0DBMTRIMTAPCAP100F
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

0 : Ctap_plus_0f


1 : Ctap_plus_100f


2 : Ctap_plus_200f


3 : Ctap_plus_300f


4 : Ctap_plus_400f


5 : Ctap_plus_500f


6 : Ctap_plus_600f


7 : Ctap_plus_700f


End of enumeration elements list.

TX0DBMTRIMTAPCAP200F : TX0DBMTRIMTAPCAP200F
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : Ctap_plus_0f


1 : Ctap_plus_200f


2 : Ctap_plus_400f


3 : Ctap_plus_600f


4 : Ctap_plus_800f


5 : Ctap_plus_1p


6 : Ctap_plus_1p2p


7 : Ctap_plus_1p4p


End of enumeration elements list.


PATRIM2


address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATRIM2 PATRIM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX0DBMTRIMDUTYCYN TX0DBMTRIMDUTYCYP TXPATRIM10DBMDUTYCYN TXPATRIM10DBMDUTYCYP

TX0DBMTRIMDUTYCYN : TX0DBMTRIMDUTYCYN
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : up_0pct


1 : up_1pct


2 : up_2pct


3 : up_3pct


4 : up_4pct


5 : up_5pct


6 : up_6pct


7 : na


End of enumeration elements list.

TX0DBMTRIMDUTYCYP : TX0DBMTRIMDUTYCYP
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0 : dn_0pct


1 : dn_1pct


2 : dn_2pct


3 : dn_3pct


4 : dn_4pct


5 : dn_5pct


6 : dn_6pct


7 : na


End of enumeration elements list.

TXPATRIM10DBMDUTYCYN : TXPATRIM10DBMDUTYCYN
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : up_0pct


1 : up_1pct


2 : up_2pct


3 : up_3pct


4 : up_4pct


5 : up_5pct


6 : up_6pct


7 : na


End of enumeration elements list.

TXPATRIM10DBMDUTYCYP : TXPATRIM10DBMDUTYCYP
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

0 : dn_0pct


1 : dn_1pct


2 : dn_2pct


3 : dn_3pct


4 : dn_4pct


5 : dn_5pct


6 : dn_6pct


7 : na


End of enumeration elements list.


PATRIM3

No Description
address_offset : 0x12C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATRIM3 PATRIM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXPATRIMBLEEDAUTOREG TXPATRIMIBIASMASTER TXPATRIMPREDRVREGFB TXPATRIMPREDRVREGFBKATT TXPATRIMPREDRVREGPSR TXPATRIMPREDRVREGSLICES TXPATRIMPREDRVREGVREF TXPATRIMREGFB TXPATRIMREGPSR TXPATRIMREGVREF

TXPATRIMBLEEDAUTOREG : TXPATRIMBLEEDAUTOREG
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : not_automatic


1 : automatic


End of enumeration elements list.

TXPATRIMIBIASMASTER : TXPATRIMIBIASMASTER
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0 : Ibias_is_45u


1 : Ibias_is_47p5u


2 : Ibias_is_50u


3 : Ibias_is_52p5u


End of enumeration elements list.

TXPATRIMPREDRVREGFB : TXPATRIMPREDRVREGFB
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : vreg_1p22


1 : vreg_1p28


2 : vreg_1p35


3 : vreg_1p44


End of enumeration elements list.

TXPATRIMPREDRVREGFBKATT : TXPATRIMPREDRVREGFBKATT
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : less_bw


1 : more_bw


End of enumeration elements list.

TXPATRIMPREDRVREGPSR : TXPATRIMPREDRVREGPSR
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : low_psr


1 : high_psr


End of enumeration elements list.

TXPATRIMPREDRVREGSLICES : TXPATRIMPREDRVREGSLICES
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : iload_7p5mA


1 : iload_15mA


2 : iload_22p5mA


3 : iload_30mA


End of enumeration elements list.

TXPATRIMPREDRVREGVREF : TXPATRIMPREDRVREGVREF
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

0 : vref_0p675


1 : vref_0p700


2 : vref_0p725


3 : vref_0p750


4 : vref_0p775


5 : vref_0p800


6 : vref_0p825


7 : vref_0p850


End of enumeration elements list.

TXPATRIMREGFB : TXPATRIMREGFB
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : vreg_1p678


1 : vreg_1p735


2 : vreg_1p801


3 : vreg_1p875


4 : vreg_3p00


5 : vreg_3p14


6 : vreg_3p3


7 : vreg_3p477


End of enumeration elements list.

TXPATRIMREGPSR : TXPATRIMREGPSR
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : low_psr


1 : high_psr


End of enumeration elements list.

TXPATRIMREGVREF : TXPATRIMREGVREF
bits : 20 - 23 (4 bit)
access : read-write

Enumeration:

0 : vref_0p651


1 : vref_0p663


2 : vref_0p676


3 : vref_0p688


4 : vref_0p701


5 : vref_0p713


6 : vref_0p726


7 : vref_0p738


8 : vref_0p751


9 : vref_0p763


10 : vref_0p776


11 : vref_0p788


12 : vref_0p801


13 : vref_0p813


14 : vref_0p826


15 : vref_0p838


End of enumeration elements list.


PATRIM4

No Description
address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATRIM4 PATRIM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXPATRIM10DBMCTAP TXPATRIM10DBMPREDRVCAP TXPATRIM10DBMPREDRVSLC TXPATRIM20DBMCTAP TXPATRIM20DBMPREDRV TXPATRIMCAPPAOUTM TXPATRIMCAPPAOUTP TXPATRIMCMGAIN

TXPATRIM10DBMCTAP : TXPATRIM10DBMCTAP
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : ctap_trim_0


1 : ctap_trim_1


2 : ctap_trim_2


3 : ctap_trim_3


4 : ctap_trim_4


5 : ctap_trim_5


6 : ctap_trim_6


7 : ctap_trim_7


8 : ctap_trim_8


End of enumeration elements list.

TXPATRIM10DBMPREDRVCAP : TXPATRIM10DBMPREDRVCAP
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : cap_0


1 : cap_1


2 : cap_2


3 : cap_3


End of enumeration elements list.

TXPATRIM10DBMPREDRVSLC : TXPATRIM10DBMPREDRVSLC
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0 : slc_0


1 : slc_1


2 : slc_2


3 : slc_3


End of enumeration elements list.

TXPATRIM20DBMCTAP : TXPATRIM20DBMCTAP
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

0 : ctap_trim_0


1 : ctap_trim_1


2 : ctap_trim_2


3 : ctap_trim_3


4 : ctap_trim_4


5 : ctap_trim_5


6 : ctap_trim_6


7 : ctap_trim_7


8 : ctap_trim_8


End of enumeration elements list.

TXPATRIM20DBMPREDRV : TXPATRIM20DBMPREDRV
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

0 : trise_137ps


1 : trise_127ps


2 : trise_117ps


3 : trise_110ps


4 : trise_75ps


5 : trise_73ps


6 : trise_71ps


7 : trise_70ps


End of enumeration elements list.

TXPATRIMCAPPAOUTM : TXPATRIMCAPPAOUTM
bits : 16 - 19 (4 bit)
access : read-write

TXPATRIMCAPPAOUTP : TXPATRIMCAPPAOUTP
bits : 20 - 23 (4 bit)
access : read-write

TXPATRIMCMGAIN : TXPATRIMCMGAIN
bits : 24 - 25 (2 bit)
access : read-write


PATRIM5

No Description
address_offset : 0x134 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATRIM5 PATRIM5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXPATRIMDACGLITCH TXPATRIMDLY0 TXPATRIMDLY1 TXPATRIMNBIAS TXPATRIMNCASC TXPATRIMPBIAS TXPATRIMPCASC TXPATRIMREGSLICES

TXPATRIMDACGLITCH : TXPATRIMDACGLITCH
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : larger_glitch


1 : smaller_glitch


End of enumeration elements list.

TXPATRIMDLY0 : TXPATRIMDLY0
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

0 : tdly_0ps


1 : tdly_64ps


2 : tdly_65ps


3 : tdly_66ps


4 : tdly_68ps


5 : tdly_70ps


6 : tdly_75ps


7 : tdly_83ps


End of enumeration elements list.

TXPATRIMDLY1 : TXPATRIMDLY1
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0 : tdly_0ps


1 : tdly_64ps


2 : tdly_65ps


3 : tdly_66ps


4 : tdly_68ps


5 : tdly_70ps


6 : tdly_75ps


7 : tdly_83ps


End of enumeration elements list.

TXPATRIMNBIAS : TXPATRIMNBIAS
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

0 : vnbias_dn104mv


1 : vnbias_dn91mv


2 : vnbias_dn78mv


3 : vnbias_dn65mv


4 : vnbias_dn52mv


5 : vnbias_dn39mv


6 : vnbias_dn26mv


7 : vnbias_dn13mv


8 : vnbias_default


9 : vnbias_up13mv


10 : vnbias_up26mv


11 : vnbias_up39mv


12 : vnbias_up52mv


13 : vnbias_up65mv


14 : vnbias_up78mv


15 : vnbias_up91mv


End of enumeration elements list.

TXPATRIMNCASC : TXPATRIMNCASC
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : ncbias_m50mv


1 : ncbiasdefault


2 : ncbias_p50mv


3 : ncbias_p100mv


End of enumeration elements list.

TXPATRIMPBIAS : TXPATRIMPBIAS
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : vpbias_up104mv


1 : vpbias_up91mv


2 : vpbias_up78mv


3 : vpbias_up65mv


4 : vpbias_up52mv


5 : vpbias_up39mv


6 : vpbias_up26mv


7 : vpbias_up13mv


8 : vpbias_default


9 : vpbias_dn13mv


10 : vpbias_dn26mv


11 : vpbias_dn38mv


12 : vpbias_dn52mv


13 : vpbias_dn65mv


14 : vpbias_dn78mv


15 : vpbias_dn91mv


End of enumeration elements list.

TXPATRIMPCASC : TXPATRIMPCASC
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0 : pcbias_n50mv


1 : pcbias_default


2 : pcbias_m50mv


3 : pcbias_m100mv


End of enumeration elements list.

TXPATRIMREGSLICES : TXPATRIMREGSLICES
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : spare1


1 : spare2


2 : spare3


3 : spare4


End of enumeration elements list.


TXPOWER

No Description
address_offset : 0x13C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXPOWER TXPOWER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX0DBMPOWER TX0DBMSELSLICE

TX0DBMPOWER : TX0DBMPOWER
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : on_stripe_0


15 : on_stripe_15


End of enumeration elements list.

TX0DBMSELSLICE : TX0DBMSELSLICE
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : on_0_slice


1 : on_1_slice


2 : NA


3 : on_1_slices


End of enumeration elements list.


CTRL

No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FORCEDISABLE PRSTXEN TXAFTERRX PRSMODE PRSCLR TXPOSTPONE ACTIVEPOL PAENPOL LNAENPOL PRSRXDIS PRSFORCETX SEQRESET EXITSHUTDOWNDIS CPUWAITDIS SEQCLKDIS RXOFDIS

FORCEDISABLE : Force Radio Disable
bits : 0 - 0 (1 bit)
access : read-write

PRSTXEN : PRS TX Enable
bits : 1 - 1 (1 bit)
access : read-write

TXAFTERRX : TX After RX
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : X0

TX will not be started automatically.

1 : X1

A transition to TX is automatically started when a received frame is accepted by the FRC.

End of enumeration elements list.

PRSMODE : PRS RXEN Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DIRECT

The PRS signal is used directly

1 : PULSE

The PRS signal is used as an RX enable pulse

End of enumeration elements list.

PRSCLR : PRS RXEN Clear
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : RXSEARCH

The PRS RXEN signal is cleared when the RSM state enters RXSEARCH

1 : PRSCH

The Selected PRS channel in PRSCLRSEL is used as a disable pulse

End of enumeration elements list.

TXPOSTPONE : TX Postpone
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : X0

In the TX state transmit data is output.

1 : X1

In the TX state an unmodulated carrier is output until this bit is cleared.

End of enumeration elements list.

ACTIVEPOL : ACTIVE signal polarity
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : X0

Active low

1 : X1

Active high

End of enumeration elements list.

PAENPOL : PAEN signal polarity
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : X0

Active low

1 : X1

Active high

End of enumeration elements list.

LNAENPOL : LNAEN signal polarity
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : X0

Active low

1 : X1

Active high

End of enumeration elements list.

PRSRXDIS : PRS RX Disable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : X0

PRS will not disable RX

1 : X1

The channel selected by PRSRXDISSEL will generate a disable RX pulse

End of enumeration elements list.

PRSFORCETX : PRS Force RX
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : X0

PRS will not force TX

1 : X1

The channel selected by PRSFORCETXSEL will generate a force TX pulse

End of enumeration elements list.

SEQRESET : SEQ reset
bits : 24 - 24 (1 bit)
access : write-only

EXITSHUTDOWNDIS : Exit SHUTDOWN state Disable
bits : 25 - 25 (1 bit)
access : read-write

CPUWAITDIS : SEQ CPU Wait Disable
bits : 26 - 26 (1 bit)
access : read-write

SEQCLKDIS : SEQ Clk Disable
bits : 27 - 27 (1 bit)
access : read-write

RXOFDIS : Switch to RXOVERFLOW Disable
bits : 28 - 28 (1 bit)
access : read-write


TXRAMP

No Description
address_offset : 0x140 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXRAMP TXRAMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARAMPMODE

PARAMPMODE : PARAMPMODE
bits : 0 - 0 (1 bit)
access : read-write


PGATRIM


address_offset : 0x148 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PGATRIM PGATRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGACTUNE PGAVCMOUTTRIM PGAVLDOTRIM

PGACTUNE : PGACTUNE
bits : 0 - 4 (5 bit)
access : read-write

PGAVCMOUTTRIM : PGAVCMOUTTRIM
bits : 6 - 8 (3 bit)
access : read-write

Enumeration:

0 : vcm_out_475


1 : vcm_out_500


2 : vcm_out_525


3 : vcm_out_550


4 : vcm_out_575


5 : vcm_out_600


6 : vcm_out_625


7 : vcm_out_650


End of enumeration elements list.

PGAVLDOTRIM : PGAVLDOTRIM
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

0 : vdda_1225


1 : vdda_1250


2 : vdda_1275


3 : vdda_1300


4 : vdda_1325


5 : vdda_1350


6 : vdda_1375


7 : vdda_1400


End of enumeration elements list.


PGACAL


address_offset : 0x14C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PGACAL PGACAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGAOFFCALI PGAOFFCALQ

PGAOFFCALI : PGAOFFCALI
bits : 0 - 5 (6 bit)
access : read-write

PGAOFFCALQ : PGAOFFCALQ
bits : 8 - 13 (6 bit)
access : read-write


PGACTRL


address_offset : 0x150 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PGACTRL PGACTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGABWMODE PGAENGHZ PGAENBIAS PGAENLATCHI PGAENLATCHQ PGAENLDOLOAD PGAENPGAI PGAENPGAQ PGAENPKD PGAPOWERMODE PGATHRPKDLOSEL PGATHRPKDHISEL

PGABWMODE : PGABWMODE
bits : 0 - 3 (4 bit)
access : read-write

PGAENGHZ : PGAENGHZ
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : ghz_disable


1 : ghz_enable


End of enumeration elements list.

PGAENBIAS : PGAENBIAS
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : bias_disable


1 : bias_enable


End of enumeration elements list.

PGAENLATCHI : PGAENLATCHI
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : pkd_latch_i_disable


1 : pkd_latch_i_enable


End of enumeration elements list.

PGAENLATCHQ : PGAENLATCHQ
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : pkd_latch_q_disable


1 : pkd_latch_q_enable


End of enumeration elements list.

PGAENLDOLOAD : PGAENLDOLOAD
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : disable_ldo_load


1 : enable_ldo_load


End of enumeration elements list.

PGAENPGAI : PGAENPGAI
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : pgai_disable


1 : pgai_enable


End of enumeration elements list.

PGAENPGAQ : PGAENPGAQ
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : pgaq_disable


1 : pgaq_enable


End of enumeration elements list.

PGAENPKD : PGAENPKD
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : pkd_disable


1 : pkd_enable


End of enumeration elements list.

PGAPOWERMODE : PGAPOWERMODE
bits : 14 - 16 (3 bit)
access : read-write

Enumeration:

0 : pm0_3u0


1 : pm1_3u5


2 : pm2_4u0


3 : pm3_4u5


4 : pm4_4u0


5 : pm5_4u5


6 : pm6_5u0


7 : pm7_5u5


End of enumeration elements list.

PGATHRPKDLOSEL : PGATHRPKDLOSEL
bits : 17 - 20 (4 bit)
access : read-write

Enumeration:

0 : vref50mv


1 : vref75mv


2 : vref100mv


3 : vref125mv


4 : vref150mv


5 : vref175mv


6 : vref200mv


7 : vref225mv


8 : vref250mv


9 : vref275mv


10 : vref300mv


End of enumeration elements list.

PGATHRPKDHISEL : PGATHRPKDHISEL
bits : 21 - 24 (4 bit)
access : read-write

Enumeration:

0 : vref50mv


1 : vref75mv


2 : vref100mv


3 : vref125mv


4 : verf150mv


5 : vref175mv


6 : vref200mv


7 : vref225mv


8 : vref250mv


9 : vref275mv


10 : vref300mv


End of enumeration elements list.


RFBIASCAL


address_offset : 0x154 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFBIASCAL RFBIASCAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFBIASCALBIAS RFBIASCALTC RFBIASCALVREF RFBIASCALVREFSTARTUP

RFBIASCALBIAS : RFBIASCALBIAS
bits : 0 - 5 (6 bit)
access : read-write

RFBIASCALTC : RFBIASCALTC
bits : 8 - 13 (6 bit)
access : read-write

RFBIASCALVREF : RFBIASCALVREF
bits : 16 - 21 (6 bit)
access : read-write

RFBIASCALVREFSTARTUP : RFBIASCALVREFSTARTUP
bits : 24 - 29 (6 bit)
access : read-write


RFBIASCTRL


address_offset : 0x158 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFBIASCTRL RFBIASCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFBIASDISABLEBOOTSTRAP RFBIASLDOHIGHCURRENT RFBIASNONFLASHMODE RFBIASSTARTUPCORE RFBIASSTARTUPSUPPLY RFBIASLDOVREFTRIM

RFBIASDISABLEBOOTSTRAP : RFBIASDISABLEBOOTSTRAP
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : enable_startup


1 : disable_startup


End of enumeration elements list.

RFBIASLDOHIGHCURRENT : RFBIASLDOHIGHCURRENT
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : low_current


1 : high_current


End of enumeration elements list.

RFBIASNONFLASHMODE : RFBIASNONFLASHMODE
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : flash_process


1 : non_flash_process


End of enumeration elements list.

RFBIASSTARTUPCORE : RFBIASSTARTUPCORE
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : default


1 : force_start


End of enumeration elements list.

RFBIASSTARTUPSUPPLY : RFBIASSTARTUPSUPPLY
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : default


1 : forc_start


End of enumeration elements list.

RFBIASLDOVREFTRIM : RFBIASLDOVREFTRIM
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : vref_v0p800


1 : vref_v0p813


2 : vref_v0p825


3 : vref_v0p837


4 : vref_v0p850


5 : vref_v0p863


6 : vref_v0p875


7 : vref_v0p887


8 : vref_v0p900


9 : vref_v0p913


10 : vref_v0p925


11 : vref_v0p938


12 : vref_v0p950


13 : vref_v0p963


14 : vref_v0p975


15 : vref_v0p988


End of enumeration elements list.


RADIOEN


address_offset : 0x15C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RADIOEN RADIOEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREEN PRESTB100UDIS RFBIASEN

PREEN : PREEN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : powered_off


1 : powered_on


End of enumeration elements list.

PRESTB100UDIS : PRESTB100UDIS
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : i100ua_enabled


1 : i100ua_disabled


End of enumeration elements list.

RFBIASEN : RFBIASEN
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : disable_rfis_vtr


1 : enable_rfis_vtr


End of enumeration elements list.


RFPATHEN0

No Description
address_offset : 0x160 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFPATHEN0 RFPATHEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXEN0 LNAMIXRFATTDCEN0 LNAMIXRFPKDENRF0 SYLODIVRLO02G4EN LNAMIXTRSW0

LNAMIXEN0 : LNAMIXEN0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

LNAMIXRFATTDCEN0 : LNAMIXRFATTDCEN0
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : disable_dc


1 : enable_dc


End of enumeration elements list.

LNAMIXRFPKDENRF0 : LNAMIXRFPKDENRF0
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable_path


End of enumeration elements list.

SYLODIVRLO02G4EN : SYLODIVRLO02G4EN
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

LNAMIXTRSW0 : LNAMIXTRSW0
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : disabled


1 : enabled


End of enumeration elements list.


RFPATHEN1

No Description
address_offset : 0x164 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFPATHEN1 RFPATHEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXEN1 LNAMIXRFATTDCEN1 LNAMIXRFPKDENRF1 SYLODIVRLO12G4EN LNAMIXTRSW1

LNAMIXEN1 : LNAMIXEN1
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

LNAMIXRFATTDCEN1 : LNAMIXRFATTDCEN1
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : disable_dc


1 : enable_dc


End of enumeration elements list.

LNAMIXRFPKDENRF1 : LNAMIXRFPKDENRF1
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable_path


End of enumeration elements list.

SYLODIVRLO12G4EN : SYLODIVRLO12G4EN
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

LNAMIXTRSW1 : LNAMIXTRSW1
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : disabled


1 : enabled


End of enumeration elements list.


RX


address_offset : 0x168 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX RX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFADCCAPRESET IFADCENLDOSERIES IFADCENLDOSHUNT LNAMIXENRFPKD LNAMIXENRFPKDLOTHRESH LNAMIXLDOLOWCUR LNAMIXREGLOADEN PGAENLDO SYCHPQNC3EN SYCHPBIASTRIMBUFRX SYPFDCHPLPENRX SYPFDFPWENRX

IFADCCAPRESET : IFADCCAPRESET
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : cap_reset_disable


1 : cap_reset_enable


End of enumeration elements list.

IFADCENLDOSERIES : IFADCENLDOSERIES
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : series_ldo_disable


1 : series_ldo_enable


End of enumeration elements list.

IFADCENLDOSHUNT : IFADCENLDOSHUNT
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : shunt_ldo_disable


1 : shunt_ldo_enable


End of enumeration elements list.

LNAMIXENRFPKD : LNAMIXENRFPKD
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

LNAMIXENRFPKDLOTHRESH : LNAMIXENRFPKDLOTHRESH
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

LNAMIXLDOLOWCUR : LNAMIXLDOLOWCUR
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : regular_mode


1 : low_current_mode


End of enumeration elements list.

LNAMIXREGLOADEN : LNAMIXREGLOADEN
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : disable_resistor


1 : enable_resistor


End of enumeration elements list.

PGAENLDO : PGAENLDO
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : disable_ldo


1 : enable_ldo


End of enumeration elements list.

SYCHPQNC3EN : SYCHPQNC3EN
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : qnc_2


1 : qnc_3


End of enumeration elements list.

SYCHPBIASTRIMBUFRX : SYCHPBIASTRIMBUFRX
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : i_tail_10u


1 : i_tail_20u


End of enumeration elements list.

SYPFDCHPLPENRX : SYPFDCHPLPENRX
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYPFDFPWENRX : SYPFDFPWENRX
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.


TX


address_offset : 0x16C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX TX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXPAENREG TXPAENRAMPCLK TX0DBMENBLEEDREG TX0DBMENREG TX0DBMENBIAS TX0DBMENPREDRV TX0DBMENPREDRVREG TX0DBMENPREDRVREGBIAS TX0DBMENRAMPCLK TX0DBMENBLEEDPREDRVREG TXPAENBLEEDPREDRVREG TXPAENBLEEDREG TXPAENPAOUT TXPAENPREDRVREG SYCHPBIASTRIMBUFTX SYPFDCHPLPENTX SYPFDFPWENTX TXPAEN10DBM TXPAEN10DBMMAINCTAP TXPAEN10DBMPREDRV TXPAEN10DBMVMID TXPAEN20DBM TXPAEN20DBMMAINCTAP TXPAEN20DBMPREDRV TXPAEN20DBMVMID TXPAEN20DBMVBIASHF TXPATRIM20DBMVBIASHF ENPAPOWER ENPASELSLICE

TXPAENREG : TXPAENREG
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TXPAENRAMPCLK : TXPAENRAMPCLK
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : silence_clk


1 : en_clk


End of enumeration elements list.

TX0DBMENBLEEDREG : TX0DBMENBLEEDREG
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TX0DBMENREG : TX0DBMENREG
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TX0DBMENBIAS : TX0DBMENBIAS
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TX0DBMENPREDRV : TX0DBMENPREDRV
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TX0DBMENPREDRVREG : TX0DBMENPREDRVREG
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TX0DBMENPREDRVREGBIAS : TX0DBMENPREDRVREGBIAS
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TX0DBMENRAMPCLK : TX0DBMENRAMPCLK
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TX0DBMENBLEEDPREDRVREG : TX0DBMENBLEEDPREDRVREG
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TXPAENBLEEDPREDRVREG : TXPAENBLEEDPREDRVREG
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TXPAENBLEEDREG : TXPAENBLEEDREG
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TXPAENPAOUT : TXPAENPAOUT
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TXPAENPREDRVREG : TXPAENPREDRVREG
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYCHPBIASTRIMBUFTX : SYCHPBIASTRIMBUFTX
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : i_tail_10u


1 : i_tail_20u


End of enumeration elements list.

SYPFDCHPLPENTX : SYPFDCHPLPENTX
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYPFDFPWENTX : SYPFDFPWENTX
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TXPAEN10DBM : TXPAEN10DBM
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TXPAEN10DBMMAINCTAP : TXPAEN10DBMMAINCTAP
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : ctap_main_dis


1 : ctap_main_en


End of enumeration elements list.

TXPAEN10DBMPREDRV : TXPAEN10DBMPREDRV
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TXPAEN10DBMVMID : TXPAEN10DBMVMID
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TXPAEN20DBM : TXPAEN20DBM
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TXPAEN20DBMMAINCTAP : TXPAEN20DBMMAINCTAP
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ctap_main_dis


1 : ctap_main_en


End of enumeration elements list.

TXPAEN20DBMPREDRV : TXPAEN20DBMPREDRV
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TXPAEN20DBMVMID : TXPAEN20DBMVMID
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TXPAEN20DBMVBIASHF : TXPAEN20DBMVBIASHF
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : disable_bias


1 : enable_bias


End of enumeration elements list.

TXPATRIM20DBMVBIASHF : TXPATRIM20DBMVBIASHF
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : bias_avss


1 : bias_low


2 : bias_mid


3 : bias_high


End of enumeration elements list.

ENPAPOWER : Override
bits : 30 - 30 (1 bit)
access : read-write

ENPASELSLICE : Override
bits : 31 - 31 (1 bit)
access : read-write


SYTRIM0


address_offset : 0x174 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYTRIM0 SYTRIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYCHPBIAS SYCHPCURRRX SYCHPCURRTX SYCHPLEVNSRC SYCHPLEVPSRCRX SYCHPLEVPSRCTX SYCHPSRCENRX SYCHPSRCENTX SYCHPREPLICACURRADJ SYTRIMCHPREGAMPBIAS SYTRIMCHPREGAMPBW

SYCHPBIAS : SYCHPBIAS
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : bias_0


1 : bias_1


3 : bias_2


7 : bias_3


End of enumeration elements list.

SYCHPCURRRX : SYCHPCURRRX
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

0 : curr_1p5uA


1 : curr_2p0uA


2 : curr_2p5uA


3 : curr_3p0uA


4 : curr_3p5uA


5 : curr_4p0uA


6 : curr_4p5uA


7 : curr_5p0uA


End of enumeration elements list.

SYCHPCURRTX : SYCHPCURRTX
bits : 6 - 8 (3 bit)
access : read-write

Enumeration:

0 : curr_1p5uA


1 : curr_2p0uA


2 : curr_2p5uA


3 : curr_3p0uA


4 : curr_3p5uA


5 : curr_4p0uA


6 : curr_4p5uA


7 : curr_5p0uA


End of enumeration elements list.

SYCHPLEVNSRC : SYCHPLEVNSRC
bits : 9 - 11 (3 bit)
access : read-write

SYCHPLEVPSRCRX : SYCHPLEVPSRCRX
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

0 : vsrcp_n105m


1 : vsrcp_n90m


2 : vsrcp_n75m


3 : vsrcp_n60m


4 : vsrcp_n45m


5 : vsrcp_n30m


6 : vsrcp_n15m


7 : vsrcp_n0m


End of enumeration elements list.

SYCHPLEVPSRCTX : SYCHPLEVPSRCTX
bits : 15 - 17 (3 bit)
access : read-write

Enumeration:

0 : vsrcp_n105m


1 : vsrcp_n90m


2 : vsrcp_n75m


3 : vsrcp_n60m


4 : vsrcp_n45m


5 : vsrcp_n30m


6 : vsrcp_n15m


7 : vsrcp_n0m


End of enumeration elements list.

SYCHPSRCENRX : SYCHPSRCENRX
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYCHPSRCENTX : SYCHPSRCENTX
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYCHPREPLICACURRADJ : SYCHPREPLICACURRADJ
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

0 : load_8ua


1 : load_16ua


2 : load_20ua


3 : load_28ua


4 : load_24ua


5 : load_32ua


6 : load_36ua


7 : load_44ua


End of enumeration elements list.

SYTRIMCHPREGAMPBIAS : SYTRIMCHPREGAMPBIAS
bits : 23 - 25 (3 bit)
access : read-write

Enumeration:

0 : bias_14uA


1 : bias_20uA


2 : bias_26uA


3 : bias_32uA


4 : bias_38uA


5 : bias_44uA


6 : bias_50uA


7 : bias_56uA


End of enumeration elements list.

SYTRIMCHPREGAMPBW : SYTRIMCHPREGAMPBW
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : C_000f


1 : C_300f


2 : C_600f


3 : C_900f


End of enumeration elements list.


SYTRIM1


address_offset : 0x178 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYTRIM1 SYTRIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYLODIVLDOTRIMCORERX SYLODIVLDOTRIMCORETX SYLODIVLDOTRIMNDIORX SYLODIVLDOTRIMNDIOTX SYLODIVTLO20DBM2G4DELAY SYMMDREPLICA1CURRADJ SYMMDREPLICA2CURRADJ SYTRIMMMDREGAMPBIAS SYTRIMMMDREGAMPBW

SYLODIVLDOTRIMCORERX : SYLODIVLDOTRIMCORERX
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : RXLO


3 : TXLO


End of enumeration elements list.

SYLODIVLDOTRIMCORETX : SYLODIVLDOTRIMCORETX
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0 : RXLO


3 : TXLO


End of enumeration elements list.

SYLODIVLDOTRIMNDIORX : SYLODIVLDOTRIMNDIORX
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0 : vreg_1p08


1 : vreg_1p11


2 : vreg_1p15


3 : vreg_1p18


4 : vreg_1p21


5 : vreg_1p24


6 : vreg_1p27


7 : vreg_1p29


8 : vreg_1p32


9 : vreg_1p34


End of enumeration elements list.

SYLODIVLDOTRIMNDIOTX : SYLODIVLDOTRIMNDIOTX
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

0 : vreg_1p08


1 : vreg_1p11


2 : vreg_1p15


3 : vreg_1p18


4 : vreg_1p21


5 : vreg_1p24


6 : vreg_1p27


7 : vreg_1p29


8 : vreg_1p32


9 : vreg_1p34


End of enumeration elements list.

SYLODIVTLO20DBM2G4DELAY : SYLODIVTLO20DBM2G4DELAY
bits : 18 - 20 (3 bit)
access : read-write

SYMMDREPLICA1CURRADJ : SYMMDREPLICA1CURRADJ
bits : 21 - 23 (3 bit)
access : read-write

Enumeration:

0 : load_8ua


1 : load_16u


2 : load_20ua


3 : load_28ua


4 : load_24ua


5 : load_32ua


6 : load_36ua


7 : load_44ua


End of enumeration elements list.

SYMMDREPLICA2CURRADJ : SYMMDREPLICA2CURRADJ
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : load_32u


1 : load_64u


2 : load_96u


3 : load_128u


4 : load_160u


5 : load_192u


6 : load_224u


7 : load_256u


End of enumeration elements list.

SYTRIMMMDREGAMPBIAS : SYTRIMMMDREGAMPBIAS
bits : 27 - 29 (3 bit)
access : read-write

Enumeration:

0 : bias_14uA


1 : bias_20uA


2 : bias_26uA


3 : bias_32uA


4 : bias_38uA


5 : bias_44uA


6 : bias_50uA


7 : bias_56uA


End of enumeration elements list.

SYTRIMMMDREGAMPBW : SYTRIMMMDREGAMPBW
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

0 : C_000f


1 : C_300f


2 : C_600f


3 : C_900f


End of enumeration elements list.


SYCAL


address_offset : 0x17C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYCAL SYCAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYVCOMODEPKD SYVCOMORECURRENT SYVCOSLOWNOISEFILTER SYVCOVCAPVCM SYHILOADCHPREG

SYVCOMODEPKD : SYVCOMODEPKD
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : t_openloop_0


1 : t_pkdetect_1


End of enumeration elements list.

SYVCOMORECURRENT : SYVCOMORECURRENT
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : more_current_0


1 : more_current_1


End of enumeration elements list.

SYVCOSLOWNOISEFILTER : SYVCOSLOWNOISEFILTER
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : slow_noise_filter_0


1 : slow_noise_filter_1


End of enumeration elements list.

SYVCOVCAPVCM : SYVCOVCAPVCM
bits : 15 - 16 (2 bit)
access : read-write

SYHILOADCHPREG : SYHILOADCHPREG
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : i_350uA


1 : i_500uA


2 : i_550uA


3 : i_700uA


End of enumeration elements list.


FORCESTATE

No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FORCESTATE FORCESTATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FORCESTATE

FORCESTATE : Force RAC state transition
bits : 0 - 3 (4 bit)
access : read-write


SYEN


address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYEN SYEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYCHPEN SYCHPLPENRX SYCHPLPENTX SYENCHPREG SYENCHPREPLICA SYENMMDREG SYENMMDREPLICA1 SYENMMDREPLICA2 SYENVCOBIAS SYENVCOPFET SYENVCOREG SYSTARTCHPREG SYSTARTMMDREG

SYCHPEN : SYCHPEN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYCHPLPENRX : SYCHPLPENRX
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYCHPLPENTX : SYCHPLPENTX
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYENCHPREG : SYENCHPREG
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : Disable


1 : Enable


End of enumeration elements list.

SYENCHPREPLICA : SYENCHPREPLICA
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYENMMDREG : SYENMMDREG
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : Disable


1 : Enable


End of enumeration elements list.

SYENMMDREPLICA1 : SYENMMDREPLICA1
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYENMMDREPLICA2 : SYENMMDREPLICA2
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : Disable


1 : Enable


End of enumeration elements list.

SYENVCOBIAS : SYENVCOBIAS
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : en_vco_bias_0


1 : en_vco_bias_1


End of enumeration elements list.

SYENVCOPFET : SYENVCOPFET
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : en_vco_pfet_0


1 : en_vco_pfet_1


End of enumeration elements list.

SYENVCOREG : SYENVCOREG
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : en_vco_reg_0


1 : en_vco_reg_1


End of enumeration elements list.

SYSTARTCHPREG : SYSTARTCHPREG
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : no_fast_startup


1 : fast_startup


End of enumeration elements list.

SYSTARTMMDREG : SYSTARTMMDREG
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : no_fast_startup


1 : fast_startup


End of enumeration elements list.


SYLOEN


address_offset : 0x184 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYLOEN SYLOEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYLODIVEN SYLODIVLDOBIASEN SYLODIVLDOEN SYLODIVRLOADCCLK2G4EN SYLODIVTLO0DBM2G4AUXEN SYLODIVTLO0DBM2G4EN SYLODIVTLO20DBM2G4AUXEN SYLODIVTLO20DBM2G4EN SYLODIVRLOADCCLKSEL

SYLODIVEN : SYLODIVEN
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYLODIVLDOBIASEN : SYLODIVLDOBIASEN
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYLODIVLDOEN : SYLODIVLDOEN
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYLODIVRLOADCCLK2G4EN : SYLODIVRLOADCCLK2G4EN
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYLODIVTLO0DBM2G4AUXEN : SYLODIVTLO0DBM2G4AUXEN
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYLODIVTLO0DBM2G4EN : SYLODIVTLO0DBM2G4EN
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYLODIVTLO20DBM2G4AUXEN : SYLODIVTLO20DBM2G4AUXEN
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYLODIVTLO20DBM2G4EN : SYLODIVTLO20DBM2G4EN
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYLODIVRLOADCCLKSEL : SYLODIVRLOADCCLKSEL
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : adc_clk_div8


1 : adc_clk_div16


End of enumeration elements list.


SYMMDCTRL


address_offset : 0x188 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYMMDCTRL SYMMDCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYMMDDIVRSDIG SYMMDMODERX SYMMDMODETX SYMMDENRSDIG

SYMMDDIVRSDIG : SYMMDDIVRSDIG
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : Divideby1


1 : Divideby2


2 : Divideby4


3 : Divideby8


End of enumeration elements list.

SYMMDMODERX : SYMMDMODERX
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : rx_w_swctrl


1 : rx_wo_swctrl


2 : qnc_dsm2


3 : qnc_dsm3


4 : rxlp_wo_swctrl


5 : notuse_5


6 : notuse_6


7 : notuse_7


End of enumeration elements list.

SYMMDMODETX : SYMMDMODETX
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : rx_w_swctrl


1 : rx_wo_swctrl


2 : qnc_dsm2


3 : qnc_dsm3


4 : rxlp_wo_swctrl


5 : notuse_5


6 : notuse_6


7 : notuse_7


End of enumeration elements list.

SYMMDENRSDIG : SYMMDENRSDIG
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.


DIGCLKRETIMECTRL

No Description
address_offset : 0x190 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIGCLKRETIMECTRL DIGCLKRETIMECTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIGCLKRETIMEENRETIME DIGCLKRETIMEDISRETIME DIGCLKRETIMERESETN DIGCLKRETIMELIMITH DIGCLKRETIMELIMITL

DIGCLKRETIMEENRETIME : DIGCLKRETIMEENRETIME
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

DIGCLKRETIMEDISRETIME : DIGCLKRETIMEDISRETIME
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : enable_retime


1 : disable_retime


End of enumeration elements list.

DIGCLKRETIMERESETN : DIGCLKRETIMERESETN
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : reset


1 : operate


End of enumeration elements list.

DIGCLKRETIMELIMITH : DIGCLKRETIMELIMITH
bits : 4 - 6 (3 bit)
access : read-write

DIGCLKRETIMELIMITL : DIGCLKRETIMELIMITL
bits : 8 - 10 (3 bit)
access : read-write


DIGCLKRETIMESTATUS

No Description
address_offset : 0x194 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIGCLKRETIMESTATUS DIGCLKRETIMESTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIGCLKRETIMECLKSEL DIGCLKRETIMERESETNLO

DIGCLKRETIMECLKSEL : DIGCLKRETIMECLKSEL
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : use_raw_clk


1 : use_retimed_clk


End of enumeration elements list.

DIGCLKRETIMERESETNLO : DIGCLKRETIMERESETNLO
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : lo


1 : hi


End of enumeration elements list.


XORETIMECTRL

No Description
address_offset : 0x198 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XORETIMECTRL XORETIMECTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XORETIMEENRETIME XORETIMEDISRETIME XORETIMERESETN XORETIMELIMITH XORETIMELIMITL

XORETIMEENRETIME : XORETIMEENRETIME
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

XORETIMEDISRETIME : XORETIMEDISRETIME
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : enable_retime


1 : disable_retime


End of enumeration elements list.

XORETIMERESETN : XORETIMERESETN
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : reset


1 : operate


End of enumeration elements list.

XORETIMELIMITH : XORETIMELIMITH
bits : 4 - 6 (3 bit)
access : read-write

XORETIMELIMITL : XORETIMELIMITL
bits : 8 - 10 (3 bit)
access : read-write


XORETIMESTATUS

No Description
address_offset : 0x19C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

XORETIMESTATUS XORETIMESTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XORETIMECLKSEL XORETIMERESETNLO

XORETIMECLKSEL : XORETIMECLKSEL
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : use_raw_clk


1 : use_retimed_clk


End of enumeration elements list.

XORETIMERESETNLO : XORETIMERESETNLO
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : lo


1 : hi


End of enumeration elements list.


AGCOVERWRITE0

No Description
address_offset : 0x1A0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AGCOVERWRITE0 AGCOVERWRITE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENMANLNAMIXRFATT ENMANLNAMIXSLICE ENMANPGAGAIN ENMANIFADCSCALE MANLNAMIXSLICE0 MANLNAMIXSLICE1 MANPGAGAIN MANIFADCSCALE

ENMANLNAMIXRFATT : Enable RAC Overwite PN
bits : 0 - 0 (1 bit)
access : read-write

ENMANLNAMIXSLICE : Enable RAC Overwite LNA
bits : 1 - 1 (1 bit)
access : read-write

ENMANPGAGAIN : Enable RAC Overwite PGA
bits : 2 - 2 (1 bit)
access : read-write

ENMANIFADCSCALE : Enable RAC Overwite PN
bits : 3 - 3 (1 bit)
access : read-write

MANLNAMIXSLICE0 : RAC Overwite LNA
bits : 4 - 9 (6 bit)
access : read-write

MANLNAMIXSLICE1 : RAC Overwite LNA
bits : 10 - 15 (6 bit)
access : read-write

MANPGAGAIN : RAC Overwite PGA
bits : 20 - 23 (4 bit)
access : read-write

MANIFADCSCALE : RAC Overwite PGA
bits : 24 - 25 (2 bit)
access : read-write


AGCOVERWRITE1

No Description
address_offset : 0x1A4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AGCOVERWRITE1 AGCOVERWRITE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MANLNAMIXRFATT0 MANLNAMIXRFATT1

MANLNAMIXRFATT0 : RAC Overwite PN
bits : 0 - 13 (14 bit)
access : read-write

MANLNAMIXRFATT1 : RAC Overwite PN
bits : 16 - 29 (14 bit)
access : read-write


AGCOVERWRITE2

No Description
address_offset : 0x1A8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AGCOVERWRITE2 AGCOVERWRITE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENMANFENOTCH MANFENOTCHEN MANFENOTCHATTNSEL MANFENOTCHRATTNENRF0 MANFENOTCHRATTNENRF1 MANFENOTCHCAPCRSE MANFENOTCHCAPFINE

ENMANFENOTCH : Enable RAC Overwrite FENOTCH
bits : 0 - 0 (1 bit)
access : read-write

MANFENOTCHEN : RAC Overwrite fenotchen
bits : 1 - 1 (1 bit)
access : read-write

MANFENOTCHATTNSEL : RAC Overwrite fenotchattnsel
bits : 2 - 5 (4 bit)
access : read-write

MANFENOTCHRATTNENRF0 : RAC Overwrite fenotchrattnenrf0
bits : 6 - 6 (1 bit)
access : read-write

MANFENOTCHRATTNENRF1 : RAC Overwrite fenotchrattnenrf1
bits : 7 - 7 (1 bit)
access : read-write

MANFENOTCHCAPCRSE : RAC Overwrite fenotchcapcrse
bits : 8 - 11 (4 bit)
access : read-write

MANFENOTCHCAPFINE : RAC Overwrite fenotchcapfine
bits : 12 - 15 (4 bit)
access : read-write


IF

No Description
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATECHANGE STIMCMPEV SEQLOCKUP SEQRESETREQ SEQ

STATECHANGE : Radio State Change
bits : 0 - 0 (1 bit)
access : read-write

STIMCMPEV : STIMER Compare Event
bits : 1 - 1 (1 bit)
access : read-write

SEQLOCKUP : SEQ locked up
bits : 2 - 2 (1 bit)
access : read-write

SEQRESETREQ : SEQ reset request
bits : 3 - 3 (1 bit)
access : read-write

SEQ : Sequencer Interrupt Flags
bits : 16 - 23 (8 bit)
access : read-write


PACTRL

No Description
address_offset : 0x1C8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PACTRL PACTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX0DBMLATCHBYPASS TX0DBMSLICERESET TXPABYPASSPREDRVREG TXPAPULLDOWNVDDPA TXPAPOWER TXPALATCHBYPASS10DBM TXPALATCHBYPASS20DBM TXPASELPREDRVREGVDDPA TXPASELPREDRVREGVDDRF TXPASELSLICE TXPASLICERST

TX0DBMLATCHBYPASS : TX0DBMLATCHBYPASS
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TX0DBMSLICERESET : TX0DBMSLICERESET
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : active


1 : reset


End of enumeration elements list.

TXPABYPASSPREDRVREG : TXPABYPASSPREDRVREG
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : not_bypass


1 : bypass


End of enumeration elements list.

TXPAPULLDOWNVDDPA : TXPAPULLDOWNVDDPA
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : not_pull_down


1 : pull_down_vddpa


End of enumeration elements list.

TXPAPOWER : TXPAPOWER
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0 : t0stripeon


1 : t1stripeon


2 : t2stripeon


3 : t3stripeon


4 : t4stripeon


5 : t5stripeon


6 : t6stripeon


7 : t7stripeon


8 : t8stripeon


9 : t9stripeon


10 : t10stripeon


11 : t11stripeon


12 : t12stripeon


13 : t13stripeon


14 : t14stripeon


15 : t15stripeon


End of enumeration elements list.

TXPALATCHBYPASS10DBM : TXPALATCHBYPASS10DBM
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TXPALATCHBYPASS20DBM : TXPALATCHBYPASS20DBM
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

TXPASELPREDRVREGVDDPA : TXPASELPREDRVREGVDDPA
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : not_selected


1 : selected


End of enumeration elements list.

TXPASELPREDRVREGVDDRF : TXPASELPREDRVREGVDDRF
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : not_selected


1 : selected


End of enumeration elements list.

TXPASELSLICE : TXPASELSLICE
bits : 12 - 15 (4 bit)
access : read-write

TXPASLICERST : TXPASLICERST
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.


FENOTCH0

No Description
address_offset : 0x1CC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FENOTCH0 FENOTCH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FENOTCHVBIAS

FENOTCHVBIAS : FENOTCHVBIAS
bits : 12 - 14 (3 bit)
access : read-write


FENOTCH1

No Description
address_offset : 0x1D0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FENOTCH1 FENOTCH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FENOTCHENVDDSW FENOTCHRCCALEN FENOTCHRCCALCOUNTER FENOTCHRCCALOSC FENOTCHRCCALOUT

FENOTCHENVDDSW : FENOTCHENVDDSW
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

FENOTCHRCCALEN : FENOTCHRCCALEN
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

FENOTCHRCCALCOUNTER : FENOTCHRCCALCOUNTER
bits : 8 - 15 (8 bit)
access : read-write

FENOTCHRCCALOSC : FENOTCHRCCALOSC
bits : 16 - 19 (4 bit)
access : read-write

FENOTCHRCCALOUT : FENOTCHRCCALOUT
bits : 20 - 20 (1 bit)
access : read-only


IEN

No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATECHANGE STIMCMPEV SEQLOCKUP SEQRESETREQ SEQ

STATECHANGE : Radio State Change Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

STIMCMPEV : STIMER Compare Event Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

SEQLOCKUP : SEQ locked up Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

SEQRESETREQ : SEQ reset request Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

SEQ : Sequencer Flags Interrupt Enable
bits : 16 - 23 (8 bit)
access : read-write


TESTCTRL

No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TESTCTRL TESTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODEN DEMODEN

MODEN : Modulator enable
bits : 0 - 0 (1 bit)
access : read-write

DEMODEN : Demodulator enable
bits : 1 - 1 (1 bit)
access : read-write


SEQIF

No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQIF SEQIF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATECHANGESEQ STIMCMPEVSEQ DEMODRXREQCLRSEQ PRSEVENTSEQ STATEOFF STATERXWARM STATERXSEARCH STATERXFRAME STATERXPD STATERX2RX STATERXOVERFLOW STATERX2TX STATETXWARM STATETX STATETXPD STATETX2RX STATETX2TX STATESHUTDOWN

STATECHANGESEQ : Radio State Change
bits : 0 - 0 (1 bit)
access : read-write

STIMCMPEVSEQ : STIMER Compare Event
bits : 1 - 1 (1 bit)
access : read-write

DEMODRXREQCLRSEQ : Demod RX request clear
bits : 2 - 2 (1 bit)
access : read-write

PRSEVENTSEQ : SEQ PRS Event
bits : 3 - 3 (1 bit)
access : read-write

STATEOFF : entering STATE_OFF
bits : 16 - 16 (1 bit)
access : read-write

STATERXWARM : entering STATE_RXWARM
bits : 17 - 17 (1 bit)
access : read-write

STATERXSEARCH : entering STATE_RXSEARCH
bits : 18 - 18 (1 bit)
access : read-write

STATERXFRAME : entering STATE_RXFRAME
bits : 19 - 19 (1 bit)
access : read-write

STATERXPD : entering STATE_RXPD
bits : 20 - 20 (1 bit)
access : read-write

STATERX2RX : entering STATE_RX2RX
bits : 21 - 21 (1 bit)
access : read-write

STATERXOVERFLOW : entering STATE_RXOVERFLOW
bits : 22 - 22 (1 bit)
access : read-write

STATERX2TX : entering STATE_RX2TX
bits : 23 - 23 (1 bit)
access : read-write

STATETXWARM : entering STATE_TXWARM
bits : 24 - 24 (1 bit)
access : read-write

STATETX : entering STATE_TX
bits : 25 - 25 (1 bit)
access : read-write

STATETXPD : entering STATE_TXPD
bits : 26 - 26 (1 bit)
access : read-write

STATETX2RX : entering STATE_TX2RX
bits : 27 - 27 (1 bit)
access : read-write

STATETX2TX : entering STATE_TX2TX
bits : 28 - 28 (1 bit)
access : read-write

STATESHUTDOWN : entering STATE_SHUTDOWN
bits : 29 - 29 (1 bit)
access : read-write


SEQIEN

No Description
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQIEN SEQIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATECHANGESEQ STIMCMPEVSEQ DEMODRXREQCLRSEQ PRSEVENTSEQ STATEOFF STATERXWARM STATERXSEARCH STATERXFRAME STATERXPD STATERX2RX STATERXOVERFLOW STATERX2TX STATETXWARM STATETX STATETXPD STATETX2RX STATETX2TX STATESHUTDOWN

STATECHANGESEQ : Radio State Change Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

STIMCMPEVSEQ : STIMER Compare Event Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

DEMODRXREQCLRSEQ : Demod RX req clr Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

PRSEVENTSEQ : PRS SEQ EVENT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

STATEOFF : STATE_OFF Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write

STATERXWARM : STATE_RXWARM Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write

STATERXSEARCH : STATE_RXSEARC Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write

STATERXFRAME : STATE_RXFRAME Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write

STATERXPD : STATE_RXPD Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write

STATERX2RX : STATE_RX2RX Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write

STATERXOVERFLOW : STATE_RXOVERFLOW Interrupt Enable
bits : 22 - 22 (1 bit)
access : read-write

STATERX2TX : STATE_RX2TX Interrupt Enable
bits : 23 - 23 (1 bit)
access : read-write

STATETXWARM : STATE_TXWARM Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write

STATETX : STATE_TX Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-write

STATETXPD : STATE_TXPD Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-write

STATETX2RX : STATE_TX2RX Interrupt Enable
bits : 27 - 27 (1 bit)
access : read-write

STATETX2TX : STATE_TX2TX Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-write

STATESHUTDOWN : STATE_SHUTDOWN Interrupt Enable
bits : 29 - 29 (1 bit)
access : read-write


STATUS1

No Description
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS1 STATUS1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXMASK

TXMASK : Transmit Enable Mask
bits : 0 - 7 (8 bit)
access : read-only


STIMER

No Description
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STIMER STIMER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STIMER

STIMER : STIMER Register
bits : 0 - 15 (16 bit)
access : read-only


STIMERCOMP

No Description
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STIMERCOMP STIMERCOMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STIMERCOMP

STIMERCOMP : STIMER Compare Register
bits : 0 - 15 (16 bit)
access : read-write


SEQCTRL

No Description
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQCTRL SEQCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPACT COMPINVALMODE RELATIVE STIMERALWAYSRUN STIMERDEBUGRUN STATEDEBUGRUN SWIRQ

COMPACT : STIMER Compare Action
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : WRAP

STIMER wraps when reaching STIMERCOMP

1 : CONTINUE

STIMER continues when reaching STIMERCOMP

End of enumeration elements list.

COMPINVALMODE : STIMER Comp Invalid Mode
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : NEVER

STIMERCOMP is always valid

1 : STATECHANGE

STIMERCOMP is invalidated when the RSM changes state

2 : COMPEVENT

STIMERCOMP is invalidated when an STIMER compare event occurs

3 : STATECOMP

STIMERCOMP is invalidated both when the RSM changes state and when a compare event occurs

End of enumeration elements list.

RELATIVE : STIMER Compare value relative
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : Absolute

The compare value set for stimer is an absolute value.

1 : Relative

The compare value set for stimer is a relative value. It takes the amount of time you set to make compare event happens.

End of enumeration elements list.

STIMERALWAYSRUN : STIMER always Run
bits : 4 - 4 (1 bit)
access : read-write

STIMERDEBUGRUN : STIMER Debug Run
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : X0

STIMER is not running when the Sequencer is halted.

1 : X1

STIMER is running when the Sequencer is halted.

End of enumeration elements list.

STATEDEBUGRUN : FSM state Debug Run
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : X0

FSM keeps unchanged when the Sequencer is halted

1 : X1

FSM keeps going when the Sequencer is halted

End of enumeration elements list.

SWIRQ : SW spare IRQ
bits : 24 - 25 (2 bit)
access : read-write


SCRATCH0

No Description
address_offset : 0x3E0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH0 SCRATCH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH0

SCRATCH0 : SCRATCH0
bits : 0 - 31 (32 bit)
access : read-write


SCRATCH1

No Description
address_offset : 0x3E4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH1 SCRATCH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH1

SCRATCH1 : SCRATCH1
bits : 0 - 31 (32 bit)
access : read-write


SCRATCH2

No Description
address_offset : 0x3E8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH2 SCRATCH2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH2

SCRATCH2 : SCRATCH2
bits : 0 - 31 (32 bit)
access : read-write


SCRATCH3

No Description
address_offset : 0x3EC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH3 SCRATCH3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH3

SCRATCH3 : SCRATCH3
bits : 0 - 31 (32 bit)
access : read-write


SCRATCH4

No Description
address_offset : 0x3F0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH4 SCRATCH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH4

SCRATCH4 : SCRATCH4
bits : 0 - 31 (32 bit)
access : read-write


SCRATCH5

No Description
address_offset : 0x3F4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH5 SCRATCH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH5

SCRATCH5 : SCRATCH5
bits : 0 - 31 (32 bit)
access : read-write


SCRATCH6

No Description
address_offset : 0x3F8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH6 SCRATCH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH6

SCRATCH6 : SCRATCH6
bits : 0 - 31 (32 bit)
access : read-write


SCRATCH7

No Description
address_offset : 0x3FC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH7 SCRATCH7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH7

SCRATCH7 : SCRATCH7
bits : 0 - 31 (32 bit)
access : read-write


EN

No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : Enable peripheral clock to this module
bits : 0 - 0 (1 bit)
access : read-write


PRESC

No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRESC PRESC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STIMER

STIMER : STIMER Prescaler
bits : 0 - 6 (7 bit)
access : read-write


SR0

No Description
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR0 SR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SR0

SR0 : Sequencer Storage Register 0
bits : 0 - 31 (32 bit)
access : read-write


SR1

No Description
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR1 SR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SR1

SR1 : Sequencer Storage Register 1
bits : 0 - 31 (32 bit)
access : read-write


SR2

No Description
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR2 SR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SR2

SR2 : Sequencer Storage Register 2
bits : 0 - 31 (32 bit)
access : read-write


SR3

No Description
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR3 SR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SR3

SR3 : Sequencer Storage Register 3
bits : 0 - 31 (32 bit)
access : read-write


STCTRL

No Description
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STCTRL STCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STCAL STSKEW

STCAL : Systick timer freq cal
bits : 0 - 23 (24 bit)
access : read-write

STSKEW : Systick timer skew
bits : 24 - 24 (1 bit)
access : read-write


FRCTXWORD

No Description
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRCTXWORD FRCTXWORD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : FRC write data
bits : 0 - 7 (8 bit)
access : read-write


FRCRXWORD

No Description
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FRCRXWORD FRCRXWORD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA

RDATA : FRC read data
bits : 0 - 7 (8 bit)
access : read-only


EM1PCSR

No Description
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EM1PCSR EM1PCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RADIOEM1PMODE RADIOEM1PDISSWREQ MCUEM1PMODE MCUEM1PDISSWREQ RADIOEM1PREQ RADIOEM1PACK RADIOEM1PHWREQ

RADIOEM1PMODE :
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : HWCTRL

Hardware Controls EM1P Request Signal

1 : SWCTRL

Software Controls EM1P Request Signal

End of enumeration elements list.

RADIOEM1PDISSWREQ :
bits : 1 - 1 (1 bit)
access : read-write

MCUEM1PMODE :
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : HWCTRL

Hardware Controls EM1P Request Signal.

1 : SWCTRL

Software Controls EM1P Request Signal

End of enumeration elements list.

MCUEM1PDISSWREQ :
bits : 5 - 5 (1 bit)
access : read-write

RADIOEM1PREQ :
bits : 16 - 16 (1 bit)
access : read-only

RADIOEM1PACK :
bits : 17 - 17 (1 bit)
access : read-only

RADIOEM1PHWREQ :
bits : 18 - 18 (1 bit)
access : read-only


THMSW

No Description
address_offset : 0x7E8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

THMSW THMSW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN HALFSWITCH

EN : Enable Switch
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

HALFSWITCH : Halfswitch Mode enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.


RXENSRCEN

No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXENSRCEN RXENSRCEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRXEN CHANNELBUSYEN TIMDETEN PREDETEN FRAMEDETEN DEMODRXREQEN PRSRXEN

SWRXEN : SW RX Enable
bits : 0 - 7 (8 bit)
access : read-write

CHANNELBUSYEN : Channel Busy Enable
bits : 8 - 8 (1 bit)
access : read-write

TIMDETEN : Timing Detected Enable
bits : 9 - 9 (1 bit)
access : read-write

PREDETEN : Preamble Detected Enable
bits : 10 - 10 (1 bit)
access : read-write

FRAMEDETEN : Frame Detected Enable
bits : 11 - 11 (1 bit)
access : read-write

DEMODRXREQEN : DEMOD RX Request Enable
bits : 12 - 12 (1 bit)
access : read-write

PRSRXEN : PRS RX Enable
bits : 13 - 13 (1 bit)
access : read-write


SYNTHENCTRL

No Description
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNTHENCTRL SYNTHENCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCOSTARTUP VCBUFEN MMDPOWERBALANCEDISABLE LPFBWSEL

VCOSTARTUP : SYVCOFASTSTARTUP
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : fast_start_up_0


1 : fast_start_up_1


End of enumeration elements list.

VCBUFEN : SYLPFVCBUFEN
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

MMDPOWERBALANCEDISABLE : SYMMDPOWERBALANCEENB
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : EnablePowerbleed


1 : DisablePowerBleed


End of enumeration elements list.

LPFBWSEL : LPF bandwidth register selection
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : LPFBWRX

Select LPFBWRX

1 : LPFBWTX

Select LPFBWTX

End of enumeration elements list.


SYNTHREGCTRL

No Description
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNTHREGCTRL SYNTHREGCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMDLDOVREFTRIM CHPLDOVREFTRIM

MMDLDOVREFTRIM : SYTRIMMMDREGVREF
bits : 10 - 12 (3 bit)
access : read-write

Enumeration:

0 : vref0p6000


1 : vref0p6125


2 : vref0p6250


3 : vref0p6375


4 : vref0p6500


5 : vref0p6625


6 : vref0p6750


7 : vref0p6875


End of enumeration elements list.

CHPLDOVREFTRIM : SYTRIMCHPREGVREF
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : vref0p6000


1 : vref0p6125


2 : vref0p6250


3 : vref0p6375


4 : vref0p6500


5 : vref0p6625


6 : vref0p6750


7 : vref0p6875


End of enumeration elements list.


VCOCTRL

No Description
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VCOCTRL VCOCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCOAMPLITUDE VCODETAMPLITUDERX VCODETAMPLITUDETX

VCOAMPLITUDE : SYVCOAMPLOPEN
bits : 0 - 3 (4 bit)
access : read-write

VCODETAMPLITUDERX : SYVCOAMPLPKDRX
bits : 4 - 7 (4 bit)
access : read-write

VCODETAMPLITUDETX : SYVCOAMPLPKDTX
bits : 8 - 11 (4 bit)
access : read-write


STATUS2

No Description
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS2 STATUS2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREVSTATE1 PREVSTATE2 PREVSTATE3 CURRSTATE

PREVSTATE1 : Previous Radio State
bits : 0 - 3 (4 bit)
access : read-only

Enumeration:

0 : OFF

Radio is off

1 : RXWARM

Radio is enabling receiver

2 : RXSEARCH

Radio is listening for incoming frames

3 : RXFRAME

Radio is receiving a frame

4 : RXPD

Radio is powering down receiver and going to OFF state

5 : RX2RX

Radio remains in receive mode after frame reception is completed

6 : RXOVERFLOW

Received data was lost due to full receive buffer

7 : RX2TX

Radio is disabling receiver and enabling transmitter

8 : TXWARM

Radio is enabling transmitter

9 : TX

Radio is transmitting data

10 : TXPD

Radio is powering down transmitter and going to OFF state

11 : TX2RX

Radio is disabling transmitter and enabling reception

12 : TX2TX

Radio is preparing for a transmission after the previous transmission was ended

13 : SHUTDOWN

Radio is powering down receiver and going to OFF state

14 : POR

Radio power-on-reset state

End of enumeration elements list.

PREVSTATE2 : Previous Radio State 2
bits : 4 - 7 (4 bit)
access : read-only

Enumeration:

0 : OFF

Radio is off

1 : RXWARM

Radio is enabling receiver

2 : RXSEARCH

Radio is listening for incoming frames

3 : RXFRAME

Radio is receiving a frame

4 : RXPD

Radio is powering down receiver and going to OFF state

5 : RX2RX

Radio remains in receive mode after frame reception is completed

6 : RXOVERFLOW

Received data was lost due to full receive buffer

7 : RX2TX

Radio is disabling receiver and enabling transmitter

8 : TXWARM

Radio is enabling transmitter

9 : TX

Radio is transmitting data

10 : TXPD

Radio is powering down transmitter and going to OFF state

11 : TX2RX

Radio is disabling transmitter and enabling reception

12 : TX2TX

Radio is preparing for a transmission after the previous transmission was ended

13 : SHUTDOWN

Radio is powering down receiver and going to OFF state

14 : POR

Radio power-on-reset state

End of enumeration elements list.

PREVSTATE3 : Previous Radio State 3
bits : 8 - 11 (4 bit)
access : read-only

Enumeration:

0 : OFF

Radio is off

1 : RXWARM

Radio is enabling receiver

2 : RXSEARCH

Radio is listening for incoming frames

3 : RXFRAME

Radio is receiving a frame

4 : RXPD

Radio is powering down receiver and going to OFF state

5 : RX2RX

Radio remains in receive mode after frame reception is completed

6 : RXOVERFLOW

Received data was lost due to full receive buffer

7 : RX2TX

Radio is disabling receiver and enabling transmitter

8 : TXWARM

Radio is enabling transmitter

9 : TX

Radio is transmitting data

10 : TXPD

Radio is powering down transmitter and going to OFF state

11 : TX2RX

Radio is disabling transmitter and enabling reception

12 : TX2TX

Radio is preparing for a transmission after the previous transmission was ended

13 : SHUTDOWN

Radio is powering down receiver and going to OFF state

14 : POR

Radio power-on-reset state

End of enumeration elements list.

CURRSTATE : Current Radio State
bits : 12 - 15 (4 bit)
access : read-only

Enumeration:

0 : OFF

Radio is off

1 : RXWARM

Radio is enabling receiver

2 : RXSEARCH

Radio is listening for incoming frames

3 : RXFRAME

Radio is receiving a frame

4 : RXPD

Radio is powering down receiver and going to OFF state

5 : RX2RX

Radio remains in receive mode after frame reception is completed

6 : RXOVERFLOW

Received data was lost due to full receive buffer

7 : RX2TX

Radio is disabling receiver and enabling transmitter

8 : TXWARM

Radio is enabling transmitter

9 : TX

Radio is transmitting data

10 : TXPD

Radio is powering down transmitter and going to OFF state

11 : TX2RX

Radio is disabling transmitter and enabling reception

12 : TX2TX

Radio is preparing for a transmission after the previous transmission was ended

13 : SHUTDOWN

Radio is powering down receiver and going to OFF state

14 : POR

Radio power-on-reset state

End of enumeration elements list.


IFPGACTRL

No Description
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFPGACTRL IFPGACTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCCALON DCRSTEN DCESTIEN DCCALDEC0 DCCALDCGEAR

DCCALON : Enable/Disable DCCAL in DEMOD
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

DC ESTI DISABLED

1 : ENABLE

DC ESTI ENABLED

End of enumeration elements list.

DCRSTEN : DC Compensation Filter Reset Enable
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

DC Comp out of Reset

1 : ENABLE

DC Comp in Reset

End of enumeration elements list.

DCESTIEN : DCESTIEN Override for RAC
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

DCESTI Disabled in MODEM

1 : ENABLE

DCESTI Enabled in MODEM

End of enumeration elements list.

DCCALDEC0 : DEC0 Value for DCCAL
bits : 22 - 24 (3 bit)
access : read-write

Enumeration:

0 : DF3

Decimation Factor 0 = 3. Cutoff 0.050 * fHFXO.

1 : DF4WIDE

Decimation Factor 0 = 4. Cutoff 0.069 * fHFXO.

2 : DF4NARROW

Decimation Factor 0 = 4. Cutoff 0.037 * fHFXO.

3 : DF8WIDE

Decimation Factor 0 = 8. Cutoff 0.012 * fHFXO.

4 : DF8NARROW

Decimation Factor 0 = 8. Cutoff 0.005 * fHFXO.

End of enumeration elements list.

DCCALDCGEAR : DC COMP GEAR Value for DCCAL
bits : 25 - 27 (3 bit)
access : read-write


PAENCTRL

No Description
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAENCTRL PAENCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARAMP INVRAMPCLK DIV2RAMPCLK RSTDIV2RAMPCLK

PARAMP : PA output level ramping
bits : 8 - 8 (1 bit)
access : read-write

INVRAMPCLK : Invert PA ramping clock
bits : 16 - 16 (1 bit)
access : read-write

DIV2RAMPCLK : Div PA ramping clock by 2
bits : 17 - 17 (1 bit)
access : read-write

RSTDIV2RAMPCLK : Reset Div2 PA ramping clock
bits : 18 - 18 (1 bit)
access : read-write


APC

No Description
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APC APC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENAPCSW AMPCONTROLLIMITSW

ENAPCSW : software control bit for apc
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLE


1 : ENABLE


End of enumeration elements list.

AMPCONTROLLIMITSW : software amp_control top limit
bits : 24 - 31 (8 bit)
access : read-write


STATUS

No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXMASK FORCESTATEACTIVE TXAFTERFRAMEPEND TXAFTERFRAMEACTIVE SEQSLEEPING SEQSLEEPDEEP STATE SEQACTIVE TXENS RXENS

RXMASK : Receive Enable Mask
bits : 0 - 15 (16 bit)
access : read-only

FORCESTATEACTIVE : FSM state force active
bits : 19 - 19 (1 bit)
access : read-only

Enumeration:

0 : X0

No special state transition is currently in progress

1 : X1

A forced state transition is currently in progress

End of enumeration elements list.

TXAFTERFRAMEPEND : TX After Frame Pending
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

0 : X0

A transmit after frame operation is currently not pending.

1 : X1

A transmit after frame operation is currently pending.

End of enumeration elements list.

TXAFTERFRAMEACTIVE : TX After Frame Active
bits : 21 - 21 (1 bit)
access : read-only

Enumeration:

0 : X0

The currently ongoing TX was not initiated by a TXAFTERFRAME command.

1 : X1

The currently ongoing TX was initiated by a TXAFTERFRAME command.

End of enumeration elements list.

SEQSLEEPING : SEQ in sleeping
bits : 22 - 22 (1 bit)
access : read-only

SEQSLEEPDEEP : SEQ in deep sleep
bits : 23 - 23 (1 bit)
access : read-only

STATE : Radio State
bits : 24 - 27 (4 bit)
access : read-only

Enumeration:

0 : OFF

Radio is off

1 : RXWARM

Radio is enabling receiver

2 : RXSEARCH

Radio is listening for incoming frames

3 : RXFRAME

Radio is receiving a frame

4 : RXPD

Radio is powering down receiver and going to OFF state

5 : RX2RX

Radio remains in receive mode after frame reception is completed

6 : RXOVERFLOW

Received data was lost due to full receive buffer

7 : RX2TX

Radio is disabling receiver and enabling transmitter

8 : TXWARM

Radio is enabling transmitter

9 : TX

Radio is transmitting data

10 : TXPD

Radio is powering down transmitter and going to OFF state

11 : TX2RX

Radio is disabling transmitter and enabling reception

12 : TX2TX

Radio is preparing for a transmission after the previous transmission was ended

13 : SHUTDOWN

Radio is powering down receiver and going to OFF state

14 : POR

Radio power-on-reset state

End of enumeration elements list.

SEQACTIVE : SEQ active
bits : 28 - 28 (1 bit)
access : read-only

TXENS : TXEN Status
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

0 : X0

TXEN is not set.

1 : X1

TXEN is set.

End of enumeration elements list.

RXENS : RXEN Status
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : X0

RXEN is not set.

1 : X1

RXEN is set.

End of enumeration elements list.


ANTDIV

No Description
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANTDIV ANTDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTDIVLNAMIXEN0 INTDIVLNAMIXRFATTDCEN0 INTDIVLNAMIXRFPKDENRF0 INTDIVSYLODIVRLO02G4EN INTDIVLNAMIXEN1 INTDIVLNAMIXRFATTDCEN1 INTDIVLNAMIXRFPKDENRF1 INTDIVSYLODIVRLO12G4EN ANTDIVSTATUS

INTDIVLNAMIXEN0 : INTDIVLNAMIXEN0
bits : 0 - 0 (1 bit)
access : read-write

INTDIVLNAMIXRFATTDCEN0 : INTDIVLNAMIXRFATTDCEN0
bits : 2 - 2 (1 bit)
access : read-write

INTDIVLNAMIXRFPKDENRF0 : INTDIVLNAMIXRFPKDENRF0
bits : 3 - 3 (1 bit)
access : read-write

INTDIVSYLODIVRLO02G4EN : INTDIVSYLODIVRLO02G4EN
bits : 4 - 4 (1 bit)
access : read-write

INTDIVLNAMIXEN1 : INTDIVLNAMIXEN1
bits : 5 - 5 (1 bit)
access : read-write

INTDIVLNAMIXRFATTDCEN1 : INTDIVLNAMIXRFATTDCEN1
bits : 7 - 7 (1 bit)
access : read-write

INTDIVLNAMIXRFPKDENRF1 : INTDIVLNAMIXRFPKDENRF1
bits : 8 - 8 (1 bit)
access : read-write

INTDIVSYLODIVRLO12G4EN : INTDIVSYLODIVRLO12G4EN
bits : 9 - 9 (1 bit)
access : read-write

ANTDIVSTATUS : ANTDIVSTATUS
bits : 10 - 11 (2 bit)
access : read-only

Enumeration:

0 : OFF

Both antenna disabled

1 : ANT1

Antenna 0 enabled

2 : ANT2

Antenna 1 enabled

3 : BOTH

Both Antenna enabled

End of enumeration elements list.


AUXADCTRIM


address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUXADCTRIM AUXADCTRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXADCCLKINVERT AUXADCLDOVREFTRIM AUXADCOUTPUTINVERT AUXADCRCTUNE AUXADCTRIMADCINPUTRES AUXADCTRIMCURRINPUTBUF AUXADCTRIMCURROPA1 AUXADCTRIMCURROPA2 AUXADCTRIMCURRREFBUF AUXADCTRIMCURRTSENSE AUXADCTRIMCURRVCMBUF AUXADCTRIMLDOHIGHCURRENT AUXADCTRIMREFP AUXADCTRIMVREFVCM AUXADCTSENSETRIMVBE2

AUXADCCLKINVERT : AUXADCCLKINVERT
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable_Invert


1 : Enable_Invert


End of enumeration elements list.

AUXADCLDOVREFTRIM : AUXADCLDOVREFTRIM
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : TRIM1p27


1 : TRIM1p3


2 : TRIM1p35


3 : TRIM1p4


End of enumeration elements list.

AUXADCOUTPUTINVERT : AUXADCOUTPUTINVERT
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCRCTUNE : AUXADCRCTUNE
bits : 4 - 8 (5 bit)
access : read-write

AUXADCTRIMADCINPUTRES : AUXADCTRIMADCINPUTRES
bits : 9 - 10 (2 bit)
access : read-write

Enumeration:

0 : RES200k


1 : RES250k


2 : RES300k


3 : RES350k


End of enumeration elements list.

AUXADCTRIMCURRINPUTBUF : AUXADCTRIMCURRINPUTBUF
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : Typ_minus_40pct


1 : Typ_minus_20pct


2 : Typ


3 : Typ_plus_20pct


End of enumeration elements list.

AUXADCTRIMCURROPA1 : AUXADCTRIMCURROPA1
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

0 : Typ_minus_40pct


1 : Typ_minus_20pct


2 : Typ


3 : Typ_plus_20pct


End of enumeration elements list.

AUXADCTRIMCURROPA2 : AUXADCTRIMCURROPA2
bits : 15 - 16 (2 bit)
access : read-write

Enumeration:

0 : Typ_minus_40pct


1 : Typ_minus_20pct


2 : Typ


3 : Typ_plus_20pct


End of enumeration elements list.

AUXADCTRIMCURRREFBUF : AUXADCTRIMCURRREFBUF
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0 : Typ_minus_40pct


1 : Typ_minus_20pct


2 : Typ


3 : Typ_plus_20pct


End of enumeration elements list.

AUXADCTRIMCURRTSENSE : AUXADCTRIMCURRTSENSE
bits : 19 - 20 (2 bit)
access : read-write

Enumeration:

0 : Typ_minus_40pct


1 : Typ_minus_20pct


2 : Typ


3 : Typ_plus_20pct


End of enumeration elements list.

AUXADCTRIMCURRVCMBUF : AUXADCTRIMCURRVCMBUF
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

0 : Typ_minus_40pct


1 : Typ_minus_20pct


2 : Typ


3 : Typ_plus_20pct


End of enumeration elements list.

AUXADCTRIMLDOHIGHCURRENT : AUXADCTRIMLDOHIGHCURRENT
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : LowCurrentMode


1 : HighCurrentMode


End of enumeration elements list.

AUXADCTRIMREFP : AUXADCTRIMREFP
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : REF1p05


1 : REF1p16


2 : REF1p2


3 : REF1p25


End of enumeration elements list.

AUXADCTRIMVREFVCM : AUXADCTRIMVREFVCM
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Trim0p6


1 : Trim0p65


2 : Trim0p7


3 : Trim0p75


End of enumeration elements list.

AUXADCTSENSETRIMVBE2 : AUXADCTSENSETRIMVBE2
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : VBE_16uA


1 : VBE_32uA


End of enumeration elements list.


AUXADCEN


address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUXADCEN AUXADCEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXADCENAUXADC AUXADCENINPUTBUFFER AUXADCENLDO AUXADCENOUTPUTDRV AUXADCENPMON AUXADCENRESONDIAGA AUXADCENTSENSE AUXADCENTSENSECAL AUXADCINPUTBUFFERBYPASS AUXADCENMEASTHERMISTOR

AUXADCENAUXADC : AUXADCENAUXADC
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCENINPUTBUFFER : AUXADCENINPUTBUFFER
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCENLDO : AUXADCENLDO
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCENOUTPUTDRV : AUXADCENOUTPUTDRV
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCENPMON : AUXADCENPMON
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCENRESONDIAGA : AUXADCENRESONDIAGA
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCENTSENSE : AUXADCENTSENSE
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCENTSENSECAL : AUXADCENTSENSECAL
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCINPUTBUFFERBYPASS : AUXADCINPUTBUFFERBYPASS
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : Not_Bypassed


1 : Bypassed


End of enumeration elements list.

AUXADCENMEASTHERMISTOR : AUXADCENMEASTHERMISTOR
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.


AUXADCCTRL0

No Description
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUXADCCTRL0 AUXADCCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CYCLES MUXSEL CLRCOUNTER CLRFILTER

CYCLES : Cycle number to run
bits : 0 - 9 (10 bit)
access : read-write

MUXSEL : Select accumulator
bits : 10 - 11 (2 bit)
access : read-write

CLRCOUNTER : Clear counter
bits : 12 - 12 (1 bit)
access : read-write

CLRFILTER : Clear accumulators
bits : 13 - 13 (1 bit)
access : read-write


AUXADCCTRL1


address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUXADCCTRL1 AUXADCCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXADCINPUTRESSEL AUXADCINPUTSELECT AUXADCPMONSELECT AUXADCTSENSESELCURR AUXADCRESET AUXADCTSENSESELVBE AUXADCTHERMISTORFREQSEL

AUXADCINPUTRESSEL : AUXADCINPUTRESSEL
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : RES640kOhm


1 : RES320kOhm


2 : RES160kOhm


3 : RES80kOhm


4 : RES40kOhm


5 : RES20kOhm


6 : RES10kOhm


7 : RES5kOhm


8 : RES2p5kOhm


9 : RES1p25kOhm


10 : RES0p6kOhm


11 : RES_switch


End of enumeration elements list.

AUXADCINPUTSELECT : AUXADCINPUTSELECT
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0 : SEL0


1 : SEL1


2 : SEL2


3 : SEL3


4 : SEL4


5 : SEL5


6 : SEL6


7 : SEL7


8 : SEL8


9 : SEL9


End of enumeration elements list.

AUXADCPMONSELECT : AUXADCPMONSELECT
bits : 8 - 11 (4 bit)
access : read-write

AUXADCTSENSESELCURR : AUXADCTSENSESELCURR
bits : 16 - 20 (5 bit)
access : read-write

AUXADCRESET : AUXADCRESET
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : Reset_Disabled


1 : Reset_Enabled


End of enumeration elements list.

AUXADCTSENSESELVBE : AUXADCTSENSESELVBE
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : VBE1


1 : VBE2


End of enumeration elements list.

AUXADCTHERMISTORFREQSEL : AUXADCTHERMISTORFREQSEL
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

0 : DIV1


1 : DIV2


2 : DIV4


3 : DIV8


4 : DIV16


5 : DIV32


6 : DIV64


7 : DIV128


8 : DIV256


9 : DIV512


10 : DIV1024


End of enumeration elements list.


AUXADCOUT

No Description
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AUXADCOUT AUXADCOUT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXADCOUT

AUXADCOUT : AUXADC output
bits : 0 - 27 (28 bit)
access : read-only


CLKMULTEN0


address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKMULTEN0 CLKMULTEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKMULTBWCAL CLKMULTDISICO CLKMULTENBBDET CLKMULTENBBXLDET CLKMULTENBBXMDET CLKMULTENCFDET CLKMULTENDITHER CLKMULTENDRVADC CLKMULTENDRVN CLKMULTENDRVP CLKMULTENDRVRX2P4G CLKMULTENFBDIV CLKMULTENREFDIV CLKMULTENREG1 CLKMULTENREG2 CLKMULTENREG3 CLKMULTENROTDET CLKMULTENBYPASS40MHZ CLKMULTFREQCAL CLKMULTREG2ADJI CLKMULTREG1ADJV CLKMULTREG2ADJV CLKMULTREG3ADJV

CLKMULTBWCAL : CLKMULTBWCAL
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : bw_1lsb


1 : bw_2lsb


2 : bw_3lsb


3 : bw_4lsb


End of enumeration elements list.

CLKMULTDISICO : CLKMULTDISICO
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : enable


1 : disable


End of enumeration elements list.

CLKMULTENBBDET : CLKMULTENBBDET
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENBBXLDET : CLKMULTENBBXLDET
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENBBXMDET : CLKMULTENBBXMDET
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENCFDET : CLKMULTENCFDET
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENDITHER : CLKMULTENDITHER
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENDRVADC : CLKMULTENDRVADC
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENDRVN : CLKMULTENDRVN
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENDRVP : CLKMULTENDRVP
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENDRVRX2P4G : CLKMULTENDRVRX2P4G
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENFBDIV : CLKMULTENFBDIV
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENREFDIV : CLKMULTENREFDIV
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENREG1 : CLKMULTENREG1
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENREG2 : CLKMULTENREG2
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENREG3 : CLKMULTENREG3
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENROTDET : CLKMULTENROTDET
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENBYPASS40MHZ : CLKMULTENBYPASS40MHZ
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTFREQCAL : CLKMULTFREQCAL
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0 : pedes_14uA


1 : pedes_22uA


2 : pedes_30uA


3 : pedes_38uA


End of enumeration elements list.

CLKMULTREG2ADJI : CLKMULTREG2ADJI
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : I_80uA


1 : I_100uA


2 : I_120uA


3 : I_140uA


End of enumeration elements list.

CLKMULTREG1ADJV : CLKMULTREG1ADJV
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : v1p28


1 : v1p32


2 : v1p33


3 : v1p38


End of enumeration elements list.

CLKMULTREG2ADJV : CLKMULTREG2ADJV
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : v1p03


1 : v1p09


2 : v1p10


3 : v1p16


End of enumeration elements list.

CLKMULTREG3ADJV : CLKMULTREG3ADJV
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

0 : v1p03


1 : v1p06


2 : v1p07


3 : v1p09


End of enumeration elements list.


CLKMULTEN1


address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKMULTEN1 CLKMULTEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKMULTINNIBBLE CLKMULTLDFNIB CLKMULTLDMNIB CLKMULTRDNIBBLE CLKMULTLDCNIB CLKMULTDRVAMPSEL

CLKMULTINNIBBLE : CLKMULTINNIBBLE
bits : 0 - 3 (4 bit)
access : read-write

CLKMULTLDFNIB : CLKMULTLDFNIB
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTLDMNIB : CLKMULTLDMNIB
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTRDNIBBLE : CLKMULTRDNIBBLE
bits : 7 - 8 (2 bit)
access : read-write

Enumeration:

0 : quarter_nibble


1 : fine_nibble


2 : moderate_nibble


3 : coarse_nibble


End of enumeration elements list.

CLKMULTLDCNIB : CLKMULTLDCNIB
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTDRVAMPSEL : CLKMULTDRVAMPSEL
bits : 11 - 16 (6 bit)
access : read-write

Enumeration:

0 : off


1 : slide_x1


3 : slide_x2


7 : slide_x3


15 : slide_x4


31 : slide_x5


63 : slide_x6


End of enumeration elements list.


CLKMULTCTRL


address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKMULTCTRL CLKMULTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKMULTDIVN CLKMULTDIVR CLKMULTDIVX CLKMULTENRESYNC CLKMULTVALID

CLKMULTDIVN : CLKMULTDIVN
bits : 0 - 6 (7 bit)
access : read-write

CLKMULTDIVR : CLKMULTDIVR
bits : 7 - 9 (3 bit)
access : read-write

CLKMULTDIVX : CLKMULTDIVX
bits : 10 - 12 (3 bit)
access : read-write

Enumeration:

0 : div_1


1 : div_2


2 : div_4


3 : div_6


4 : div_8


5 : div10


6 : div12


7 : div14


End of enumeration elements list.

CLKMULTENRESYNC : CLKMULTENRESYNC
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : disable_sync


1 : enable_sync


End of enumeration elements list.

CLKMULTVALID : CLKMULTVALID
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : invalid


1 : valid


End of enumeration elements list.


CLKMULTSTATUS


address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CLKMULTSTATUS CLKMULTSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKMULTOUTNIBBLE CLKMULTACKVALID

CLKMULTOUTNIBBLE : CLKMULTOUTNIBBLE
bits : 0 - 3 (4 bit)
access : read-only

CLKMULTACKVALID : CLKMULTACKVALID
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

0 : invalid


1 : valid


End of enumeration elements list.


IFADCTRIM0


address_offset : 0xEC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFADCTRIM0 IFADCTRIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFADCCLKSEL IFADCLDOSERIESAMPLVL IFADCLDOSHUNTAMPLVL1 IFADCLDOSHUNTAMPLVL2 IFADCLDOSHUNTCURLVL1 IFADCLDOSHUNTCURLVL2 IFADCOTACURRENT IFADCREFBUFAMPLVL IFADCREFBUFCURLVL IFADCSIDETONEAMP IFADCSIDETONEFREQ IFADCENHALFMODE

IFADCCLKSEL : IFADCCLKSEL
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : clk_2p4g


1 : clk_subg


End of enumeration elements list.

IFADCLDOSERIESAMPLVL : IFADCLDOSERIESAMPLVL
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : v1p225


1 : v1p250


2 : v1p275


3 : v1p300


4 : v1p325


5 : v1p350


6 : v1p375


7 : v1p400


End of enumeration elements list.

IFADCLDOSHUNTAMPLVL1 : IFADCLDOSHUNTAMPLVL1
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : v1p125


1 : v1p150


2 : v1p175


3 : v1p200


4 : v1p225


5 : v1p250


6 : v1p275


7 : v1p300


End of enumeration elements list.

IFADCLDOSHUNTAMPLVL2 : IFADCLDOSHUNTAMPLVL2
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

IFADCLDOSHUNTCURLVL1 : IFADCLDOSHUNTCURLVL1
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

0 : i55u


1 : i65u


2 : i70u


3 : i85u


4 : i85u2


5 : i95u


6 : i100u


7 : i110u


End of enumeration elements list.

IFADCLDOSHUNTCURLVL2 : IFADCLDOSHUNTCURLVL2
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

0 : i4u


1 : i4p5u


2 : i5u


3 : i5p5u


4 : i5u2


5 : i5p5u2


6 : i6u


7 : i6p5u


End of enumeration elements list.

IFADCOTACURRENT : IFADCOTACURRENT
bits : 15 - 17 (3 bit)
access : read-write

Enumeration:

0 : i3u


1 : i3p5u


2 : i4u


3 : i4p5u


4 : i4u2


5 : i4p5u2


6 : i5u


7 : i5p5u


End of enumeration elements list.

IFADCREFBUFAMPLVL : IFADCREFBUFAMPLVL
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

0 : v0p88


1 : v0p91


2 : v0p94


3 : v0p97


4 : v1p00


5 : v1p03


6 : v1p06


7 : v1p09


End of enumeration elements list.

IFADCREFBUFCURLVL : IFADCREFBUFCURLVL
bits : 21 - 23 (3 bit)
access : read-write

Enumeration:

0 : i4u


1 : i4p5u


2 : i5u


3 : i5p5u


4 : i5u2


5 : i5p5u2


6 : i6u


7 : i6p5u


End of enumeration elements list.

IFADCSIDETONEAMP : IFADCSIDETONEAMP
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : diff_5p68mV


1 : diff_29p1mV


2 : diff_9p73mV


3 : diff_76p9mV


4 : diff_9p68_mV


5 : diff_51_mV


6 : diff_17p2_mV


7 : disable


End of enumeration elements list.

IFADCSIDETONEFREQ : IFADCSIDETONEFREQ
bits : 27 - 29 (3 bit)
access : read-write

Enumeration:

0 : na0


1 : div_128


2 : div_64


3 : div_32


4 : div_16


5 : div_8


6 : div_4


7 : na7


End of enumeration elements list.

IFADCENHALFMODE : IFADCENHALFMODE
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : full_speed_mode


1 : half_speed_mode


End of enumeration elements list.


IFADCTRIM1


address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFADCTRIM1 IFADCTRIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFADCVCMLVL IFADCENNEGRES IFADCNEGRESCURRENT IFADCNEGRESVCM

IFADCVCMLVL : IFADCVCMLVL
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : vcm_475mV


1 : vcm_500mV


2 : vcm_525mV


3 : vcm_550mV


4 : vcm_575mV


5 : vcm_600mV


6 : vcm_625mV


7 : cm_650mV


End of enumeration elements list.

IFADCENNEGRES : IFADCENNEGRES
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

IFADCNEGRESCURRENT : IFADCNEGRESCURRENT
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0 : i1p0u


1 : i1p5u


2 : i2p0u


3 : i2p5u


4 : i2p0u2


5 : i2p5u2


6 : i3p0u


7 : i3p5u


End of enumeration elements list.

IFADCNEGRESVCM : IFADCNEGRESVCM
bits : 7 - 8 (2 bit)
access : read-write

Enumeration:

0 : r210k_x_1uA


1 : r210k_x_1uA2


2 : r100k_x_2uA


3 : r50k_x_3uA


End of enumeration elements list.


IFADCCAL


address_offset : 0xF4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFADCCAL IFADCCAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFADCENRCCAL IFADCTUNERCCALMODE IFADCTUNERC IFADCRCCALCOUNTERSTARTVAL

IFADCENRCCAL : IFADCENRCCAL
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : rccal_disable


1 : rccal_enable


End of enumeration elements list.

IFADCTUNERCCALMODE : IFADCTUNERCCALMODE
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SYmode


1 : ADCmode


End of enumeration elements list.

IFADCTUNERC : IFADCTUNERC
bits : 8 - 12 (5 bit)
access : read-write

IFADCRCCALCOUNTERSTARTVAL : IFADCRCCALCOUNTERSTARTVAL
bits : 16 - 23 (8 bit)
access : read-write


IFADCSTATUS


address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IFADCSTATUS IFADCSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFADCRCCALOUT

IFADCRCCALOUT : IFADCRCCALOUT
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : lo


1 : hi


End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.