\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IPVERSION
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0ENS : Channel 0 Enabled Status
bits : 0 - 0 (1 bit)
access : read-only
CH1ENS : Channel 1 Enabled Status
bits : 1 - 1 (1 bit)
access : read-only
CH0WARM : Channel 0 Warmed Status
bits : 4 - 4 (1 bit)
access : read-only
CH1WARM : Channel 1 Warmed Status
bits : 5 - 5 (1 bit)
access : read-only
CH0FIFOFULL : Channel 0 FIFO Full Status
bits : 8 - 8 (1 bit)
access : read-only
CH1FIFOFULL : Channel 1 FIFO Full Status
bits : 9 - 9 (1 bit)
access : read-only
CH0FIFOCNT : Channel 0 FIFO Valid Count
bits : 12 - 14 (3 bit)
access : read-only
CH1FIFOCNT : Channel 1 FIFO Valid Count
bits : 15 - 17 (3 bit)
access : read-only
CH0CURRENTSTATE : Channel 0 Current Status
bits : 19 - 19 (1 bit)
access : read-only
CH1CURRENTSTATE : Channel 1 Current Status
bits : 20 - 20 (1 bit)
access : read-only
CH0FIFOEMPTY : Channel 0 FIFO Empty Status
bits : 22 - 22 (1 bit)
access : read-only
CH1FIFOEMPTY : Channel 1 FIFO Empty Status
bits : 23 - 23 (1 bit)
access : read-only
CH0FIFOFLBUSY : CH0 WFIFO Flush Sync Busy
bits : 26 - 26 (1 bit)
access : read-only
CH1FIFOFLBUSY : CH1 WFIFO Flush Sync Busy
bits : 27 - 27 (1 bit)
access : read-only
ABUSINPUTCONFLICT : ABUS Input Conflict Status
bits : 28 - 28 (1 bit)
access : read-only
SINEACTIVE : Sine Wave Output Status on Channel
bits : 29 - 29 (1 bit)
access : read-only
ABUSALLOCERR : ABUS Allocation Error Status
bits : 30 - 30 (1 bit)
access : read-only
SYNCBUSY : Sync Busy Combined
bits : 31 - 31 (1 bit)
access : read-only
No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CONVMODE : Channel 0 Conversion Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CONTINUOUS
DAC channel 0 is set in continuous mode
1 : SAMPLEOFF
DAC channel 0 is set in sample/shut off mode
End of enumeration elements list.
POWERMODE : Channel 0 Power Mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : HIGHPOWER
Default is High Power Mode
1 : LOWPOWER
Set this bit for Low Power Mode
End of enumeration elements list.
TRIGMODE : Channel 0 Trigger Mode
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : NONE
No Conversion Trigger Source Selected for Channel 0
1 : SW
Channel 0 is triggered by Channel 0 FIFO (CH0F) write
2 : SYNCPRS
Channel 0 is triggered by Sync PRS input. PRS Trigger should have the same clock group as VDAC.
4 : INTERNALTIMER
Channel 0 is triggered by Internal Timer Overflow
5 : ASYNCPRS
Channel 0 is triggered by Async PRS input
End of enumeration elements list.
REFRESHSOURCE : Channel 0 Refresh Source
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : NONE
No Refresh Source Selected for Channel 0.
1 : REFRESHTIMER
Channel 0 Refresh triggered by Refresh Timer Overflow
2 : SYNCPRS
Channel 0 Refresh triggered by Sync PRS. PRS Trigger should have the same clock group as VDAC.
3 : ASYNCPRS
Channel 0 Refresh triggered by Async PRS
End of enumeration elements list.
FIFODVL : Channel 0 FIFO Low Watermark
bits : 11 - 12 (2 bit)
access : read-write
HIGHCAPLOADEN : Channel 0 High Cap Load Mode Enable
bits : 14 - 14 (1 bit)
access : read-write
KEEPWARM : Channel 0 Keepwarm Mode Enable
bits : 16 - 16 (1 bit)
access : read-write
No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CONVMODE : Channel 1 Conversion Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CONTINUOUS
DAC channel 1 is set in continuous mode
1 : SAMPLEOFF
DAC channel 1 is set in sample/shut off mode
End of enumeration elements list.
POWERMODE : Channel 1 Power Mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : HIGHPOWER
Default is High Power Mode
1 : LOWPOWER
Set this bit for Low Power Mode
End of enumeration elements list.
TRIGMODE : Channel 1 Trigger Mode
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : NONE
No Conversion Trigger Source Selected for Channel 1
1 : SW
Channel 1 is triggered by Channel 1 FIFO (CH1F) write
2 : SYNCPRS
Channel 1 is triggered by Sync PRS input.PRS Trigger should have the same clock group as VDAC.
4 : INTERNALTIMER
Channel 1 is triggered by Internal Timer Overflow
5 : ASYNCPRS
Channel 1 is triggered by Async PRS input
End of enumeration elements list.
REFRESHSOURCE : Channel 1 Refresh Source
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : NONE
No Refresh Source Selected
1 : REFRESHTIMER
CH1 Refresh Triggered by Refresh Timer Overflow
2 : SYNCPRS
CH1 Refresh Triggered by Sync PRS. PRS Trigger should have the same clock group as VDAC.
3 : ASYNCPRS
CH1 Refresh Triggered by Async PRS
End of enumeration elements list.
FIFODVL : Channel 1 FIFO Low Watermark
bits : 11 - 12 (2 bit)
access : read-write
HIGHCAPLOADEN : Channel 1 High Cap Load Mode Enable
bits : 14 - 14 (1 bit)
access : read-write
KEEPWARM : Channel 1 Keepwarm Mode Enable
bits : 16 - 16 (1 bit)
access : read-write
No Description
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0EN : DAC Channel 0 Enable
bits : 0 - 0 (1 bit)
access : write-only
CH0DIS : DAC Channel 0 Disable
bits : 1 - 1 (1 bit)
access : write-only
CH1EN : DAC Channel 1 Enable
bits : 4 - 4 (1 bit)
access : write-only
CH1DIS : DAC Channel 1 Disable
bits : 5 - 5 (1 bit)
access : write-only
CH0FIFOFLUSH : CH0 WFIFO Flush
bits : 8 - 8 (1 bit)
access : write-only
CH1FIFOFLUSH : CH1 WFIFO Flush
bits : 9 - 9 (1 bit)
access : write-only
SINEMODESTART : Start Sine Wave Generation
bits : 10 - 10 (1 bit)
access : write-only
SINEMODESTOP : Stop Sine Wave Generation
bits : 11 - 11 (1 bit)
access : write-only
No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0CD : CH0 Conversion Done Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
CH1CD : CH1 Conversion Done Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write
CH0OF : CH0 Data Overflow Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write
CH1OF : CH1 Data Overflow Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write
CH0UF : CH0 Data Underflow Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-write
CH1UF : CH1 Data Underflow Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-write
ABUSALLOCERR : ABUS Port Allocation Error Flag
bits : 18 - 18 (1 bit)
access : read-write
CH0DVL : CH0 Data Valid Level Interrupt Flag
bits : 20 - 20 (1 bit)
access : read-write
CH1DVL : CH1 Data Valid Level Interrupt Flag
bits : 21 - 21 (1 bit)
access : read-write
ABUSINPUTCONFLICT : ABUS Input Conflict Error Flag
bits : 26 - 26 (1 bit)
access : read-write
No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0CD : CH0 Conversion Done Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
CH1CD : CH1 Conversion Done Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write
CH0OF : CH0 Data Overflow Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write
CH1OF : CH1 Data Overflow Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write
CH0UF : CH0 Data Underflow Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-write
CH1UF : CH1 Data Underflow Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-write
ABUSALLOCERR : ABUS Allocation Error Interrupt Flag
bits : 18 - 18 (1 bit)
access : read-write
CH0DVL : CH0 Data Valid Level Interrupt Flag
bits : 20 - 20 (1 bit)
access : read-write
CH1DVL : CH1 Data Valid Level Interrupt Flag
bits : 21 - 21 (1 bit)
access : read-write
ABUSINPUTCONFLICT : ABUS Input Conflict Interrupt Flag
bits : 26 - 26 (1 bit)
access : read-write
No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Channel 0 Data
bits : 0 - 11 (12 bit)
access : write-only
No Description
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Channel 1 Data
bits : 0 - 11 (12 bit)
access : write-only
No Description
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAINOUTENCH0 : CH0 Main Output Enable
bits : 0 - 0 (1 bit)
access : read-write
MAINOUTENCH1 : CH1 Main Output Enable
bits : 1 - 1 (1 bit)
access : read-write
AUXOUTENCH0 : CH0 Alternative Output Enable
bits : 4 - 4 (1 bit)
access : read-write
AUXOUTENCH1 : CH1 Alternative Output Enable
bits : 5 - 5 (1 bit)
access : read-write
SHORTCH0 : CH1 Main and Alternative Output Short
bits : 8 - 8 (1 bit)
access : read-write
SHORTCH1 : CH0 Main and Alternative Output Short
bits : 9 - 9 (1 bit)
access : read-write
ABUSPORTSELCH0 : CH0 ABUS Port Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : NONE
No GPIO Selected for CH0 ABUS Output
1 : PORTA
Port A Selected
2 : PORTB
Port B Selected
3 : PORTC
Port C Selected
4 : PORTD
Port D Selected
End of enumeration elements list.
ABUSPINSELCH0 : CH0 ABUS Pin Select
bits : 15 - 20 (6 bit)
access : read-write
ABUSPORTSELCH1 : CH1 ABUS Port Select
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
0 : NONE
No GPIO Selected for CH1 ABUS Output
1 : PORTA
Port A Selected
2 : PORTB
Port B Selected
3 : PORTC
Port C Selected
4 : PORTD
Port D Selected
End of enumeration elements list.
ABUSPINSELCH1 : CH1 ABUS Pin Select
bits : 25 - 30 (6 bit)
access : read-write
No Description
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0OUTHOLDTIME : CH0 Output Hold Time
bits : 0 - 9 (10 bit)
access : read-write
CH1OUTHOLDTIME : CH1 Output Hold Time
bits : 15 - 24 (10 bit)
access : read-write
No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : VDAC Module Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
1 : ENABLE
Enable
End of enumeration elements list.
DISABLING : Disablement busy status
bits : 1 - 1 (1 bit)
access : read-only
No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software reset command
bits : 0 - 0 (1 bit)
access : write-only
RESETTING : Software reset busy status
bits : 1 - 1 (1 bit)
access : read-only
No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIFF : Differential Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SINGLEENDED
Single ended output
1 : DIFFERENTIAL
Differential output
End of enumeration elements list.
SINEMODE : Sine Mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISSINEMODE
Sine mode disabled. Sine reset to 0 degrees
1 : ENSINEMODE
Sine mode enabled
End of enumeration elements list.
SINERESET : Sine Wave Reset When inactive
bits : 2 - 2 (1 bit)
access : read-write
CH0PRESCRST : Channel 0 Start Reset Prescaler
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NORESETPRESC
Prescaler not reset on channel 0 start
1 : RESETPRESC
Prescaler reset on channel 0 start
End of enumeration elements list.
REFRSEL : Reference Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : V125
Internal 1.25 V bandgap reference
1 : V25
Internal 2.5 V bandgap reference
2 : VDD
AVDD reference
3 : EXT
External pin reference
End of enumeration elements list.
PRESC : Prescaler Setting for DAC clock
bits : 7 - 13 (7 bit)
access : read-write
TIMEROVRFLOWPERIOD : Internal Timer Overflow Period
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : CYCLES2
The Timer overflows every 2 Prescaled CLK_DAC cycles
1 : CYCLES4
The Timer overflows every 4 Prescaled CLK_DAC cycles
2 : CYCLES8
The Timer overflows every 8 Prescaled CLK_DAC cycles
3 : CYCLES16
The Timer overflows every 16 Prescaled CLK_DAC cycles
4 : CYCLES32
The Timer overflows every 32 Prescaled CLK_DAC cycles
5 : CYCLES64
The Timer overflows every 64 Prescaled CLK_DAC cycles
End of enumeration elements list.
REFRESHPERIOD : Refresh Timer Overflow Period
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : CYCLES2
All channels with enabled refresh are refreshed every 2 CLK_REFRESH cycles
1 : CYCLES4
All channels with enabled refresh are refreshed every 4 CLK_REFRESH cycles
2 : CYCLES8
All channels with enabled refresh are refreshed every 8 CLK_REFRESH cycles
3 : CYCLES16
All channels with enabled refresh are refreshed every 16 CLK_REFRESH cycles
4 : CYCLES32
All channels with enabled refresh are refreshed every 32 CLK_REFRESH cycles
5 : CYCLES64
All channels with enabled refresh are refreshed every 64 CLK_REFRESH cycles
6 : CYCLES128
All channels with enabled refresh are refreshed every 128 CLK_REFRESH cycles
7 : CYCLES256
All channels with enabled refresh are refreshed every 256 CLK_REFRESH cycles
End of enumeration elements list.
BIASKEEPWARM : Bias Keepwarm Mode Enable
bits : 24 - 24 (1 bit)
access : read-write
DMAWU : VDAC DMA Wakeup
bits : 25 - 25 (1 bit)
access : read-write
ONDEMANDCLKDIS : Always allow clk_dac
bits : 26 - 26 (1 bit)
access : read-write
DBGHALT : Debug Halt
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Continue operation as normal during debug mode
1 : HALT
Complete the current conversion and then halt during debug mode
End of enumeration elements list.
WARMUPTIME : DAC Warmup Time
bits : 28 - 30 (3 bit)
access : read-write
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