\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
Network control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPBACKLOCAL : Loopback local
bits : 1 - 1 (1 bit)
access : read-write
ENBRX : Receive enable
bits : 2 - 2 (1 bit)
access : read-write
ENBTX : Transmit enable
bits : 3 - 3 (1 bit)
access : read-write
MANPORTEN : Management port enable
bits : 4 - 4 (1 bit)
access : read-write
CLRALLSTATSREGS : Clear statistics registers
bits : 5 - 5 (1 bit)
access : read-write
INCALLSTATSREGS : Incremental statistics registers
bits : 6 - 6 (1 bit)
access : read-write
STATSWREN : Write enable for statistics registers
bits : 7 - 7 (1 bit)
access : read-write
BACKPRESSURE : Back pressure will force collisions on all received frames
bits : 8 - 8 (1 bit)
access : read-write
TXSTRT : Start transmission
bits : 9 - 9 (1 bit)
access : read-write
TXHALT : Transmit halt
bits : 10 - 10 (1 bit)
access : read-write
TXPFRMREQ : Transmit pause frame
bits : 11 - 11 (1 bit)
access : read-write
TXPFRMZERO : Transmit zero quantum pause frame
bits : 12 - 12 (1 bit)
access : read-write
STORERXTS : Store receive time stamp to memory.
bits : 15 - 15 (1 bit)
access : read-write
PFCENB : Enable PFC Priority Based Pause Reception capabilities.
bits : 16 - 16 (1 bit)
access : read-write
TXPFCPRIORPFRM : Write a one to transmit PFC priority based pause frame.
bits : 17 - 17 (1 bit)
access : read-write
FLUSHRXPKT : Flush the next packet from the external RX DPRAM.
bits : 18 - 18 (1 bit)
access : read-write
TXLPIEN : Enable LPI transmission when set LPI (low power idle) is immediately transmitted.
bits : 19 - 19 (1 bit)
access : read-write
PTPUNICASTEN : Enable detection of unicast PTP unicast frames.
bits : 20 - 20 (1 bit)
access : read-write
STOREUDPOFFSET : Store UDP / TCP offset to memory.
bits : 22 - 22 (1 bit)
access : read-write
ONESTEPSYNCMODE : 1588 One Step Sync Mode.
bits : 24 - 24 (1 bit)
access : read-write
PFCCTRL : Enable multiple PFC pause quantums, one per pause priority
bits : 25 - 25 (1 bit)
access : read-write
DMA Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AMBABRSTLEN : Selects the burst length to use on the AMBA (AHB) when transferring frame data.
bits : 0 - 4 (5 bit)
access : read-write
HDRDATASPLITEN : Enable header data Splitting.
bits : 5 - 5 (1 bit)
access : read-write
RXPBUFSIZE : Receiver packet buffer memory size select.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x00000000 : SIZE0
Do not use top three address bits (0.5 Kb)
0x00000001 : SIZE1
Do not use top two address bits (1 Kb)
0x00000002 : SIZE2
Do not use top address bit (2 Kb)
0x00000003 : SIZE3
Use full configured addressable space (4 Kb)
End of enumeration elements list.
TXPBUFSIZE : Transmitter packet buffer memory size select.
bits : 10 - 10 (1 bit)
access : read-write
TXPBUFTCPEN : Transmitter IP, TCP and UDP checksum generation offload enable
bits : 11 - 11 (1 bit)
access : read-write
INFLASTDBUFSIZEEN : Forces the DMA
bits : 12 - 12 (1 bit)
access : read-write
RXBUFSIZE : DMA receive buffer size in external AMBA (AHB) system memory.
bits : 16 - 23 (8 bit)
access : read-write
FRCDISCARDONERR : Auto Discard RX pkts during lack of resource.
bits : 24 - 24 (1 bit)
access : read-write
FRCMAXAMBABRSTRX : Force max length bursts on RX.
bits : 25 - 25 (1 bit)
access : read-write
FRCMAXAMBABRSTTX : Force max length bursts on TX.
bits : 26 - 26 (1 bit)
access : read-write
RXBDEXTNDMODEEN : Enable RX extended BD mode.
bits : 28 - 28 (1 bit)
access : read-write
TXBDEXTENDMODEEN : Enable TX extended BD mode.
bits : 29 - 29 (1 bit)
access : read-write
Octets transmitted 31:0
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Transmitted octets in frame without errors [31:0]
bits : 0 - 31 (32 bit)
access : read-write
Octets Transmitted 47:32
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Transmitted octets in frame without errors [47:32]
bits : 0 - 15 (16 bit)
access : read-write
Frames Transmitted
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Frames transmitted without error
bits : 0 - 31 (32 bit)
access : read-write
Broadcast Frames Transmitted
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Broadcast frames transmitted without error
bits : 0 - 31 (32 bit)
access : read-write
Multicast Frames Transmitted
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Multicast frames transmitted without error
bits : 0 - 31 (32 bit)
access : read-write
Pause Frames Transmitted
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Transmitted pause frames
bits : 0 - 15 (16 bit)
access : read-write
64 Byte Frames Transmitted
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 64 byte frames transmitted without error
bits : 0 - 31 (32 bit)
access : read-write
65 to 127 Byte Frames Transmitted
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 65 to127 byte frames transmitted without error
bits : 0 - 31 (32 bit)
access : read-write
128 to 255 Byte Frames Transmitted
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 128 to 255 byte frames transmitted without error
bits : 0 - 31 (32 bit)
access : read-write
256 to 511 Byte Frames Transmitted
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 256 to 511 byte frames transmitted without error
bits : 0 - 31 (32 bit)
access : read-write
512 to 1023 Byte Frames Transmitted
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 512 to 1023 byte frames transmitted without error
bits : 0 - 31 (32 bit)
access : read-write
1024 to 1518 Byte Frames Transmitted
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 1024 to 1518 byte frames transmitted without error
bits : 0 - 31 (32 bit)
access : read-write
Greater Than 1518 Byte Frames Transmitted
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Greater than 1518 byte frames transmitted without error
bits : 0 - 31 (32 bit)
access : read-write
Transmit Under Runs
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Transmit under runs
bits : 0 - 9 (10 bit)
access : read-write
Single Collision Frames
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Single collision frames
bits : 0 - 17 (18 bit)
access : read-write
Multiple Collision Frames
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Multiple collision frames
bits : 0 - 17 (18 bit)
access : read-write
Transmit status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USEDBITREAD : Used bit read
bits : 0 - 0 (1 bit)
access : read-write
COLOCCRD : Collision occurred
bits : 1 - 1 (1 bit)
access : read-write
RETRYLMTEXCD : Retry limit exceeded
bits : 2 - 2 (1 bit)
access : read-write
TXGO : Transmit go
bits : 3 - 3 (1 bit)
access : read-only
AMBAERR : Transmit frame corruption due to AMBA (AHB) errors.
bits : 4 - 4 (1 bit)
access : read-write
TXCMPLT : Transmit complete
bits : 5 - 5 (1 bit)
access : read-write
TXUNDERRUN : Transmit under run
bits : 6 - 6 (1 bit)
access : read-write
LATECOLOCCRD : Late collision occurred
bits : 7 - 7 (1 bit)
access : read-write
RESPNOTOK : bresp/hresp not OK
bits : 8 - 8 (1 bit)
access : read-write
Excessive Collisions
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Excessive collisions
bits : 0 - 9 (10 bit)
access : read-write
Late Collisions
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Late collisions
bits : 0 - 9 (10 bit)
access : read-write
Deferred Transmission Frames
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Deferred transmission frames
bits : 0 - 17 (18 bit)
access : read-write
Carrier Sense Errors
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Carrier sense errors
bits : 0 - 9 (10 bit)
access : read-write
Octets Received 31:0
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Received octets in frame without errors
bits : 0 - 31 (32 bit)
access : read-write
Octets Received 47:32
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Received octets in frame without errors
bits : 0 - 15 (16 bit)
access : read-write
Frames Received
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Frames received without error
bits : 0 - 31 (32 bit)
access : read-write
Broadcast Frames Received
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Broadcast frames received without error
bits : 0 - 31 (32 bit)
access : read-write
Multicast Frames Received
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Multicast frames received without error
bits : 0 - 31 (32 bit)
access : read-write
Pause Frames Received
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Received pause frames
bits : 0 - 15 (16 bit)
access : read-write
64 Byte Frames Received
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 64 byte frames received without error
bits : 0 - 31 (32 bit)
access : read-write
65 to 127 Byte Frames Received
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 65 to 127 byte frames received without error
bits : 0 - 31 (32 bit)
access : read-write
128 to 255 Byte Frames Received
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 128 to 255 byte frames received without error
bits : 0 - 31 (32 bit)
access : read-write
256 to 511 Byte Frames Received
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 256 to 511 byte frames received without error
bits : 0 - 31 (32 bit)
access : read-write
512 to 1023 Byte Frames Received
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 512 to 1023 byte frames received without error
bits : 0 - 31 (32 bit)
access : read-write
1024 to 1518 Byte Frames Received
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 1024 to 1518 byte frames received without error
bits : 0 - 31 (32 bit)
access : read-write
Start address of the receive buffer queue
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMARXQPTR : Receive buffer queue base address
bits : 2 - 31 (30 bit)
access : read-write
1519 to maximum Byte Frames Received
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 1519 to maximum byte frames received without error
bits : 0 - 31 (32 bit)
access : read-write
Undersized Frames Received
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Undersize frames received
bits : 0 - 9 (10 bit)
access : read-write
Oversize Frames Received
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Oversize frames received
bits : 0 - 9 (10 bit)
access : read-write
Jabbers Received
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Jabbers received
bits : 0 - 9 (10 bit)
access : read-write
Frame Check Sequence Errors
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Frame check sequence errors
bits : 0 - 9 (10 bit)
access : read-write
Length Field Frame Errors
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Length field frame errors
bits : 0 - 9 (10 bit)
access : read-write
Receive Symbol Errors
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Receive symbol errors
bits : 0 - 9 (10 bit)
access : read-write
Alignment Errors
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Alignment errors
bits : 0 - 9 (10 bit)
access : read-write
Receive Resource Errors
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Receive resource errors
bits : 0 - 17 (18 bit)
access : read-write
Receive Overruns
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Receive overruns
bits : 0 - 9 (10 bit)
access : read-write
IP Header Checksum Errors
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : IP header checksum errors
bits : 0 - 7 (8 bit)
access : read-write
TCP Checksum Errors
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : TCP checksum errors
bits : 0 - 7 (8 bit)
access : read-write
UDP Checksum Errors
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : UDP checksum errors
bits : 0 - 7 (8 bit)
access : read-write
Receive DMA Flushed Packets
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Flushed RX pkts counter
bits : 0 - 15 (16 bit)
access : read-write
1588 Timer Increment Register subscript nsec
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBNSINCR : MSB [23:8] of the subscript-ns value
bits : 0 - 15 (16 bit)
access : read-write
SUBNSINCRLSB : LSB [7:0] of the subscript-ns value
bits : 24 - 31 (8 bit)
access : read-write
Start address of the transmit buffer queue
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMATXQPTR : Transmit buffer queue base address
bits : 2 - 31 (30 bit)
access : read-write
1588 Timer Seconds Register 47:32
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER : MSB 16 bits of seconds timer count.
bits : 0 - 15 (16 bit)
access : read-write
1588 Timer Seconds Register 31:0
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER : 1588 Timer Seconds Register
bits : 0 - 31 (32 bit)
access : read-write
1588 Timer Nanoseconds Register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER : Timer count in nanoseconds
bits : 0 - 29 (30 bit)
access : read-write
This register returns all zeroes when read.
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENTVAL : Timer increment value
bits : 0 - 29 (30 bit)
access : read-write
ADDSUBTRACT : Write as one to subtract from the 1588 timer
bits : 31 - 31 (1 bit)
access : read-write
1588 Timer Increment Register
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSINCREMENT : A count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle
bits : 0 - 7 (8 bit)
access : read-write
ALTNSINCR : Alternative nanoseconds count
bits : 8 - 15 (8 bit)
access : read-write
NUMINCS : Number of incs before alt inc
bits : 16 - 23 (8 bit)
access : read-write
PTP Event Frame Transmitted Seconds Register 31:0
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMER : PTP Event Frame Transmitted Seconds
bits : 0 - 31 (32 bit)
access : read-only
PTP Event Frame Transmitted Nanoseconds Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMER : PTP Event Frame Transmitted Nanoseconds
bits : 0 - 29 (30 bit)
access : read-only
PTP Event Frame Received Seconds Register 31:0
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMER : PTP Event Frame Received Seconds
bits : 0 - 31 (32 bit)
access : read-only
PTP Event Frame Received Nanoseconds Register
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMER : PTP Event Frame Received Nanoseconds
bits : 0 - 29 (30 bit)
access : read-only
PTP Peer Event Frame Transmitted Seconds Register 31:0
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMER : PTP Peer Event Frame Received Seconds
bits : 0 - 31 (32 bit)
access : read-only
PTP Peer Event Frame Transmitted Nanoseconds Register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMER : PTP Peer Event Frame Transmitted Nanoseconds
bits : 0 - 29 (30 bit)
access : read-only
PTP Peer Event Frame Received Seconds Register 31:0
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMER : PTP Peer Event Frame Received Seconds
bits : 0 - 31 (32 bit)
access : read-only
PTP Peer Event Frame Received Nanoseconds Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMER : PTP Peer Event Frame Received Nanoseconds
bits : 0 - 29 (30 bit)
access : read-only
Receive status register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFFNOTAVAIL : Buffer not available
bits : 0 - 0 (1 bit)
access : read-write
FRMRX : Frame received
bits : 1 - 1 (1 bit)
access : read-write
RXOVERRUN : Receive overrun
bits : 2 - 2 (1 bit)
access : read-write
RESPNOTOK : bresp/hresp not OK
bits : 3 - 3 (1 bit)
access : read-write
Interrupt status register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MNGMNTDONE : Management frame sent
bits : 0 - 0 (1 bit)
access : read-write
RXCMPLT : Receive complete
bits : 1 - 1 (1 bit)
access : read-write
RXUSEDBITREAD : RX used bit read
bits : 2 - 2 (1 bit)
access : read-write
TXUSEDBITREAD : TX used bit read
bits : 3 - 3 (1 bit)
access : read-write
TXUNDERRUN : Transmit under run
bits : 4 - 4 (1 bit)
access : read-write
RTRYLMTORLATECOL : Retry limit exceeded or late collision
bits : 5 - 5 (1 bit)
access : read-write
AMBAERR : Transmit frame corruption due to AMBA (AHB) error.
bits : 6 - 6 (1 bit)
access : read-write
TXCMPLT : Transmit complete
bits : 7 - 7 (1 bit)
access : read-write
RXOVERRUN : Receive overrun
bits : 10 - 10 (1 bit)
access : read-write
RESPNOTOK : Hresp not OK
bits : 11 - 11 (1 bit)
access : read-write
NONZEROPFRMQUANT : Pause frame with non-zero pause quantum received
bits : 12 - 12 (1 bit)
access : read-write
PAUSETIMEZERO : Pause Time zero
bits : 13 - 13 (1 bit)
access : read-write
PFRMTX : Pause frame transmitted
bits : 14 - 14 (1 bit)
access : read-write
PTPDLYREQFRMRX : PTP delay_req frame received
bits : 18 - 18 (1 bit)
access : read-write
PTPSYNCFRMRX : PTP sync frame received
bits : 19 - 19 (1 bit)
access : read-write
PTPDLYREQFRMTX : PTP delay_req frame transmitted
bits : 20 - 20 (1 bit)
access : read-write
PTPSYNCFRMTX : PTP sync frame transmitted
bits : 21 - 21 (1 bit)
access : read-write
PTPPDLYREQFRMRX : PTP pdelay_req frame received
bits : 22 - 22 (1 bit)
access : read-write
PTPPDLYRESPFRMRX : PTP pdelay_resp frame received
bits : 23 - 23 (1 bit)
access : read-write
PTPPDLYREQFRMTX : PTP pdelay_req frame transmitted
bits : 24 - 24 (1 bit)
access : read-write
PTPPDLYRESPFRMTX : PTP pdelay_resp frame transmitted
bits : 25 - 25 (1 bit)
access : read-write
TSUSECREGINCR : TSU seconds register increment
bits : 26 - 26 (1 bit)
access : read-write
RXLPIINDC : Receive LPI indication status bit change
bits : 27 - 27 (1 bit)
access : read-write
WOLEVNTRX : WOL event received interrupt.
bits : 28 - 28 (1 bit)
access : read-write
TSUTIMERCOMP : TSU timer comparison interrupt.
bits : 29 - 29 (1 bit)
access : read-write
Transmit Pause Quantum Register 1
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QUANTP2 : Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 2.
bits : 0 - 15 (16 bit)
access : read-write
QUANTP3 : Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 3.
bits : 16 - 31 (16 bit)
access : read-write
Transmit Pause Quantum Register 2
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QUANTP4 : Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 4.
bits : 0 - 15 (16 bit)
access : read-write
QUANTP5 : Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 5.
bits : 16 - 31 (16 bit)
access : read-write
Transmit Pause Quantum Register 3
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QUANTP6 : Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 6.
bits : 0 - 15 (16 bit)
access : read-write
QUANTP7 : Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 7.
bits : 16 - 31 (16 bit)
access : read-write
Received LPI transitions
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Count of RX LPI transitions
bits : 0 - 15 (16 bit)
access : read-write
Received LPI time
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPITIME : Time in LPI
bits : 0 - 23 (24 bit)
access : read-write
Transmit LPI transitions
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Count of LPI transmitions
bits : 0 - 15 (16 bit)
access : read-write
Transmit LPI time
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPITIME : Time in LPI
bits : 0 - 23 (24 bit)
access : read-write
Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MNGMNTDONE : Enable management done interrupt
bits : 0 - 0 (1 bit)
access : write-only
RXCMPLT : Enable receive complete interrupt
bits : 1 - 1 (1 bit)
access : write-only
RXUSEDBITREAD : Enable receive used bit read interrupt
bits : 2 - 2 (1 bit)
access : write-only
TXUSEDBITREAD : Enable transmit used bit read interrupt
bits : 3 - 3 (1 bit)
access : write-only
TXUNDERRUN : Enable transmit buffer under run interrupt
bits : 4 - 4 (1 bit)
access : write-only
RTRYLMTORLATECOL : Enable retry limit exceeded or late collision interrupt
bits : 5 - 5 (1 bit)
access : write-only
AMBAERR : Enable transmit frame corruption due to AMBA (AHB) error interrupt
bits : 6 - 6 (1 bit)
access : write-only
TXCMPLT : Enable transmit complete interrupt
bits : 7 - 7 (1 bit)
access : write-only
RXOVERRUN : Enable receive overrun interrupt
bits : 10 - 10 (1 bit)
access : write-only
RESPNOTOK : Enable bresp/hresp not OK interrupt
bits : 11 - 11 (1 bit)
access : write-only
NONZEROPFRMQUANT : Enable pause frame with non-zero pause quantum interrupt
bits : 12 - 12 (1 bit)
access : write-only
PAUSETIMEZERO : Enable pause time zero interrupt
bits : 13 - 13 (1 bit)
access : write-only
PFRMTX : Enable pause frame transmitted interrupt
bits : 14 - 14 (1 bit)
access : write-only
PTPDLYREQFRMRX : Enable PTP delay_req frame received interrupt
bits : 18 - 18 (1 bit)
access : write-only
PTPSYNCFRMRX : Enable PTP sync frame received interrupt
bits : 19 - 19 (1 bit)
access : write-only
PTPDLYREQFRMTX : Enable PTP delay_req frame transmitted interrupt
bits : 20 - 20 (1 bit)
access : write-only
PTPSYNCFRMTX : Enable PTP sync frame transmitted interrupt
bits : 21 - 21 (1 bit)
access : write-only
PTPPDLYREQFRMRX : Enable PTP pdelay_req frame received interrupt
bits : 22 - 22 (1 bit)
access : write-only
PTPPDLYRESPFRMRX : Enable PTP pdelay_resp frame received interrupt
bits : 23 - 23 (1 bit)
access : write-only
PTPPDLYREQFRMTX : Enable PTP pdelay_req frame transmitted interrupt
bits : 24 - 24 (1 bit)
access : write-only
PTPPDLYRESPFRMTX : Enable PTP pdelay_resp frame transmitted interrupt
bits : 25 - 25 (1 bit)
access : write-only
TSUSECREGINCR : Enable TSU seconds register increment interrupt
bits : 26 - 26 (1 bit)
access : write-only
RXLPIINDC : Enable RX LPI indication interrupt
bits : 27 - 27 (1 bit)
access : write-only
WOLEVNTRX : Enable WOL event received interrupt
bits : 28 - 28 (1 bit)
access : write-only
TSUTIMERCOMP : Enable TSU timer comparison interrupt.
bits : 29 - 29 (1 bit)
access : write-only
Interrupt Disable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MNGMNTDONE : Disable management done interrupt
bits : 0 - 0 (1 bit)
access : write-only
RXCMPLT : Disable receive complete interrupt
bits : 1 - 1 (1 bit)
access : write-only
RXUSEDBITREAD : Disable receive used bit read interrupt
bits : 2 - 2 (1 bit)
access : write-only
TXUSEDBITREAD : Disable transmit used bit read interrupt
bits : 3 - 3 (1 bit)
access : write-only
TXUNDERRUN : Disable transmit buffer under run interrupt
bits : 4 - 4 (1 bit)
access : write-only
RTRYLMTORLATECOL : Disable retry limit exceeded or late collision interrupt
bits : 5 - 5 (1 bit)
access : write-only
AMBAERR : Disable transmit frame corruption due to AMBA (AHB) error interrupt
bits : 6 - 6 (1 bit)
access : write-only
TXCMPLT : Disable transmit complete interrupt
bits : 7 - 7 (1 bit)
access : write-only
RXOVERRUN : Disable receive overrun interrupt
bits : 10 - 10 (1 bit)
access : write-only
RESPNOTOK : Disable bresp/hresp not OK interrupt
bits : 11 - 11 (1 bit)
access : write-only
NONZEROPFRMQUANT : Disable pause frame with non-zero pause quantum interrupt
bits : 12 - 12 (1 bit)
access : write-only
PAUSETIMEZERO : Disable pause time zero interrupt
bits : 13 - 13 (1 bit)
access : write-only
PFRMTX : Disable pause frame transmitted interrupt
bits : 14 - 14 (1 bit)
access : write-only
PTPDLYREQFRMRX : Disable PTP delay_req frame received interrupt
bits : 18 - 18 (1 bit)
access : write-only
PTPSYNCFRMRX : Disable PTP sync frame received interrupt
bits : 19 - 19 (1 bit)
access : write-only
PTPDLYREQFRMTX : Disable PTP delay_req frame transmitted interrupt
bits : 20 - 20 (1 bit)
access : write-only
PTPSYNCFRMTX : Disable PTP sync frame transmitted interrupt
bits : 21 - 21 (1 bit)
access : write-only
PTPPDLYREQFRMRX : Disable PTP pdelay_req frame received interrupt
bits : 22 - 22 (1 bit)
access : write-only
PTPPDLYRESPFRMRX : Disable PTP pdelay_resp frame received interrupt
bits : 23 - 23 (1 bit)
access : write-only
PTPPDLYREQFRMTX : Disable PTP pdelay_req frame transmitted interrupt
bits : 24 - 24 (1 bit)
access : write-only
PTPPDLYRESPFRMTX : Disable PTP pdelay_resp frame transmitted interrupt
bits : 25 - 25 (1 bit)
access : write-only
TSUSECREGINCR : Disable TSU seconds register increment interrupt
bits : 26 - 26 (1 bit)
access : write-only
RXLPIINDC : Disable RX LPI indication interrupt
bits : 27 - 27 (1 bit)
access : write-only
WOLEVNTRX : Disable WOL event received interrupt
bits : 28 - 28 (1 bit)
access : write-only
TSUTIMERCOMP : Disable TSU timer comparison interrupt.
bits : 29 - 29 (1 bit)
access : write-only
Interrupt mask register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MNGMNTDONE : management done interrupt mask
bits : 0 - 0 (1 bit)
access : read-write
RXCMPLT : receive complete interrupt mask
bits : 1 - 1 (1 bit)
access : read-write
RXUSEDBITREAD : receive used bit read interrupt mask
bits : 2 - 2 (1 bit)
access : read-write
TXUSEDBITREAD : transmit used bit read interrupt mask
bits : 3 - 3 (1 bit)
access : read-write
TXUNDERRUN : transmit buffer under run interrupt mask
bits : 4 - 4 (1 bit)
access : read-write
RTRYLMTORLATECOL : Retry limit exceeded or late collision (gigabit mode only) interrupt mask
bits : 5 - 5 (1 bit)
access : read-write
AMBAERR : Transmit frame corruption due to AMBA (AHB) error interrupt mask
bits : 6 - 6 (1 bit)
access : read-write
TXCMPLT : Transmit complete interrupt mask
bits : 7 - 7 (1 bit)
access : read-write
UNUSED : Unused
bits : 8 - 8 (1 bit)
access : read-write
RXOVERRUN : Receive overrun interrupt mask
bits : 10 - 10 (1 bit)
access : read-write
RESPNOTOK : bresp/hresp not OK interrupt mask
bits : 11 - 11 (1 bit)
access : read-write
NONZEROPFRMQUANT : Pause frame with non-zero pause quantum interrupt mask
bits : 12 - 12 (1 bit)
access : read-write
PAUSETIMEZERO : pause time zero interrupt mask
bits : 13 - 13 (1 bit)
access : read-write
PFRMTX : pause frame transmitted interrupt mask
bits : 14 - 14 (1 bit)
access : read-write
PTPDLYREQFRMRX : PTP delay_req frame received mask
bits : 18 - 18 (1 bit)
access : read-write
PTPSYNCFRMRX : PTP sync frame received mask
bits : 19 - 19 (1 bit)
access : read-write
PTPDLYREQFRMTX : PTP delay_req frame transmitted mask
bits : 20 - 20 (1 bit)
access : read-write
PTPSYNCFRMTX : PTP sync frame transmitted mask
bits : 21 - 21 (1 bit)
access : read-write
PTPPDLYREQFRMRX : PTP pdelay_req frame received mask
bits : 22 - 22 (1 bit)
access : read-write
PTPPDLYRESPFRMRX : PTP pdelay_resp frame received mask
bits : 23 - 23 (1 bit)
access : read-write
PTPPDLYREQFRMTX : PTP pdelay_req frame transmitted mask
bits : 24 - 24 (1 bit)
access : read-write
PTPPDLYRESPFRMTX : PTP pdelay_resp frame transmitted mask
bits : 25 - 25 (1 bit)
access : read-write
TSUSECREGINCR : TSU seconds register increment mask
bits : 26 - 26 (1 bit)
access : read-write
RXLPIINDC : RX LPI indication mask
bits : 27 - 27 (1 bit)
access : read-write
WOLEVNTRX : WOL event received mask
bits : 28 - 28 (1 bit)
access : read-write
TSUTIMERCOMP : TSU timer comparison interrupt mask.
bits : 29 - 29 (1 bit)
access : read-write
PHY management register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHYRWDATA : PHY read write data
bits : 0 - 15 (16 bit)
access : read-write
WRITE10 : Must be written with 10.
bits : 16 - 17 (2 bit)
access : read-write
REGADDR : Register address - specifies the register in the PHY to access.
bits : 18 - 22 (5 bit)
access : read-write
PHYADDR : PHY address.
bits : 23 - 27 (5 bit)
access : read-write
OPERATION : Operation. For a Clause 45 frame: 00 is an addr, 01 is a write, 10 is a post read increment, 11 is a read frame. For a Clause 22 frame: 10 is a read, 01 is a write.
bits : 28 - 29 (2 bit)
access : read-write
WRITE1 : Must be written to 1 for a valid Clause 22 frame and to 0 for a valid Clause 45 frame.
bits : 30 - 30 (1 bit)
access : read-write
WRITE0 : Must be written with 0.
bits : 31 - 31 (1 bit)
access : read-write
Received Pause Quantum Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
QUANT : Received pause quantum
bits : 0 - 15 (16 bit)
access : read-only
Transmit Pause Quantum Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QUANT : Transmit pause quantum
bits : 0 - 15 (16 bit)
access : read-write
QUANTP1 : Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 1.
bits : 16 - 31 (16 bit)
access : read-write
Network configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPEED : Speed
bits : 0 - 0 (1 bit)
access : read-write
FULLDUPLEX : Full duplex
bits : 1 - 1 (1 bit)
access : read-write
DISCRDNONVLANFRAMES : Discard non-VLAN frames
bits : 2 - 2 (1 bit)
access : read-write
JUMBOFRAMES : Jumbo frames enable
bits : 3 - 3 (1 bit)
access : read-write
COPYALLFRAMES : Copy all frames
bits : 4 - 4 (1 bit)
access : read-write
NOBROADCAST : No broadcast
bits : 5 - 5 (1 bit)
access : read-write
MULTICASTHASHEN : Multicast hash enable
bits : 6 - 6 (1 bit)
access : read-write
UNICASTHASHEN : Unicast hash enable
bits : 7 - 7 (1 bit)
access : read-write
RX1536BYTEFRAMES : Receive 1536 byte frames
bits : 8 - 8 (1 bit)
access : read-write
RETRYTEST : Retry test
bits : 12 - 12 (1 bit)
access : read-write
PAUSEEN : Pause enable
bits : 13 - 13 (1 bit)
access : read-write
RXBUFFOFFSET : Receive buffer offset
bits : 14 - 15 (2 bit)
access : read-write
LENFIELDERRFRMDISCRD : Length field error frame discard
bits : 16 - 16 (1 bit)
access : read-write
FCSREMOVE : FCS remove
bits : 17 - 17 (1 bit)
access : read-write
MDCCLKDIV : MDC clock division
bits : 18 - 20 (3 bit)
access : read-write
Enumeration:
0x00000000 : DIVBY8
divide HFBUSCLKETH by 8 (HFBUSCLKETH up to 20 MHz)
0x00000001 : DIVBY16
divide HFBUSCLKETH by 16 (HFBUSCLKETH up to 40 MHz)
0x00000002 : DIVBY32
divide HFBUSCLKETH by 32 (HFBUSCLKETH up to 80 MHz)
0x00000003 : DIVBY48
divide HFBUSCLKETH by 48 (HFBUSCLKETH up to 120 MHz)
0x00000004 : DIVBY64
divide HFBUSCLKETH by 64 (HFBUSCLKETH up to 160 MHz)
0x00000005 : DIVBY96
divide HFBUSCLKETH by 96 (HFBUSCLKETH up to 240 MHz)
0x00000006 : DIVBY128
divide HFBUSCLKETH by 128 (HFBUSCLKETH up to 320 MHz)
0x00000007 : DIVBY224
divide HFBUSCLKETH by 224 (HFBUSCLKETH up to 540 MHz)
End of enumeration elements list.
DISCOPYOFPFRAMES : Disable copy of pause frames
bits : 23 - 23 (1 bit)
access : read-write
RXCHKSUMOFFLOADEN : Receive checksum offload enable
bits : 24 - 24 (1 bit)
access : read-write
ENHALFDUPLEXRX : Enable frames to be received in half-duplex mode while transmitting.
bits : 25 - 25 (1 bit)
access : read-write
IGNORERXFCS : Ignore RX FCS
bits : 26 - 26 (1 bit)
access : read-write
IPGSTRTCHEN : IPG stretch enable
bits : 28 - 28 (1 bit)
access : read-write
NSPCHANGE : Receive bad preamble.
bits : 29 - 29 (1 bit)
access : read-write
IGNOREIPGRXER : Ignore IPG rx_er.
bits : 30 - 30 (1 bit)
access : read-write
TX Partial Store and Forward
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMATXCUTTHRUTHR : Watermark value
bits : 0 - 9 (10 bit)
access : read-write
DMATXCUTTHRU : Enable TX partial store and forward operation
bits : 31 - 31 (1 bit)
access : read-write
RX Partial Store and Forward
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMARXCUTTHRUTHR : Watermark value
bits : 0 - 9 (10 bit)
access : read-write
DMARXCUTTHRU : Enable RX partial store and forward operation
bits : 31 - 31 (1 bit)
access : read-write
Maximum Jumbo Frame Size.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JUMBOMAXLEN : Maximum Jumbo Frame Size - resets to the gem_jumbo_max_length define value.
bits : 0 - 13 (14 bit)
access : read-write
TX BD control register
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXBDTSMODE : TX Descriptor Timestamp Insertion mode, 00: TS insertion disable, 01: TS inserted for PTP Event Frames only, 10: TS inserted for All PTP Frames only, 11: TS insertion for All Frames
bits : 4 - 5 (2 bit)
access : read-write
RX BD control register
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXBDTSMODE : RX Descriptor Timestamp Insertion mode, 00: TS insertion disable, 01: TS inserted for PTP Event Frames only, 10: TS inserted for All PTP Frames only, 11: TS insertion for All Frames
bits : 4 - 5 (2 bit)
access : read-write
Interrupt moderation register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXINTMOD : Count of 800ns periods before bit 1 is set in the interrupt status register after a frame is received
bits : 0 - 7 (8 bit)
access : read-write
TXINTMOD : Count of 800ns periods before bit 7 is set in the interrupt status register after a frame is transmitted
bits : 16 - 23 (8 bit)
access : read-write
System wake time
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSWAKETIME : Count of 64ns, 320ns or 3200ns intervals before transmission starts after deassertion of tx_lpi_en
bits : 0 - 15 (16 bit)
access : read-write
Network status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MDIOIN : Returns status of the mdio_in pin.
bits : 1 - 1 (1 bit)
access : read-only
MANDONE : The PHY management logic is idle (i.e. has completed).
bits : 2 - 2 (1 bit)
access : read-only
PFCNEGOTIATE : Set when PFC Priority Based Pause has been negotiated.
bits : 6 - 6 (1 bit)
access : read-only
LPIINDICATE : LPI Indication
bits : 7 - 7 (1 bit)
access : read-only
Hash Register Bottom [31:0]
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : The first 32 bits of the hash address register.
bits : 0 - 31 (32 bit)
access : read-write
Hash Register Top [63:32]
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : The remaining 32 bits of the hash address register.
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 1 Bottom
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Least significant 32 bits of the destination address
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 1 Top
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific address 1 MSB
bits : 0 - 15 (16 bit)
access : read-write
FILTERTYPE : MAC SA or DA selection
bits : 16 - 16 (1 bit)
access : read-write
Specific Address 2 Bottom
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Least significant 32 bits of the destination address
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 2 Top
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific address 2 MSB
bits : 0 - 15 (16 bit)
access : read-write
FILTERTYPE : MAC SA or DA selection
bits : 16 - 16 (1 bit)
access : read-write
FILTERBYTEMASK : Filter byte Mask
bits : 24 - 29 (6 bit)
access : read-write
Specific Address 3 Bottom
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Least significant 32 bits of the destination address
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 3 Top
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific address 3 MSB
bits : 0 - 15 (16 bit)
access : read-write
FILTERTYPE : MAC SA or DA selection
bits : 16 - 16 (1 bit)
access : read-write
FILTERBYTEMASK : Filter byte Mask
bits : 24 - 29 (6 bit)
access : read-write
Specific Address 4 Bottom
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Least significant 32 bits of the destination address
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 4 Top
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific address 4 MSB
bits : 0 - 15 (16 bit)
access : read-write
FILTERTYPE : MAC SA or DA selection
bits : 16 - 16 (1 bit)
access : read-write
FILTERBYTEMASK : Filter byte Mask
bits : 24 - 29 (6 bit)
access : read-write
Type ID Match 1
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Type ID match 1
bits : 0 - 15 (16 bit)
access : read-write
ENBCOPY : Enable copying of type ID match 1 matched frames.
bits : 31 - 31 (1 bit)
access : read-write
Type ID Match 2
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Type ID match 2
bits : 0 - 15 (16 bit)
access : read-write
ENBCOPY : Enable copying of type ID match 2 matched frames.
bits : 31 - 31 (1 bit)
access : read-write
Type ID Match 3
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Type ID match 3
bits : 0 - 15 (16 bit)
access : read-write
ENBCOPY : Enable copying of type ID match 3 matched frames.
bits : 31 - 31 (1 bit)
access : read-write
Type ID Match 4
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Type ID match 4
bits : 0 - 15 (16 bit)
access : read-write
ENBCOPY : Enable copying of type ID match 4 matched frames.
bits : 31 - 31 (1 bit)
access : read-write
Wake on LAN Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Wake on LAN ARP request IP address. Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake on LAN event. A value of zero will not generate an event, even if this is matched by the received frame.
bits : 0 - 15 (16 bit)
access : read-write
WOLMASK0 : Wake on LAN magic packet event enable
bits : 16 - 16 (1 bit)
access : read-write
WOLMASK1 : Wake on LAN ARP request event enable
bits : 17 - 17 (1 bit)
access : read-write
WOLMASK2 : Wake on LAN specific address register 1 event enable
bits : 18 - 18 (1 bit)
access : read-write
WOLMASK3 : Wake on LAN multicast hash event enable
bits : 19 - 19 (1 bit)
access : read-write
IPG stretch register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPGSTRETCH : IPG Stretch
bits : 0 - 15 (16 bit)
access : read-write
Stacked VLAN Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : User defined VLAN_TYPE field
bits : 0 - 15 (16 bit)
access : read-write
ENBPROCESSING : Enable stacked VLAN processing mode
bits : 31 - 31 (1 bit)
access : read-write
I/O Route Enable Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDIOPEN : MDIO I/O Enable
bits : 0 - 0 (1 bit)
access : read-write
MIITXERPEN : MII TX ER I/O Enable
bits : 1 - 1 (1 bit)
access : read-write
MIIRXERPEN : MII TX ER I/O Enable
bits : 2 - 2 (1 bit)
access : read-write
MIIPEN : MII I/O Enable
bits : 3 - 3 (1 bit)
access : read-write
RMIIPEN : RMII I/O Enable
bits : 4 - 4 (1 bit)
access : read-write
TSUTMRTOGPEN : TSU_TMR_CNT_SEC Output Enable
bits : 5 - 5 (1 bit)
access : read-write
I/O Route Location Register 0
address_offset : 0xC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MIITXLOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
End of enumeration elements list.
MIIRXLOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
End of enumeration elements list.
MIICRSLOC : I/O Location
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
End of enumeration elements list.
MIICOLLOC : I/O Location
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
End of enumeration elements list.
I/O Route Location Register 1
address_offset : 0xC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSUEXTCLKLOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
End of enumeration elements list.
TSUTMRTOGLOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
End of enumeration elements list.
MDIOLOC : I/O Location
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
End of enumeration elements list.
RMIILOC : I/O Location
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
End of enumeration elements list.
Ethernet control register
address_offset : 0xC10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSUCLKSEL : TSU Clock selection value
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x00000000 : NOCLOCK
No TSU clock source selected
0x00000001 : PLL
Select system clock as TSU Clock
0x00000002 : RXCLK
Select ethernet RX Clock as TSU Clock
0x00000003 : REFCLK
Select ref clock as TSU Clock
0x00000004 : TSUEXTCLK
Select tsu external pin as TSU Clock
End of enumeration elements list.
TSUPRESC : Clock division factor of TSUPRESC+1
bits : 4 - 7 (4 bit)
access : read-write
MIISEL : MII select signal
bits : 8 - 8 (1 bit)
access : read-write
GBLCLKEN : Global Clock Enable signal for Ethernet clocks tsu_clk, tx_clk, rx_clk and ref_clk
bits : 9 - 9 (1 bit)
access : read-write
TXREFCLKSEL : REFCLK source select for RMII_TXD and RMII_TX_EN
bits : 10 - 10 (1 bit)
access : read-write
Transmit PFC Pause Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTORENB : Priority Vector Enable. If bit 17 of the network control register is written with a one then the priority enable vector of the PFC priority based pause frame will be set equal to the value stored in this register [7:0].
bits : 0 - 7 (8 bit)
access : read-write
VECTOR : Priority Vector Pause Size. If bit 17 of the network control register is written with a one then for each entry equal to zero in the Transmit PFC Pause Register[15:8], the PFC pause frame's pause quantum field associated with that entry will be taken from the transmit pause quantum register. For each entry equal to one in the Transmit PFC Pause Register [15:8], the pause quantum associated with that entry will be zero.
bits : 8 - 15 (8 bit)
access : read-write
Specific Address Mask 1 Bottom 31:0
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRMASK : Specific Address Mask
bits : 0 - 31 (32 bit)
access : read-write
Specific Address Mask 1 Top 47:32
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRMASK : Specific Address Mask
bits : 0 - 15 (16 bit)
access : read-write
PTP RX unicast IP destination address
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Unicast IP destination address
bits : 0 - 31 (32 bit)
access : read-write
PTP TX unicast IP destination address
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Unicast IP destination address
bits : 0 - 31 (32 bit)
access : read-write
TSU timer comparison value nanoseconds
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPVAL : TSU timer comparison value (ns)
bits : 0 - 21 (22 bit)
access : read-write
TSU timer comparison value seconds [31:0]
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPVAL : TSU timer comparison value (s)
bits : 0 - 31 (32 bit)
access : read-write
TSU timer comparison value seconds [47:32]
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPVAL : TSU timer comparison value (s)
bits : 0 - 15 (16 bit)
access : read-write
PTP Event Frame Transmitted Seconds Register 47:32
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMERSEC : PTP Event Frame TX Seconds
bits : 0 - 15 (16 bit)
access : read-only
PTP Event Frame Received Seconds Register 47:32
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMERSEC : PTP Event Frame TX Seconds
bits : 0 - 15 (16 bit)
access : read-only
PTP Peer Event Frame Transmitted Seconds Register 47:32
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMERSEC : PTP Peer Event Frame TX Seconds
bits : 0 - 15 (16 bit)
access : read-only
PTP Peer Event Frame Received Seconds Register 47:32
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMERSEC : PTP Peer Event Frame RX Seconds
bits : 0 - 15 (16 bit)
access : read-only
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