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ICU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x120 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x130 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x140 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1A0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1C0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x200 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x300 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IRQCR0

IRQCR1

NMICR

NMIER

NMICLR

NMISR

WUPEN

IELEN

IRQCR2

SELSR0

IRQCR3

IELSR0

IELSR1

IELSR2

IELSR3

IELSR4

IELSR5

IELSR6

IELSR7

IELSR8

IELSR9

IELSR10

IELSR11

IELSR12

IELSR13

IELSR14

IELSR15

IELSR16

IELSR17

IELSR18

IELSR19

IELSR20

IELSR21

IELSR22

IELSR23

IELSR24

IELSR25

IELSR26

IELSR27

IELSR28

IELSR29

IELSR30

IELSR31

IRQCR4

IRQCR5

IRQCR6

IRQCR7


IRQCR0

IRQ Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR0 IRQCR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IRQCR1

IRQ Control Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR1 IRQCR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


NMICR

NMI Pin Interrupt Control Register
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMICR NMICR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NMIMD NFCLKSEL NFLTEN

NMIMD : NMI Detection Set
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Falling edge

#1 : 1

Rising edge

End of enumeration elements list.

NFCLKSEL : NMI Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

NFLTEN : NMI Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.


NMIER

Non-Maskable Interrupt Enable Register
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMIER NMIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IWDTEN WDTEN LVD1EN LVD2EN OSTEN NMIEN RPEEN BUSSEN BUSMEN SPEEN

IWDTEN : IWDT Underflow/Refresh Error Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled.

End of enumeration elements list.

WDTEN : WDT Underflow/Refresh Error Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

LVD1EN : Voltage monitor 1 Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

LVD2EN : Voltage monitor 2 Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

OSTEN : Oscillation Stop Detection Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

NMIEN : NMI Pin Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RPEEN : SRAM Parity Error Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

BUSSEN : MPU Bus Slave Error Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

BUSMEN : MPU Bus Master Error Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

SPEEN : CPU Stack Pointer Monitor Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.


NMICLR

Non-Maskable Interrupt Status Clear Register
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMICLR NMICLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IWDTCLR WDTCLR LVD1CLR LVD2CLR OSTCLR NMICLR RPECLR BUSSCLR BUSMCLR SPECLR

IWDTCLR : IWDT Clear
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.IWDTST flag

End of enumeration elements list.

WDTCLR : WDT Clear
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.WDTST flag

End of enumeration elements list.

LVD1CLR : LVD1 Clear
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.LVD1ST flag

End of enumeration elements list.

LVD2CLR : LVD2 Clear
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.LVD2ST flag.

End of enumeration elements list.

OSTCLR : OST Clear
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.OSTST flag

End of enumeration elements list.

NMICLR : NMI Clear
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.NMIST flag

End of enumeration elements list.

RPECLR : SRAM Parity Error Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.RPEST flag

End of enumeration elements list.

BUSSCLR : Bus Slave Error Clear
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.BUSSST flag

End of enumeration elements list.

BUSMCLR : Bus Master Error Clear
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.BUSMST flag

End of enumeration elements list.

SPECLR : CPU Stack Pointer Monitor Interrupt Clear
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.SPEST flag

End of enumeration elements list.


NMISR

Non-Maskable Interrupt Status Register
address_offset : 0x140 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NMISR NMISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IWDTST WDTST LVD1ST LVD2ST OSTST NMIST RPEST BUSSST BUSMST SPEST

IWDTST : IWDT Underflow/Refresh Error Status Flag
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.

WDTST : WDT Underflow/Refresh Error Status Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.

LVD1ST : Voltage Monitor 1 Interrupt Status Flag
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.

LVD2ST : Voltage Monitor 2 Interrupt Status Flag
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.

OSTST : Oscillation Stop Detection Interrupt Status Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested for main oscillation stop

#1 : 1

Interrupt requested for main oscillation stop

End of enumeration elements list.

NMIST : NMI Status Flag
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.

RPEST : SRAM Parity Error Interrupt Status Flag
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.

BUSSST : MPU Bus Slave Error Interrupt Status Flag
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested.

End of enumeration elements list.

BUSMST : MPU Bus Master Error Interrupt Status Flag
bits : 11 - 10 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.

SPEST : CPU Stack Pointer Monitor Interrupt Status Flag
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.


WUPEN

Wake Up Interrupt Enable Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WUPEN WUPEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQWUPEN IWDTWUPEN KEYWUPEN LVD1WUPEN LVD2WUPEN ACMPLP0WUPEN RTCALMWUPEN RTCPRDWUPEN AGT1UDWUPEN AGT1CAWUPEN AGT1CBWUPEN IIC0WUPEN

IRQWUPEN : IRQ Interrupt Software Standby Returns Enable
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

#0 : 0

Software Standby returns by IRQn interrupt disabled

#1 : 1

Software Standby returns by IRQn interrupt enabled

End of enumeration elements list.

IWDTWUPEN : IWDT Interrupt Software Standby Returns Enable
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software Standby returns by IWDT interrupt disabled

#1 : 1

Software Standby returns by IWDT interrupt enabled

End of enumeration elements list.

KEYWUPEN : Key Interrupt Software Standby Returns Enable
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software Standby returns by KEY interrupt disabled

#1 : 1

Software Standby returns by KEY interrupt enabled

End of enumeration elements list.

LVD1WUPEN : LVD1 Interrupt Software Standby Returns Enable
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software Standby returns by LVD1 interrupt disabled

#1 : 1

Software Standby returns by LVD1 interrupt enabled

End of enumeration elements list.

LVD2WUPEN : LVD2 Interrupt Software Standby Returns Enable
bits : 19 - 18 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software Standby returns by LVD2 interrupt disabled

#1 : 1

Software Standby returns by LVD2 interrupt enabled

End of enumeration elements list.

ACMPLP0WUPEN : ACMPLP0 Interrupt Software Standby Returns Enable
bits : 23 - 22 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software Standby returns by ACMPLP0 interrupt disabled

#1 : 1

Software Standby returns by ACMPLP0 interrupt enabled

End of enumeration elements list.

RTCALMWUPEN : RTC Alarm Interrupt Software Standby Returns Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software Standby returns by RTC alarm interrupt disabled

#1 : 1

Software Standby returns by RTC alarm interrupt enabled.

End of enumeration elements list.

RTCPRDWUPEN : RTC Period Interrupt Software Standby Returns Enable
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software Standby returns by RTC period interrupt disabled

#1 : 1

Software Standby returns by RTC period interrupt enabled

End of enumeration elements list.

AGT1UDWUPEN : AGT1 Underflow Interrupt Software Standby Returns Enable
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software Standby returns by AGT1 underflow interrupt disabled

#1 : 1

Software Standby returns by AGT1 underflow

End of enumeration elements list.

AGT1CAWUPEN : AGT1 Compare Match A Interrupt Software Standby Returns Enable
bits : 29 - 28 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software Standby returns by AGT1 compare match A interrupt disabled.

#1 : 1

Software Standby returns by AGT1 compare match A interrupt enabled.

End of enumeration elements list.

AGT1CBWUPEN : AGT1 Compare Match B Interrupt Software Standby Returns Enable
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software Standby returns by AGT1 compare match B interrupt disabled.

#1 : 1

Software Standby returns by AGT1 compare match B interrupt enabled.

End of enumeration elements list.

IIC0WUPEN : IIC0 Address Match Interrupt Software Standby Returns Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software Standby returns by IIC0 address match interrupt disabled

#1 : 1

Software Standby returns by IIC0 address match interrupt enabled

End of enumeration elements list.


IELEN

ICU event Enable Register
address_offset : 0x1C0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELEN IELEN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RTCINTEN IELEN

RTCINTEN : RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit = 1)
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

IELEN : Parts Asynchronous Interrupts Enable except RTC (when LPOPTEN bit = 1)
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.


IRQCR2

IRQ Control Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR2 IRQCR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


SELSR0

SYS Event Link Setting Register
address_offset : 0x200 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SELSR0 SELSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQCR3

IRQ Control Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR3 IRQCR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IELSR0

ICU Event Link Setting Register %s
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR0 IELSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR1

ICU Event Link Setting Register %s
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR1 IELSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR2

ICU Event Link Setting Register %s
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR2 IELSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR3

ICU Event Link Setting Register %s
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR3 IELSR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR4

ICU Event Link Setting Register %s
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR4 IELSR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR5

ICU Event Link Setting Register %s
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR5 IELSR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR6

ICU Event Link Setting Register %s
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR6 IELSR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR7

ICU Event Link Setting Register %s
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR7 IELSR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR8

ICU Event Link Setting Register %s
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR8 IELSR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR9

ICU Event Link Setting Register %s
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR9 IELSR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR10

ICU Event Link Setting Register %s
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR10 IELSR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR11

ICU Event Link Setting Register %s
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR11 IELSR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR12

ICU Event Link Setting Register %s
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR12 IELSR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR13

ICU Event Link Setting Register %s
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR13 IELSR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR14

ICU Event Link Setting Register %s
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR14 IELSR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR15

ICU Event Link Setting Register %s
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR15 IELSR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR16

ICU Event Link Setting Register %s
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR16 IELSR16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR17

ICU Event Link Setting Register %s
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR17 IELSR17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR18

ICU Event Link Setting Register %s
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR18 IELSR18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR19

ICU Event Link Setting Register %s
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR19 IELSR19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR20

ICU Event Link Setting Register %s
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR20 IELSR20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR21

ICU Event Link Setting Register %s
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR21 IELSR21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR22

ICU Event Link Setting Register %s
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR22 IELSR22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR23

ICU Event Link Setting Register %s
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR23 IELSR23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR24

ICU Event Link Setting Register %s
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR24 IELSR24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR25

ICU Event Link Setting Register %s
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR25 IELSR25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR26

ICU Event Link Setting Register %s
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR26 IELSR26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR27

ICU Event Link Setting Register %s
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR27 IELSR27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR28

ICU Event Link Setting Register %s
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR28 IELSR28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR29

ICU Event Link Setting Register %s
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR29 IELSR29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR30

ICU Event Link Setting Register %s
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR30 IELSR30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR31

ICU Event Link Setting Register %s
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR31 IELSR31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQCR4

IRQ Control Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR4 IRQCR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IRQCR5

IRQ Control Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR5 IRQCR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IRQCR6

IRQ Control Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR6 IRQCR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IRQCR7

IRQ Control Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR7 IRQCR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.



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