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SYSC

Peripheral Memory Blocks

address_offset : 0xC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x26 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x31 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x36 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3E Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x61 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x92 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x94 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x98 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x9F Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xA2 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xAA Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xE0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3FE Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40E Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x410 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x413 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x417 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x41A Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x480 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x490 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x492 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MSTPCRA

SCKDIVCR

SCKSCR

MEMWAIT

MOSCCR

HOCOCR

MOCOCR

OSCSF

CKOCR

PRCR

OSTDCR

SYOCDCR

OSTDSR

RSTSR0

RSTSR2

MOMCR

LVCMPCR

LVDLVLR

LVD1CR0

LVD2CR0

SOSCCR

SOMCR

SOMRG

LOCOCR

LOCOUTCR

LPOPT

MOCOUTCR

HOCOUTCR

SNZCR

SNZEDCR0

SNZREQCR0

PSMCR

OPCCR

MOSCWTCR

SOPCCR

SBYCR

RSTSR1

LVD1CR1

LVD1SR

LVD2CR1

LVD2SR


MSTPCRA

Module Stop Control Register A
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSTPCRA MSTPCRA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSTPA22

MSTPA22 : DTC Module Stop
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

#0 : 0

Cancel the module-stop state

#1 : 1

Enter the module-stop state

End of enumeration elements list.


SCKDIVCR

System Clock Division Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCKDIVCR SCKDIVCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCKD PCKB ICK

PCKD : Peripheral Module Clock D (PCLKD) Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

x 1/1

#001 : 001

x 1/2

#010 : 010

x 1/4

#011 : 011

x 1/8

#100 : 100

x 1/16

#101 : 101

x 1/32

#110 : 110

x 1/64

: Others

Settings prohibited

End of enumeration elements list.

PCKB : Peripheral Module Clock B (PCLKB) Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : 000

x 1/1

#001 : 001

x 1/2

#010 : 010

x 1/4

#011 : 011

x 1/8

#100 : 100

x 1/16

#101 : 101

x 1/32

#110 : 110

x 1/64

: Others

Settings prohibited

End of enumeration elements list.

ICK : System Clock (ICLK) Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#000 : 000

x 1/1

#001 : 001

x 1/2

#010 : 010

x 1/4

#011 : 011

x 1/8

#100 : 100

x 1/16

#101 : 101

x 1/32

#110 : 110

x 1/64

: Others

Settings prohibited

End of enumeration elements list.


SCKSCR

System Clock Source Control Register
address_offset : 0x26 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCKSCR SCKSCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKSEL

CKSEL : Clock Source Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

HOCO

#001 : 001

MOCO

#010 : 010

LOCO

#011 : 011

Main clock oscillator (MOSC)

#100 : 100

Sub-clock oscillator (SOSC)

End of enumeration elements list.


MEMWAIT

Memory Wait Cycle Control Register for Code Flash
address_offset : 0x31 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMWAIT MEMWAIT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MEMWAIT

MEMWAIT : Memory Wait Cycle Select for Code Flash
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No wait

#1 : 1

Wait

End of enumeration elements list.


MOSCCR

Main Clock Oscillator Control Register
address_offset : 0x32 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOSCCR MOSCCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MOSTP

MOSTP : Main Clock Oscillator Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operate the main clock oscillator

#1 : 1

Stop the main clock oscillator

End of enumeration elements list.


HOCOCR

High-Speed On-Chip Oscillator Control Register
address_offset : 0x36 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOCOCR HOCOCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 HCSTP

HCSTP : HOCO Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operate the HOCO clock

#1 : 1

Stop the HOCO clock

End of enumeration elements list.


MOCOCR

Middle-Speed On-Chip Oscillator Control Register
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOCOCR MOCOCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MCSTP

MCSTP : MOCO Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

MOCO clock is operating

#1 : 1

MOCO clock is stopped

End of enumeration elements list.


OSCSF

Oscillation Stabilization Flag Register
address_offset : 0x3C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OSCSF OSCSF read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 HOCOSF MOSCSF

HOCOSF : HOCO Clock Oscillation Stabilization Flag
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

The HOCO clock is stopped or is not yet stable

#1 : 1

The HOCO clock is stable, so is available for use as the system clock

End of enumeration elements list.

MOSCSF : Main Clock Oscillation Stabilization Flag
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

The main clock oscillator is stopped (MOSTP = 1) or is not yet stable

#1 : 1

The main clock oscillator is stable, so is available for use as the system clock

End of enumeration elements list.


CKOCR

Clock Out Control Register
address_offset : 0x3E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKOCR CKOCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKOSEL CKODIV CKOEN

CKOSEL : Clock Out Source Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

HOCO

#001 : 001

MOCO

#010 : 010

LOCO

#011 : 011

MOSC

#100 : 100

SOSC

#101 : 101

Setting prohibited

: Others

Setting prohibited

End of enumeration elements list.

CKODIV : Clock Output Frequency Division Ratio
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#000 : 000

x 1/1

#001 : 001

x 1/2

#010 : 010

x 1/4

#011 : 011

x 1/8

#100 : 100

x 1/16

#101 : 101

x 1/32

#110 : 110

x 1/64

#111 : 111

x 1/128

End of enumeration elements list.

CKOEN : Clock Out Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable clock out

#1 : 1

Enable clock out

End of enumeration elements list.


PRCR

Protect Register
address_offset : 0x3FE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRCR PRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRC0 PRC1 PRC3 PRKEY

PRC0 : Enable writing to the registers related to the clock generation circuit
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable writes

#1 : 1

Enable writes

End of enumeration elements list.

PRC1 : Enable writing to the registers related to the low power modes
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable writes

#1 : 1

Enable writes

End of enumeration elements list.

PRC3 : Enable writing to the registers related to the LVD
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable writes

#1 : 1

Enable writes

End of enumeration elements list.

PRKEY : PRC Key Code
bits : 8 - 14 (7 bit)
access : write-only


OSTDCR

Oscillation Stop Detection Control Register
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSTDCR OSTDCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OSTDIE OSTDE

OSTDIE : Oscillation Stop Detection Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable oscillation stop detection interrupt (do not notify the POEG)

#1 : 1

Enable oscillation stop detection interrupt (notify the POEG)

End of enumeration elements list.

OSTDE : Oscillation Stop Detection Function Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable oscillation stop detection function

#1 : 1

Enable oscillation stop detection function

End of enumeration elements list.


SYOCDCR

System Control OCD Control Register
address_offset : 0x40E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYOCDCR SYOCDCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGEN

DBGEN : Debugger Enable bit
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

On-chip debugger is disabled

#1 : 1

On-chip debugger is enabled

End of enumeration elements list.


OSTDSR

Oscillation Stop Detection Status Register
address_offset : 0x41 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSTDSR OSTDSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OSTDF

OSTDF : Oscillation Stop Detection Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Main clock oscillation stop not detected

#1 : 1

Main clock oscillation stop detected

End of enumeration elements list.


RSTSR0

Reset Status Register 0
address_offset : 0x410 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTSR0 RSTSR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PORF LVD0RF LVD1RF LVD2RF

PORF : Power-On Reset Detect Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Power-on reset not detected

#1 : 1

Power-on reset detected

End of enumeration elements list.

LVD0RF : Voltage Monitor 0 Reset Detect Flag
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage monitor 0 reset not detected

#1 : 1

Voltage monitor 0 reset detected

End of enumeration elements list.

LVD1RF : Voltage Monitor 1 Reset Detect Flag
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage monitor 1 reset not detected

#1 : 1

Voltage monitor 1 reset detected

End of enumeration elements list.

LVD2RF : Voltage Monitor 2 Reset Detect Flag
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage monitor 2 reset not detected

#1 : 1

Voltage monitor 2 reset detected

End of enumeration elements list.


RSTSR2

Reset Status Register 2
address_offset : 0x411 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTSR2 RSTSR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CWSF

CWSF : Cold/Warm Start Determination Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Cold start

#1 : 1

Warm start

End of enumeration elements list.


MOMCR

Main Clock Oscillator Mode Oscillation Control Register
address_offset : 0x413 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOMCR MOMCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MODRV1 MOSEL

MODRV1 : Main Clock Oscillator Drive Capability 1 Switching
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

10 MHz to 20 MHz

#1 : 1

1 MHz to 10 MHz

End of enumeration elements list.

MOSEL : Main Clock Oscillator Switching
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Resonator

#1 : 1

External clock input

End of enumeration elements list.


LVCMPCR

Voltage Monitor Circuit Control Register
address_offset : 0x417 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVCMPCR LVCMPCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LVD1E LVD2E

LVD1E : Voltage Detection 1 Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage detection 1 circuit disabled

#1 : 1

Voltage detection 1 circuit enabled

End of enumeration elements list.

LVD2E : Voltage Detection 2 Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Voltage detection 2 circuit disabled

#1 : 1

Voltage detection 2 circuit enabled

End of enumeration elements list.


LVDLVLR

Voltage Detection Level Select Register
address_offset : 0x418 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVDLVLR LVDLVLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LVD1LVL LVD2LVL

LVD1LVL : Voltage Detection 1 Level Select (Standard voltage during fall in voltage)
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

Vdet1_0

0x01 : 0x01

Vdet1_1

0x02 : 0x02

Vdet1_2

0x03 : 0x03

Vdet1_3

0x04 : 0x04

Vdet1_4

0x05 : 0x05

Vdet1_5

0x06 : 0x06

Vdet1_6

0x07 : 0x07

Vdet1_7

0x08 : 0x08

Vdet1_8

0x09 : 0x09

Vdet1_9

0x0a : 0x0A

Vdet1_A

0x0b : 0x0B

Vdet1_B

0x0c : 0x0C

Vdet1_C

0x0d : 0x0D

Vdet1_D

0x0e : 0x0E

Vdet1_E

0x0f : 0x0F

Vdet1_F

: Others

Setting prohibited

End of enumeration elements list.

LVD2LVL : Voltage Detection 2 Level Select (Standard voltage during fall in voltage)
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

#000 : 000

Vdet2_0

#001 : 001

Vdet2_1

#010 : 010

Vdet2_2

#011 : 011

Vdet2_3

: Others

Setting prohibited

End of enumeration elements list.


LVD1CR0

Voltage Monitor 1 Circuit Control Register 0
address_offset : 0x41A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVD1CR0 LVD1CR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RIE CMPE RI RN

RIE : Voltage Monitor 1 Interrupt/Reset Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

CMPE : Voltage Monitor 1 Circuit Comparison Result Output Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable voltage monitor 1 circuit comparison result output

#1 : 1

Enable voltage monitor 1 circuit comparison result output

End of enumeration elements list.

RI : Voltage Monitor 1 Circuit Mode Select
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Generate voltage monitor 1 interrupt on Vdet1 crossing

#1 : 1

Enable voltage monitor 1 reset when the voltage falls to and below Vdet1

End of enumeration elements list.

RN : Voltage Monitor 1 Reset Negate Select
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Negate after a stabilization time (tLVD1) when VCC > Vdet1 is detected

#1 : 1

Negate after a stabilization time (tLVD1) on assertion of the LVD1 reset

End of enumeration elements list.


LVD2CR0

Voltage Monitor 2 Circuit Control Register 0
address_offset : 0x41B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVD2CR0 LVD2CR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RIE CMPE RI RN

RIE : Voltage Monitor 2 Interrupt/Reset Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

CMPE : Voltage Monitor 2 Circuit Comparison Result Output Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable voltage monitor 2 circuit comparison result output

#1 : 1

Enable voltage monitor 2 circuit comparison result output

End of enumeration elements list.

RI : Voltage Monitor 2 Circuit Mode Select
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Generate voltage monitor 2 interrupt on Vdet2 crossing

#1 : 1

Enable voltage monitor 2 reset when the voltage falls to and below Vdet2

End of enumeration elements list.

RN : Voltage Monitor 2 Reset Negate Select
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Negate after a stabilization time (tLVD2) when VCC > Vdet2 is detected

#1 : 1

Negate after a stabilization time (tLVD2) on assertion of the LVD2 reset

End of enumeration elements list.


SOSCCR

Sub-Clock Oscillator Control Register
address_offset : 0x480 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOSCCR SOSCCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOSTP

SOSTP : Sub Clock Oscillator Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operate the sub-clock oscillator

#1 : 1

Stop the sub-clock oscillator

End of enumeration elements list.


SOMCR

Sub-Clock Oscillator Mode Control Register
address_offset : 0x481 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOMCR SOMCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SODRV

SODRV : Sub-Clock Oscillator Drive Capability Switching
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Normal Mode

#01 : 01

Low Power Mode 1

#10 : 10

Low Power Mode 2

#11 : 11

Low Power Mode 3

End of enumeration elements list.


SOMRG

Sub-Clock Oscillator Margin Check Register
address_offset : 0x482 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOMRG SOMRG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOSCMRG

SOSCMRG : Sub Clock Oscillator Margin check Switching
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Normal Current

#01 : 01

Lower Margin check

#10 : 10

Upper Margin check

#11 : 11

Setting prohibited

End of enumeration elements list.


LOCOCR

Low-Speed On-Chip Oscillator Control Register
address_offset : 0x490 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCOCR LOCOCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LCSTP

LCSTP : LOCO Stop
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Operate the LOCO clock

#1 : 1

Stop the LOCO clock

End of enumeration elements list.


LOCOUTCR

LOCO User Trimming Control Register
address_offset : 0x492 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCOUTCR LOCOUTCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LOCOUTRM

LOCOUTRM : LOCO User Trimming
bits : 0 - 6 (7 bit)
access : read-write


LPOPT

Lower Power Operation Control Register
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPOPT LPOPT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MPUDIS DCLKDIS BPFCLKDIS LPOPTEN

MPUDIS : MPU Clock Disable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

MPU operates as normal

#1 : 1

MPU operate clock stops (MPU function disable).

End of enumeration elements list.

DCLKDIS : Debug Clock Disable Control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#00 : 00

Debug clock does not stop

: Others

Debug clock stops (valid only when LPOPT.LPOPTEN = 1)

End of enumeration elements list.

BPFCLKDIS : BPF Clock Disable Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Flash register R/W clock operates as normal

#1 : 1

Flash register R/W clock stops.

End of enumeration elements list.

LPOPTEN : Lower Power Operation Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

All lower power counter measure disable

#1 : 1

All lower power counter measure enable

End of enumeration elements list.


MOCOUTCR

MOCO User Trimming Control Register
address_offset : 0x61 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOCOUTCR MOCOUTCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MOCOUTRM

MOCOUTRM : MOCO User Trimming
bits : 0 - 6 (7 bit)
access : read-write


HOCOUTCR

HOCO User Trimming Control Register
address_offset : 0x62 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOCOUTCR HOCOUTCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 HOCOUTRM

HOCOUTRM : HOCO User Trimming
bits : 0 - 6 (7 bit)
access : read-write


SNZCR

Snooze Control Register
address_offset : 0x92 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNZCR SNZCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RXDREQEN SNZDTCEN SNZE

RXDREQEN : RXD0 Snooze Request Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Ignore RXD0 falling edge in Software Standby mode

#1 : 1

Detect RXD0 falling edge in Software Standby mode

End of enumeration elements list.

SNZDTCEN : DTC Enable in Snooze mode
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable DTC operation

#1 : 1

Enable DTC operation

End of enumeration elements list.

SNZE : Snooze mode Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable Snooze mode

#1 : 1

Enable Snooze mode

End of enumeration elements list.


SNZEDCR0

Snooze End Control Register 0
address_offset : 0x94 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNZEDCR0 SNZEDCR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AGTUNFED DTCZRED DTCNZRED AD0MATED AD0UMTED SCI0UMTED

AGTUNFED : AGT1 Underflow Snooze End Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze end request

#1 : 1

Enable the snooze end request

End of enumeration elements list.

DTCZRED : Last DTC Transmission Completion Snooze End Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze end request

#1 : 1

Enable the snooze end request

End of enumeration elements list.

DTCNZRED : Not Last DTC Transmission Completion Snooze End Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze end request

#1 : 1

Enable the snooze end request

End of enumeration elements list.

AD0MATED : AD120 Compare Match Snooze End Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze end request

#1 : 1

Enable the snooze end request

End of enumeration elements list.

AD0UMTED : AD120 Compare Mismatch Snooze End Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze end request

#1 : 1

Enable the snooze end request

End of enumeration elements list.

SCI0UMTED : SCI0 Address Mismatch Snooze End Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze end request

#1 : 1

Enable the snooze end request

End of enumeration elements list.


SNZREQCR0

Snooze Request Control Register 0
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNZREQCR0 SNZREQCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SNZREQEN0 SNZREQEN1 SNZREQEN2 SNZREQEN3 SNZREQEN4 SNZREQEN5 SNZREQEN6 SNZREQEN7 SNZREQEN17 SNZREQEN23 SNZREQEN24 SNZREQEN25 SNZREQEN28 SNZREQEN29 SNZREQEN30

SNZREQEN0 : Enable IRQ0 pin snooze request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze request

#1 : 1

Enable the snooze request

End of enumeration elements list.

SNZREQEN1 : Enable IRQ1 pin snooze request
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze request

#1 : 1

Enable the snooze request

End of enumeration elements list.

SNZREQEN2 : Enable IRQ2 pin snooze request
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze request

#1 : 1

Enable the snooze request

End of enumeration elements list.

SNZREQEN3 : Enable IRQ3 pin snooze request
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze request

#1 : 1

Enable the snooze request

End of enumeration elements list.

SNZREQEN4 : Enable IRQ4 pin snooze request
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze request

#1 : 1

Enable the snooze request

End of enumeration elements list.

SNZREQEN5 : Enable IRQ5 pin snooze request
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze request

#1 : 1

Enable the snooze request

End of enumeration elements list.

SNZREQEN6 : Enable IRQ6 pin snooze request
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze request

#1 : 1

Enable the snooze request

End of enumeration elements list.

SNZREQEN7 : Enable IRQ7 pin snooze request
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze request

#1 : 1

Enable the snooze request

End of enumeration elements list.

SNZREQEN17 : Enable KEY_INTKR snooze request
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze request

#1 : 1

Enable the snooze request

End of enumeration elements list.

SNZREQEN23 : Enable ACMPLP snooze request
bits : 23 - 22 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze request

#1 : 1

Enable the snooze request

End of enumeration elements list.

SNZREQEN24 : Enable RTC alarm snooze request
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze request

#1 : 1

Enable the snooze request

End of enumeration elements list.

SNZREQEN25 : Enable RTC period snooze request
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze request

#1 : 1

Enable the snooze request

End of enumeration elements list.

SNZREQEN28 : Enable AGT1 underflow snooze request
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze request

#1 : 1

Enable the snooze request

End of enumeration elements list.

SNZREQEN29 : Enable AGT1 compare match A snooze request
bits : 29 - 28 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze request

#1 : 1

Enable the snooze request

End of enumeration elements list.

SNZREQEN30 : Enable AGT1 compare match B snooze request
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable the snooze request

#1 : 1

Enable the snooze request

End of enumeration elements list.


PSMCR

Power Save Memory Control Register
address_offset : 0x9F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSMCR PSMCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PSMC

PSMC : Power Save Memory Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

All SRAMs are on in Software Standby mode

#01 : 01

8 KB SRAM (0x2000_4000 to 0x2000_5FFF) is on in Software Standby mode

#10 : 10

Setting prohibited

#11 : 11

Setting prohibited

End of enumeration elements list.


OPCCR

Operating Power Control Register
address_offset : 0xA0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPCCR OPCCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OPCM OPCMTSF

OPCM : Operating Power Control Mode Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

High-speed mode

#01 : 01

Middle-speed mode

#10 : 10

Setting prohibited

#11 : 11

Low-speed mode

End of enumeration elements list.

OPCMTSF : Operating Power Control Mode Transition Status Flag
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transition completed

#1 : 1

During transition

End of enumeration elements list.


MOSCWTCR

Main Clock Oscillator Wait Control Register
address_offset : 0xA2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOSCWTCR MOSCWTCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MSTS

MSTS : Main Clock Oscillator Wait Time Setting
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

Wait time = 2 cycles (0.25 us)

0x1 : 0x1

Wait time = 1024 cycles (128 us)

0x2 : 0x2

Wait time = 2048 cycles (256 us)

0x3 : 0x3

Wait time = 4096 cycles (512 us)

0x4 : 0x4

Wait time = 8192 cycles (1024 us)

0x5 : 0x5

Wait time = 16384 cycles (2048 us)

0x6 : 0x6

Wait time = 32768 cycles (4096 us)

0x7 : 0x7

Wait time = 65536 cycles (8192 us)

0x8 : 0x8

Wait time = 131072 cycles (16384 us)

0x9 : 0x9

Wait time = 262144 cycles (32768 us)

: Others

Setting prohibited

End of enumeration elements list.


SOPCCR

Sub Operating Power Control Register
address_offset : 0xAA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOPCCR SOPCCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOPCM SOPCMTSF

SOPCM : Sub Operating Power Control Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Other than Subosc-speed mode

#1 : 1

Subosc-speed mode

End of enumeration elements list.

SOPCMTSF : Operating Power Control Mode Transition Status Flag
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transition completed

#1 : 1

During transition

End of enumeration elements list.


SBYCR

Standby Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SBYCR SBYCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSBY

SSBY : Software Standby Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Sleep mode

#1 : 1

Software Standby mode.

End of enumeration elements list.


RSTSR1

Reset Status Register 1
address_offset : 0xC0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTSR1 RSTSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IWDTRF WDTRF SWRF RPERF BUSSRF BUSMRF SPERF

IWDTRF : Independent Watchdog Timer Reset Detect Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Independent watchdog timer reset not detected

#1 : 1

Independent watchdog timer reset detected

End of enumeration elements list.

WDTRF : Watchdog Timer Reset Detect Flag
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer reset not detected

#1 : 1

Watchdog timer reset detected

End of enumeration elements list.

SWRF : Software Reset Detect Flag
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software reset not detected

#1 : 1

Software reset detected

End of enumeration elements list.

RPERF : SRAM Parity Error Reset Detect Flag
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

SRAM parity error reset not detected

#1 : 1

SRAM parity error reset detected

End of enumeration elements list.

BUSSRF : Bus Slave MPU Error Reset Detect Flag
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus slave MPU error reset not detected

#1 : 1

Bus slave MPU error reset detected

End of enumeration elements list.

BUSMRF : Bus Master MPU Error Reset Detect Flag
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus master MPU error reset not detected

#1 : 1

Bus master MPU error reset detected

End of enumeration elements list.

SPERF : CPU Stack Pointer Error Reset Detect Flag
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

CPU stack pointer error reset not detected

#1 : 1

CPU stack pointer error reset detected

End of enumeration elements list.


LVD1CR1

Voltage Monitor 1 Circuit Control Register
address_offset : 0xE0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVD1CR1 LVD1CR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IDTSEL IRQSEL

IDTSEL : Voltage Monitor 1 Interrupt Generation Condition Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

When VCC >= Vdet1 (rise) is detected

#01 : 01

When VCC < Vdet1 (fall) is detected

#10 : 10

When fall and rise are detected

#11 : 11

Settings prohibited

End of enumeration elements list.

IRQSEL : Voltage Monitor 1 Interrupt Type Select
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non-maskable interrupt

#1 : 1

Maskable interrupt

End of enumeration elements list.


LVD1SR

Voltage Monitor 1 Circuit Status Register
address_offset : 0xE1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVD1SR LVD1SR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DET MON

DET : Voltage Monitor 1 Voltage Variation Detection Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not detected

#1 : 1

Vdet1 crossing is detected

End of enumeration elements list.

MON : Voltage Monitor 1 Signal Monitor Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

VCC < Vdet1

#1 : 1

VCC >= Vdet1 or MON is disabled

End of enumeration elements list.


LVD2CR1

Voltage Monitor 2 Circuit Control Register 1
address_offset : 0xE2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVD2CR1 LVD2CR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IDTSEL IRQSEL

IDTSEL : Voltage Monitor 2 Interrupt Generation Condition Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

When VCC>= Vdet2 (rise) is detected

#01 : 01

When VCC < Vdet2 (fall) is detected

#10 : 10

When fall and rise are detected

#11 : 11

Settings prohibited

End of enumeration elements list.

IRQSEL : Voltage Monitor 2 Interrupt Type Select
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non-maskable interrupt

#1 : 1

Maskable interrupt

End of enumeration elements list.


LVD2SR

Voltage Monitor 2 Circuit Status Register
address_offset : 0xE3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LVD2SR LVD2SR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DET MON

DET : Voltage Monitor 2 Voltage Variation Detection Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Not detected

#1 : 1

Vdet2 crossing is detected

End of enumeration elements list.

MON : Voltage Monitor 2 Signal Monitor Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

VCC < Vdet2

#1 : 1

VCC>= Vdet2 or MON is disabled

End of enumeration elements list.



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