\n

WDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WDTRR

WDTCR

WDTSR

WDTRCR

WDTCSTPR


WDTRR

WDT Refresh Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTRR WDTRR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

WDTCR

WDT Control Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTCR WDTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOPS CKS RPES RPSS

TOPS : Timeout Period Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

1024 cycles (0x03FF)

#01 : 01

4096 cycles (0x0FFF)

#10 : 10

8192 cycles (0x1FFF)

#11 : 11

16384 cycles (0x3FFF)

End of enumeration elements list.

CKS : Clock Division Ratio Select
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x1 : 0x1

PCLKB/4

0x4 : 0x4

PCLKB/64

0xf : 0xF

PCLKB/128

0x6 : 0x6

PCLKB/512

0x7 : 0x7

PCLKB/2048

0x8 : 0x8

PCLKB/8192

: Others

Setting prohibited

End of enumeration elements list.

RPES : Window End Position Select
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : 00

75%

#01 : 01

50%

#10 : 10

25%

#11 : 11

0% (do not specify window end position).

End of enumeration elements list.

RPSS : Window Start Position Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#00 : 00

25%

#01 : 01

50%

#10 : 10

75%

#11 : 11

100% (do not specify window start position).

End of enumeration elements list.


WDTSR

WDT Status Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTSR WDTSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTVAL UNDFF REFEF

CNTVAL : Down-Counter Value
bits : 0 - 12 (13 bit)
access : read-only

UNDFF : Underflow Flag
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

No underflow occurred

#1 : 1

Underflow occurred

End of enumeration elements list.

REFEF : Refresh Error Flag
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

No refresh error occurred

#1 : 1

Refresh error occurred

End of enumeration elements list.


WDTRCR

WDT Reset Control Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTRCR WDTRCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RSTIRQS

RSTIRQS : Reset Interrupt Request Select
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Enable non-maskable interrupt request or interrupt request output

#1 : 1

Enable reset output

End of enumeration elements list.


WDTCSTPR

WDT Count Stop Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTCSTPR WDTCSTPR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLCSTP

SLCSTP : WDT Count Stop Control Register
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable count stop

#1 : 1

Stop count on transition to Sleep mode

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.