\n
address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
D/A Data Register 0
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D/A Control Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAOE0 : D/A Output Enable 0
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable analog output of channel 0 (DA0)
#1 : 1
Enable D/A conversion of channel 0 (DA0)
End of enumeration elements list.
DADR0 Format Select Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPSEL : DADR0 Format Select
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Right-justified format
#1 : 1
Left-justified format
End of enumeration elements list.
D/A A/D Synchronous Start Control Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAADST : D/A A/D Synchronous Conversion
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not synchronize DAC12 with ADC12 operation (disable interference reduction between D/A and A/D conversion).
#1 : 1
Synchronize DAC12 with ADC12 operation (enable interference reduction between D/A and A/D conversion).
End of enumeration elements list.
D/A VREF Control Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REF : D/A Reference Voltage Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No reference voltage selected.
#1 : 1
AVCC0/AVSS0 selected.
End of enumeration elements list.
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