Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1D byte (0x0)
mem_usage : registers
protection : not protected
Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKS : Clock Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLK clock (n = 0)
#01 : 01
PCLK/4 clock (n = 1)
#10 : 10
PCLK/16 clock (n = 2)
#11 : 11
PCLK/64 clock (n = 3)
End of enumeration elements list.
MP : Multi-Processor Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable multi-processor communications function
#1 : 1
Enable multi-processor communications function
End of enumeration elements list.
STOP : Stop Bit Length
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
1 stop bit
#1 : 1
2 stop bits
End of enumeration elements list.
PM : Parity Mode
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Even parity
#1 : 1
Odd parity
End of enumeration elements list.
PE : Parity Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
When transmitting: Do not add parity bit When receiving: Do not check parity bit
#1 : 1
When transmitting: Add parity bit When receiving: Check parity bit
End of enumeration elements list.
CHR : Character Length
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value)
#1 : 1
SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 7-bit data length
End of enumeration elements list.
CM : Communication Mode
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Asynchronous mode or simple IIC mode
#1 : 1
Clock synchronous mode or simple SPI mode
End of enumeration elements list.
Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1)
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SMR
reset_Mask : 0x0
CKS : Clock Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLK clock (n = 0)
#01 : 01
PCLK/4 clock (n = 1)
#10 : 10
PCLK/16 clock (n = 2)
#11 : 11
PCLK/64 clock (n = 3)
End of enumeration elements list.
BCP : Base Clock Pulse
bits : 2 - 2 (1 bit)
access : read-write
PM : Parity Mode
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Even parity
#1 : 1
Odd parity
End of enumeration elements list.
PE : Parity Enable
bits : 5 - 4 (0 bit)
access : read-write
BLK : Block Transfer Mode
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal mode operation
#1 : 1
Block transfer mode operation
End of enumeration elements list.
GM : GSM Mode
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal mode operation
#1 : 1
GSM mode operation
End of enumeration elements list.
Bit Rate Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Receive FIFO Data Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDAT : Serial receive data
bits : 0 - 7 (8 bit)
access : read-only
MPB : Multi-Processor Bit Flag
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : 0
Data transmission cycle
#1 : 1
ID transmission cycle
End of enumeration elements list.
DR : Receive Data Ready Flag
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : 0
Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception
#1 : 1
Next receive data is not received for a period after successfully completed reception
End of enumeration elements list.
PER : Parity Error Flag
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
#0 : 0
No parity error occurred in the first data of FRDRH and FRDRL
#1 : 1
Parity error occurred in the first data of FRDRH and FRDRL
End of enumeration elements list.
FER : Framing Error Flag
bits : 12 - 11 (0 bit)
access : read-only
Enumeration:
#0 : 0
No framing error occurred in the first data of FRDRH and FRDRL
#1 : 1
Framing error occurred in the first data of FRDRH and FRDRL
End of enumeration elements list.
ORER : Overrun Error Flag
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : 0
No overrun error occurred
#1 : 1
Overrun error occurred
End of enumeration elements list.
RDF : Receive FIFO Data Full Flag
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number
#1 : 1
The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number
End of enumeration elements list.
Transmit FIFO Data Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
alternate_register : FRDRHL
reset_Mask : 0x0
TDAT : Serial transmit data
bits : 0 - 7 (8 bit)
access : write-only
MPBT : Multi-Processor Transfer Bit Flag
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : 0
Data transmission cycle
#1 : 1
ID transmission cycle
End of enumeration elements list.
Receive Data Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : FRDRHL
reset_Mask : 0x0
RDAT : Serial Receive Data
bits : 0 - 7 (8 bit)
access : read-only
Receive FIFO Data Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
alternate_register : FRDRHL
reset_Mask : 0x0
MPB : Multi-Processor Bit Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
Data transmission cycle
#1 : 1
ID transmission cycle
End of enumeration elements list.
DR : Receive Data Ready Flag
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception
#1 : 1
Next receive data is not received for a period after successfully completed reception
End of enumeration elements list.
PER : Parity Error Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
No parity error occurred in the first data of FRDRH and FRDRL
#1 : 1
Parity error occurred in the first data of FRDRH and FRDRL
End of enumeration elements list.
FER : Framing Error Flag
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
No framing error occurred in the first data of FRDRH and FRDRL
#1 : 1
Framing error occurred in the first data of FRDRH and FRDRL
End of enumeration elements list.
ORER : Overrun Error Flag
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
No overrun error occurred
#1 : 1
Overrun error occurred
End of enumeration elements list.
RDF : Receive FIFO Data Full Flag
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number
#1 : 1
The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number
End of enumeration elements list.
Transmit FIFO Data Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
alternate_register : FRDRHL
reset_Mask : 0x0
MPBT : Multi-Processor Transfer Bit Flag
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : 0
Data transmission cycle
#1 : 1
ID transmission cycle
End of enumeration elements list.
Receive FIFO Data Register
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
alternate_register : FRDRHL
reset_Mask : 0x0
RDAT : Serial receive data
bits : 0 - 6 (7 bit)
access : read-only
Transmit FIFO Data Register
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
alternate_register : FRDRL
reset_Mask : 0x0
TDAT : Serial transmit data
bits : 0 - 6 (7 bit)
access : write-only
Modulation Duty Register
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Compare Match Control Register
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMF : Data Compare Match Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not matched
#1 : 1
Matched
End of enumeration elements list.
DPER : Data Compare Match Parity Error Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No parity error occurred
#1 : 1
Parity error occurred
End of enumeration elements list.
DFER : Data Compare Match Framing Error Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No framing error occurred
#1 : 1
Framing error occurred
End of enumeration elements list.
IDSEL : ID Frame Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Always compare data regardless of the MPB bit value
#1 : 1
Only compare data when MPB bit = 1 (ID frame)
End of enumeration elements list.
DCME : Data Compare Match Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable address match function
#1 : 1
Enable address match function
End of enumeration elements list.
FIFO Control Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FM : FIFO Mode Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication.
#1 : 1
FIFO mode. Selects FTDRHL/FRDRHL for communication.
End of enumeration elements list.
RFRST : Receive FIFO Data Register Reset
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not reset FRDRHL
#1 : 1
Reset FRDRHL
End of enumeration elements list.
TFRST : Transmit FIFO Data Register Reset
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not reset FTDRHL
#1 : 1
Reset FTDRHL
End of enumeration elements list.
DRES : Receive Data Ready Error Select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Receive data full interrupt (SCIn_RXI)
#1 : 1
Receive error interrupt (SCIn_ERI)
End of enumeration elements list.
TTRG : Transmit FIFO Data Trigger Number
bits : 4 - 6 (3 bit)
access : read-write
RTRG : Receive FIFO Data Trigger Number
bits : 8 - 10 (3 bit)
access : read-write
RSTRG : RTS Output Active Trigger Number Select
bits : 12 - 14 (3 bit)
access : read-write
FIFO Data Count Register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
R : Receive FIFO Data Count
bits : 0 - 3 (4 bit)
access : read-only
T : Transmit FIFO Data Count
bits : 8 - 11 (4 bit)
access : read-only
Line Status Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ORER : Overrun Error Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No overrun error occurred
#1 : 1
Overrun error occurred
End of enumeration elements list.
FNUM : Framing Error Count
bits : 2 - 5 (4 bit)
access : read-only
PNUM : Parity Error Count
bits : 8 - 11 (4 bit)
access : read-only
Compare Match Data Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPD : Compare Match Data
bits : 0 - 7 (8 bit)
access : read-write
Serial Port Register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDMON : Serial Input Data Monitor
bits : 0 - -1 (0 bit)
access : read-only
SPB2DT : Serial Port Break Data Select
bits : 1 - 0 (0 bit)
access : read-write
SPB2IO : Serial Port Break I/O
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not output value of SPB2DT bit on TXD pin
#1 : 1
Output value of SPB2DT bit on TXD pin
End of enumeration elements list.
Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKE : Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin.
#01 : 01
In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin.
: Others
In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin.
End of enumeration elements list.
TEIE : Transmit End Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable SCIn_TEI interrupt requests
#1 : 1
Enable SCIn_TEI interrupt requests
End of enumeration elements list.
MPIE : Multi-Processor Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal reception
#1 : 1
When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed.
End of enumeration elements list.
RE : Receive Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable serial reception
#1 : 1
Enable serial reception
End of enumeration elements list.
TE : Transmit Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable serial transmission
#1 : 1
Enable serial transmission
End of enumeration elements list.
RIE : Receive Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable SCIn_RXI and SCIn_ERI interrupt requests
#1 : 1
Enable SCIn_RXI and SCIn_ERI interrupt requests
End of enumeration elements list.
TIE : Transmit Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable SCIn_TXI interrupt requests
#1 : 1
Enable SCIn_TXI interrupt requests
End of enumeration elements list.
Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1)
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SCR
reset_Mask : 0x0
CKE : Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low
#01 : 01
When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock
#10 : 10
When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high
#11 : 11
When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock
End of enumeration elements list.
TEIE : Transmit End Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
MPIE : Multi-Processor Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
RE : Receive Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable serial reception
#1 : 1
Enable serial reception
End of enumeration elements list.
TE : Transmit Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable serial transmission
#1 : 1
Enable serial transmission
End of enumeration elements list.
RIE : Receive Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable SCIn_RXI and SCIn_ERI interrupt requests
#1 : 1
Enable SCIn_RXI and SCIn_ERI interrupt requests
End of enumeration elements list.
TIE : Transmit Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable SCIn_TXI interrupt requests
#1 : 1
Enable SCIn_TXI interrupt requests
End of enumeration elements list.
Transmit Data Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0)
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPBT : Multi-Processor Bit Transfer
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data transmission cycle
#1 : 1
ID transmission cycle
End of enumeration elements list.
MPB : Multi-Processor
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
Data transmission cycle
#1 : 1
ID transmission cycle
End of enumeration elements list.
TEND : Transmit End Flag
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
A character is being transmitted
#1 : 1
Character transfer is complete
End of enumeration elements list.
PER : Parity Error Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No parity error occurred
#1 : 1
Parity error occurred
End of enumeration elements list.
FER : Framing Error Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No framing error occurred
#1 : 1
Framing error occurred
End of enumeration elements list.
ORER : Overrun Error Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
No overrun error occurred
#1 : 1
Overrun error occurred
End of enumeration elements list.
RDRF : Receive Data Full Flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No received data in RDR register
#1 : 1
Received data in RDR register
End of enumeration elements list.
TDRE : Transmit Data Empty Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit data in TDR register
#1 : 1
No transmit data in TDR register
End of enumeration elements list.
Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0, FCR.FM = 1)
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SSR
reset_Mask : 0x0
DR : Receive Data Ready Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty)
#1 : 1
Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number
End of enumeration elements list.
TEND : Transmit End Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
A character is being transmitted
#1 : 1
Character transfer is complete
End of enumeration elements list.
PER : Parity Error Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No parity error occurred
#1 : 1
Parity error occurred
End of enumeration elements list.
FER : Framing Error Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No framing error occurred
#1 : 1
Framing error occurred
End of enumeration elements list.
ORER : Overrun Error Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
No overrun error occurred
#1 : 1
Overrun error occurred
End of enumeration elements list.
RDF : Receive FIFO Data Full Flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
The amount of receive data written in FRDRHL is less than the specified receive triggering number
#1 : 1
The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number
End of enumeration elements list.
TDFE : Transmit FIFO Data Empty Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number
#1 : 1
The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number
End of enumeration elements list.
Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1)
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SSR
reset_Mask : 0x0
MPBT : Multi-Processor Bit Transfer
bits : 0 - -1 (0 bit)
access : read-write
MPB : Multi-Processor
bits : 1 - 0 (0 bit)
access : read-only
TEND : Transmit End Flag
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
A character is being transmitted
#1 : 1
Character transfer is complete
End of enumeration elements list.
PER : Parity Error Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No parity error occurred
#1 : 1
Parity error occurred
End of enumeration elements list.
ERS : Error Signal Status Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No low error signal response
#1 : 1
Low error signal response occurred
End of enumeration elements list.
ORER : Overrun Error Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
No overrun error occurred
#1 : 1
Overrun error occurred
End of enumeration elements list.
RDRF : Receive Data Full Flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No received data in RDR register
#1 : 1
Received data in RDR register
End of enumeration elements list.
TDRE : Transmit Data Empty Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit data in TDR register
#1 : 1
No transmit data in TDR register
End of enumeration elements list.
Receive Data Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Smart Card Mode Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMIF : Smart Card Interface Mode Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode)
#1 : 1
Smart card interface mode
End of enumeration elements list.
SINV : Transmitted/Received Data Invert
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
TDR contents are transmitted as they are. Received data is stored as received in the RDR register.
#1 : 1
TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register.
End of enumeration elements list.
SDIR : Transmitted/Received Data Transfer Direction
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transfer LSB-first
#1 : 1
Transfer MSB-first
End of enumeration elements list.
CHR1 : Character Length 1
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
SMR.CHR = 0: Transmit/receive in 9-bit data length SMR.CHR = 1: Transmit/receive in 9-bit data length
#1 : 1
SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) SMR.CHR = 1: Transmit/receive in 7-bit data length
End of enumeration elements list.
BCP2 : Base Clock Pulse 2
bits : 7 - 6 (0 bit)
access : read-write
Serial Extended Mode Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRME : Bit Rate Modulation Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable bit rate modulation function
#1 : 1
Enable bit rate modulation function
End of enumeration elements list.
ABCSE : Asynchronous Mode Extended Base Clock Select 1
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register
#1 : 1
Baud rate is 6 base clock cycles for 1-bit period
End of enumeration elements list.
ABCS : Asynchronous Mode Base Clock Select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Select 16 base clock cycles for 1-bit period
#1 : 1
Select 8 base clock cycles for 1-bit period
End of enumeration elements list.
NFEN : Digital Noise Filter Function Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals
#1 : 1
In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals
End of enumeration elements list.
BGDM : Baud Rate Generator Double-Speed Mode Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output clock from baud rate generator with normal frequency
#1 : 1
Output clock from baud rate generator with doubled frequency
End of enumeration elements list.
RXDESEL : Asynchronous Start Bit Edge Detection Select
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Detect low level on RXDn pin as start bit
#1 : 1
Detect falling edge of RXDn pin as start bit
End of enumeration elements list.
Noise Filter Setting Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NFCS : Noise Filter Clock Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
In asynchronous mode: Use clock signal divided by 1 with noise filter In simple IIC mode: Setting prohibited
#001 : 001
In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 1 with noise filter
#010 : 010
In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 2 with noise filter
#011 : 011
In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 4 with noise filter
#100 : 100
In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 8 with noise filter
: Others
Setting prohibited
End of enumeration elements list.
IIC Mode Register 1
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IICM : Simple IIC Mode Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode
#1 : 1
SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited
End of enumeration elements list.
IICDL : SDAn Delay Output Select
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0x00 : 0x00
No output delay
: Others
(IICDL - 1) to (IICDL) cycles
End of enumeration elements list.
IIC Mode Register 2
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IICINTM : IIC Interrupt Mode Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Use ACK/NACK interrupts
#1 : 1
Use reception and transmission interrupts
End of enumeration elements list.
IICCSC : Clock Synchronization
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not synchronize with clock signal
#1 : 1
Synchronize with clock signal
End of enumeration elements list.
IICACKT : ACK Transmission Data
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
ACK transmission
#1 : 1
NACK transmission and ACK/NACK reception
End of enumeration elements list.
IIC Mode Register 3
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IICSTAREQ : Start Condition Generation
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not generate start condition
#1 : 1
Generate start condition
End of enumeration elements list.
IICRSTAREQ : Restart Condition Generation
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not generate restart condition
#1 : 1
Generate restart condition
End of enumeration elements list.
IICSTPREQ : Stop Condition Generation
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not generate stop condition
#1 : 1
Generate stop condition
End of enumeration elements list.
IICSTIF : Issuing of Start, Restart, or Stop Condition Completed Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No requests are being made for generating conditions, or a condition is being generated
#1 : 1
Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0
End of enumeration elements list.
IICSDAS : SDAn Output Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
Output serial data
#01 : 01
Generate start, restart, or stop condition
#10 : 10
Output low on SDAn pin
#11 : 11
Drive SDAn pin to high-impedance state
End of enumeration elements list.
IICSCLS : SCLn Output Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
Output serial clock
#01 : 01
Generate start, restart, or stop condition
#10 : 10
Output low on SCLn pin
#11 : 11
Drive SCLn pin to high-impedance state
End of enumeration elements list.
IIC Status Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IICACKR : ACK Reception Data Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
ACK received
#1 : 1
NACK received
End of enumeration elements list.
SPI Mode Register
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSE : SSn Pin Function Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable SSn pin function
#1 : 1
Enable SSn pin function
End of enumeration elements list.
CTSE : CTS Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable CTS function (enable RTS output function)
#1 : 1
Enable CTS function
End of enumeration elements list.
MSS : Master Slave Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit through TXDn pin and receive through RXDn pin (master mode)
#1 : 1
Receive through TXDn pin and transmit through RXDn pin (slave mode)
End of enumeration elements list.
MFF : Mode Fault Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No mode fault error
#1 : 1
Mode fault error
End of enumeration elements list.
CKPOL : Clock Polarity Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not invert clock polarity
#1 : 1
Invert clock polarity
End of enumeration elements list.
CKPH : Clock Phase Select
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not delay clock
#1 : 1
Delay clock
End of enumeration elements list.
Transmit Data Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDAT : Serial Transmit Data
bits : 0 - 7 (8 bit)
access : read-write
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