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SPI0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xA Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SPCR

SSLP

SPCMD0

SPPCR

SPSR

SPDR

SPDR_HA

SPBR

SPDCR

SPCKD

SSLND

SPND

SPCR2


SPCR

SPI Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCR SPCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPMS TXMD MODFEN MSTR SPEIE SPTIE SPE SPRIE

SPMS : SPI Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Select SPI operation (4-wire method)

#1 : 1

Select clock synchronous operation (3-wire method)

End of enumeration elements list.

TXMD : Communications Operating Mode Select
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Select full-duplex synchronous serial communications

#1 : 1

Select serial communications with transmit-only

End of enumeration elements list.

MODFEN : Mode Fault Error Detection Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable detection of mode fault errors

#1 : 1

Enable detection of mode fault errors

End of enumeration elements list.

MSTR : SPI Master/Slave Mode Select
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Select slave mode

#1 : 1

Select master mode

End of enumeration elements list.

SPEIE : SPI Error Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable SPI error interrupt requests

#1 : 1

Enable SPI error interrupt requests

End of enumeration elements list.

SPTIE : Transmit Buffer Empty Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable transmit buffer empty interrupt requests

#1 : 1

Enable transmit buffer empty interrupt requests

End of enumeration elements list.

SPE : SPI Function Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable SPI function

#1 : 1

Enable SPI function

End of enumeration elements list.

SPRIE : SPI Receive Buffer Full Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable SPI receive buffer full interrupt requests

#1 : 1

Enable SPI receive buffer full interrupt requests

End of enumeration elements list.


SSLP

SPI Slave Select Polarity Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSLP SSLP read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SSL0P SSL1P SSL2P SSL3P

SSL0P : SSLn0 Signal Polarity Setting
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Set SSLn0 signal to active-low

#1 : 1

Set SSLn0 signal to active-high

End of enumeration elements list.

SSL1P : SSLn1 Signal Polarity Setting
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Set SSLn1 signal to active-low

#1 : 1

Set SSLn1 signal to active-high

End of enumeration elements list.

SSL2P : SSLn2 Signal Polarity Setting
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Set SSLn2 signal to active-low

#1 : 1

Set SSLn2 signal to active-high

End of enumeration elements list.

SSL3P : SSLn3 Signal Polarity Setting
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Set SSLn3 signal to active-low

#1 : 1

Set SSLn3 signal to active-high

End of enumeration elements list.


SPCMD0

SPI Command Register 0
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCMD0 SPCMD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPHA CPOL BRDV SSLA SPB LSBF SPNDEN SLNDEN SCKDEN

CPHA : RSPCK Phase Setting
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Select data sampling on leading edge, data change on trailing edge

#1 : 1

Select data change on leading edge, data sampling on trailing edge

End of enumeration elements list.

CPOL : RSPCK Polarity Setting
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Set RSPCK low during idle

#1 : 1

Set RSPCK high during idle

End of enumeration elements list.

BRDV : Bit Rate Division Setting
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : 00

Base bit rate

#01 : 01

Base bit rate divided by 2

#10 : 10

Base bit rate divided by 4

#11 : 11

Base bit rate divided by 8

End of enumeration elements list.

SSLA : SSL Signal Assertion Setting
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#000 : 000

SSL0

#001 : 001

SSL1

#010 : 010

SSL2

#011 : 011

SSL3

: Others

Setting prohibited

End of enumeration elements list.

SPB : SPI Data Length Setting
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

20 bits

0x1 : 0x1

24 bits

0x2 : 0x2

32 bits

0x3 : 0x3

32 bits

0x8 : 0x8

9 bits

0x9 : 0x9

10 bits

0xa : 0xA

11 bits

0xb : 0xB

12 bits

0xc : 0xC

13 bits

0xd : 0xD

14 bits

0xe : 0xE

15 bits

0xf : 0xF

16 bits

: Others

8 bits

End of enumeration elements list.

LSBF : SPI LSB First
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

MSB-first

#1 : 1

LSB-first

End of enumeration elements list.

SPNDEN : SPI Next-Access Delay Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Select next-access delay of 1 RSPCK + 2 PCLKB

#1 : 1

Select next-access delay equal to the setting in the SPI Next-Access Delay Register (SPND)

End of enumeration elements list.

SLNDEN : SSL Negation Delay Setting Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Select SSL negation delay of 1 RSPCK

#1 : 1

Select SSL negation delay equal to the setting in the SPI Slave Select Negation Delay Register (SSLND)

End of enumeration elements list.

SCKDEN : RSPCK Delay Setting Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Select RSPCK delay of 1 RSPCK

#1 : 1

Select RSPCK delay equal to the setting in the SPI Clock Delay Register (SPCKD)

End of enumeration elements list.


SPPCR

SPI Pin Control Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPPCR SPPCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPLP SPLP2 MOIFV MOIFE

SPLP : SPI Loopback
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal mode

#1 : 1

Loopback mode (receive data = inverted transmit data)

End of enumeration elements list.

SPLP2 : SPI Loopback 2
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal mode

#1 : 1

Loopback mode (receive data = transmit data)

End of enumeration elements list.

MOIFV : MOSI Idle Fixed Value
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Set level output on MOSIn pin during MOSI idling to low

#1 : 1

Set level output on MOSIn pin during MOSI idling to high

End of enumeration elements list.

MOIFE : MOSI Idle Value Fixing Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Set MOSI output value to equal final data from previous transfer

#1 : 1

Set MOSI output value to equal value set in the MOIFV bit

End of enumeration elements list.


SPSR

SPI Status Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPSR SPSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVRF IDLNF MODF PERF UDRF SPTEF SPRF

OVRF : Overrun Error Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No overrun error occurred

#1 : 1

Overrun error occurred

End of enumeration elements list.

IDLNF : SPI Idle Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

SPI is in the idle state

#1 : 1

SPI is in the transfer state

End of enumeration elements list.

MODF : Mode Fault Error Flag
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No mode fault or underrun error occurred

#1 : 1

Mode fault error or underrun error occurred

End of enumeration elements list.

PERF : Parity Error Flag
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

No parity error occurred

#1 : 1

Parity error occurred

End of enumeration elements list.

UDRF : Underrun Error Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Mode fault error occurred (MODF = 1)

#1 : 1

Underrun error occurred (MODF = 1)

End of enumeration elements list.

SPTEF : SPI Transmit Buffer Empty Flag
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data is in the transmit buffer

#1 : 1

No data is in the transmit buffer

End of enumeration elements list.

SPRF : SPI Receive Buffer Full Flag
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

No valid data is in SPDR/SPDR_HA

#1 : 1

Valid data is in SPDR/SPDR_HA

End of enumeration elements list.


SPDR

SPI Data Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPDR SPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPDR_HA

SPI Data Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : SPDR
reset_Mask : 0x0

SPDR_HA SPDR_HA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPBR

SPI Bit Rate Register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPBR SPBR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

SPDCR

SPI Data Control Register
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPDCR SPDCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPRDTD SPLW

SPRDTD : SPI Receive/Transmit Data Select
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Read SPDR/SPDR_HA values from receive buffer

#1 : 1

Read SPDR/SPDR_HA values from transmit buffer, but only if the transmit buffer is empty

End of enumeration elements list.

SPLW : SPI Word Access/Halfword Access Specification
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Set SPDR_HA to valid for halfword access

#1 : 1

Set SPDR to valid for word access

End of enumeration elements list.


SPCKD

SPI Clock Delay Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCKD SPCKD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SCKDL

SCKDL : RSPCK Delay Setting
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

1 RSPCK

#001 : 001

2 RSPCK

#010 : 010

3 RSPCK

#011 : 011

4 RSPCK

#100 : 100

5 RSPCK

#101 : 101

6 RSPCK

#110 : 110

7 RSPCK

#111 : 111

8 RSPCK

End of enumeration elements list.


SSLND

SPI Slave Select Negation Delay Register
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSLND SSLND read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLNDL

SLNDL : SSL Negation Delay Setting
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

1 RSPCK

#001 : 001

2 RSPCK

#010 : 010

3 RSPCK

#011 : 011

4 RSPCK

#100 : 100

5 RSPCK

#101 : 101

6 RSPCK

#110 : 110

7 RSPCK

#111 : 111

8 RSPCK

End of enumeration elements list.


SPND

SPI Next-Access Delay Register
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPND SPND read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPNDL

SPNDL : SPI Next-Access Delay Setting
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

1 RSPCK + 2 PCLKB

#001 : 001

2 RSPCK + 2 PCLKB

#010 : 010

3 RSPCK + 2 PCLKB

#011 : 011

4 RSPCK + 2 PCLKB

#100 : 100

5 RSPCK + 2 PCLKB

#101 : 101

6 RSPCK + 2 PCLKB

#110 : 110

7 RSPCK + 2 PCLKB

#111 : 111

8 RSPCK + 2 PCLKB

End of enumeration elements list.


SPCR2

SPI Control Register 2
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCR2 SPCR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPPE SPOE SPIIE PTE SCKASE

SPPE : Parity Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not add parity bit to transmit data and do not check parity bit of receive data

#1 : 1

When SPCR.TXMD = 0: Add parity bit to transmit data and check parity bit of receive data When SPCR.TXMD = 1: Add parity bit to transmit data but do not check parity bit of receive data

End of enumeration elements list.

SPOE : Parity Mode
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Select even parity for transmission and reception

#1 : 1

Select odd parity for transmission and reception

End of enumeration elements list.

SPIIE : SPI Idle Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable idle interrupt requests

#1 : 1

Enable idle interrupt requests

End of enumeration elements list.

PTE : Parity Self-Testing
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable self-diagnosis function of the parity circuit

#1 : 1

Enable self-diagnosis function of the parity circuit

End of enumeration elements list.

SCKASE : RSPCK Auto-Stop Function Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable RSPCK auto-stop function

#1 : 1

Enable RSPCK auto-stop function

End of enumeration elements list.



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