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GPT_OPS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

OPSCR


OPSCR

Output Phase Switching Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPSCR OPSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UF VF WF U V W EN FB P N INV RV ALIGN GRP GODF NFEN NFCS

UF :
bits : 0 - -1 (0 bit)
access : read-write

VF :
bits : 1 - 0 (0 bit)
access : read-write

WF :
bits : 2 - 1 (0 bit)
access : read-write

U : Input U-Phase Monitor
bits : 4 - 3 (0 bit)
access : read-only

V : Input V-Phase Monitor
bits : 5 - 4 (0 bit)
access : read-only

W : Input W-Phase Monitor
bits : 6 - 5 (0 bit)
access : read-only

EN : Enable-Phase Output Control
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not output (Hi-Z external pin)

#1 : 1

Output

End of enumeration elements list.

FB : External Feedback Signal Enable
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : 0

Select the external input

#1 : 1

Select the soft setting (OPSCR.UF, VF, WF)

End of enumeration elements list.

P : Positive-Phase Output (P) Control
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : 0

Level signal output

#1 : 1

PWM signal output (PWM of GPT164)

End of enumeration elements list.

N : Negative-Phase Output (N) Control
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

#0 : 0

Level signal output

#1 : 1

PWM signal output (PWM of GPT164)

End of enumeration elements list.

INV : Invert-Phase Output Control
bits : 19 - 18 (0 bit)
access : read-write

Enumeration:

#0 : 0

Positive logic (active-high) output

#1 : 1

Negative logic (active-low) output

End of enumeration elements list.

RV : Output Phase Rotation Direction Reversal Control
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : 0

Positive rotation

#1 : 1

Reverse rotation

End of enumeration elements list.

ALIGN : Input Phase Alignment
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

#0 : 0

Input phase aligned to PCLKD

#1 : 1

Input phase aligned to PWM

End of enumeration elements list.

GRP : Output Disabled Source Selection
bits : 24 - 24 (1 bit)
access : read-write

GODF : Group Output Disable Function
bits : 26 - 25 (0 bit)
access : read-write

Enumeration:

#0 : 0

This bit function is ignored

#1 : 1

Group disable clears the OPSCR.EN bit

End of enumeration elements list.

NFEN : External Input Noise Filter Enable
bits : 29 - 28 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not use a noise filter on the external input

#1 : 1

Use a noise filter on the external input

End of enumeration elements list.

NFCS : External Input Noise Filter Clock Selection
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKD/1

#01 : 01

PCLKD/4

#10 : 10

PCLKD/16

#11 : 11

PCLKD/64

End of enumeration elements list.



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