\n
address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
CTSU Control Register A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRT : CTSU Measurement Operation Start
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stop measurement operation
#1 : 1
Start measurement operation
End of enumeration elements list.
CAP : CTSU Measurement Operation Start Trigger Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Software trigger
#1 : 1
External trigger
End of enumeration elements list.
SNZ : CTSU Wait State Power-Saving Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable power-saving function during wait state
#1 : 1
Enable power-saving function during wait state
End of enumeration elements list.
CFCON : CTSU CFC Power on Control
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
CFC power off
#1 : 1
CFC power on
End of enumeration elements list.
INIT : CTSU Control Block Initialization
bits : 4 - 3 (0 bit)
access : write-only
PUMPON : CTSU Boost Circuit Control
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Boost circuit off
#1 : 1
Boost circuit on
End of enumeration elements list.
TXVSEL : CTSU Transmission Power Supply Selection
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
VCC is selected as the power supply for the transmit pins in measurement methods other than self-capacitance method.
#01 : 01
VCC is selected as the power supply for the transmit pins in self-capacitance method.
#10 : 10
VCL is selected as the power-supply voltage for the transmit pins.
#11 : 11
Setting prohibited
End of enumeration elements list.
PON : CTSU Power Supply Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Power off the CTSU
#1 : 1
Power on the CTSU
End of enumeration elements list.
CSW : CTSU LPF Capacitance Charging Control
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Turn off capacitance switch
#1 : 1
Turn on capacitance switch
End of enumeration elements list.
ATUNE0 : CTSU Power Supply Operating Mode Setting
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
VCC ≥ 2.4 V: Normal operating mode VCC < 2.4 V: Setting prohibited
#1 : 1
Low-voltage operating mode
End of enumeration elements list.
ATUNE1 : CTSU Current Range Adjustment
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
40 µA when CTSUATUNE2 = 0 20 µA when CTSUATUNE2 = 1
#1 : 1
80 µA when CTSUATUNE2 = 0 160 µA when CTSUATUNE2 = 1
End of enumeration elements list.
CLK : CTSU Operating Clock Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/2 (PCLKB divided by 2)
#10 : 10
PCLKB/4 (PCLKB divided by 4)
#11 : 11
PCLKB/8 (PCLKB divided by 8)
End of enumeration elements list.
MD0 : CTSU Measurement Mode Select 0
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Single scan mode
#1 : 1
Multi-scan mode
End of enumeration elements list.
MD1 : CTSU Measurement Mode Select 1
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Self-capacitance
#1 : 1
Mutual capacitance
End of enumeration elements list.
MD2 : CTSU Measurement Mode Select 2
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Measure the current that flows through the switched capacitor.
#1 : 1
Measure the transfer charge in CFC circuit (high speed measurement)
End of enumeration elements list.
ATUNE2 : CTSU Current Range Adjustment
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
40 µA when CTSUATUNE1 = 0 80 µA when CTSUATUNE2 = 1
#1 : 1
20 µA when CTSUATUNE1 = 0 160 µA when CTSUATUNE2 = 1
End of enumeration elements list.
LOAD : CTSU Measurement Load Control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#00 : 00
Normal measurement mode
#01 : 01
Load off mode
#10 : 10
Current load mode
#11 : 11
Resistance load mode
End of enumeration elements list.
POSEL : CTSU Non-measured Channel Output Select
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#00 : 00
Output low through GPIO
#01 : 01
Hi-Z
#10 : 10
Output low through the power setting in the TXVSEL[1:0] bits
#11 : 11
Same phase pulse output as transmission channel through the power setting in the TXVSEL[1:0] bits
End of enumeration elements list.
SDPSEL : CTSU Sensor Drive Pulse Select
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
Random pulse mode
#1 : 1
High resolution pulse mode
End of enumeration elements list.
FCMODE : CTSU SUCLK Control
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
SUCLK is used as frequency diffusion clock
#1 : 1
SUCLK is used as recovery clock for multi-clock measurement
End of enumeration elements list.
STCLK : CTSU STCLK Select
bits : 24 - 28 (5 bit)
access : read-write
DCMODE : CTSU Current Measurement Mode Select
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal mode
#1 : 1
Current measurement mode
End of enumeration elements list.
DCBACK : CTSU Current Measurement Feedback Select
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
TSCAP pin is selected
#1 : 1
Measurement pin is selected
End of enumeration elements list.
CTSU Control Register A
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCRA
reset_Mask : 0x0
CTSU Control Register A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCRA
reset_Mask : 0x0
CTSU Control Register A
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCRA
reset_Mask : 0x0
CTSU Channel Enable Control Register B
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHAC32 : CTSU Channel Enable Control B
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC33 : CTSU Channel Enable Control B
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC34 : CTSU Channel Enable Control B
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CTSU Channel Enable Control Register B
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCHACB
reset_Mask : 0x0
CTSU Channel Enable Control Register B
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCHACB
reset_Mask : 0x0
CTSU Channel Transmit/Receive Control Register A
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHTRC00 : CTSU Channel Transmit/Receive Control A
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC02 : CTSU Channel Transmit/Receive Control A
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC04 : CTSU Channel Transmit/Receive Control A
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC05 : CTSU Channel Transmit/Receive Control A
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC06 : CTSU Channel Transmit/Receive Control A
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC07 : CTSU Channel Transmit/Receive Control A
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC08 : CTSU Channel Transmit/Receive Control A
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC09 : CTSU Channel Transmit/Receive Control A
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC10 : CTSU Channel Transmit/Receive Control A
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC11 : CTSU Channel Transmit/Receive Control A
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC12 : CTSU Channel Transmit/Receive Control A
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC13 : CTSU Channel Transmit/Receive Control A
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC14 : CTSU Channel Transmit/Receive Control A
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC15 : CTSU Channel Transmit/Receive Control A
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC16 : CTSU Channel Transmit/Receive Control A
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC17 : CTSU Channel Transmit/Receive Control A
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC18 : CTSU Channel Transmit/Receive Control A
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC21 : CTSU Channel Transmit/Receive Control A
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC22 : CTSU Channel Transmit/Receive Control A
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC23 : CTSU Channel Transmit/Receive Control A
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC24 : CTSU Channel Transmit/Receive Control A
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC25 : CTSU Channel Transmit/Receive Control A
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC26 : CTSU Channel Transmit/Receive Control A
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC27 : CTSU Channel Transmit/Receive Control A
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC28 : CTSU Channel Transmit/Receive Control A
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC30 : CTSU Channel Transmit/Receive Control A
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC31 : CTSU Channel Transmit/Receive Control A
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CTSU Channel Transmit/Receive Control Register A
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCHTRCA
reset_Mask : 0x0
CTSU Channel Transmit/Receive Control Register A
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCHTRCA
reset_Mask : 0x0
CTSU Channel Transmit/Receive Control Register A
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCHTRCA
reset_Mask : 0x0
CTSU Channel Transmit/Receive Control Register A
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCHTRCA
reset_Mask : 0x0
CTSU Channel Transmit/Receive Control Register A
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCHTRCAH
reset_Mask : 0x0
CTSU Channel Transmit/Receive Control Register A
address_offset : 0x17 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCHTRCA
reset_Mask : 0x0
CTSU Channel Transmit/Receive Control Register B
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHTRC32 : CTSU Channel Transmit/Receive Control B
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC33 : CTSU Channel Transmit/Receive Control B
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CHTRC34 : CTSU Channel Transmit/Receive Control B
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reception
#1 : 1
Transmission
End of enumeration elements list.
CTSU Channel Transmit/Receive Control Register B
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCHTRCB
reset_Mask : 0x0
CTSU Channel Transmit/Receive Control Register B
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCHTRCB
reset_Mask : 0x0
CTSU Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFC : CTSU Multi-clock Counter
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Multi-clock 0
#01 : 01
Multi-clock 1
#10 : 10
Multi-clock 2
#11 : 11
Multi-clock 3
End of enumeration elements list.
ICOMPRST : CTSU CTSUICOMP1 Flag Reset
bits : 5 - 4 (0 bit)
access : write-only
ICOMP1 : CTSU Sense Current Error Monitor
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
Normal sensor current
#1 : 1
Abnormal sensor current
End of enumeration elements list.
ICOMP0 : TSCAP Voltage Error Monitor
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
Normal TSCAP voltage
#1 : 1
Abnormal TSCAP voltage
End of enumeration elements list.
STC : CTSU Measurement Status Counter
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
#000 : 000
Status 0
#001 : 001
Status 1
#010 : 010
Status 2
#011 : 011
Status 3
#100 : 100
Status 4
#101 : 101
Status 5
End of enumeration elements list.
DTSR : CTSU Data Transfer Status Flag
bits : 12 - 11 (0 bit)
access : read-only
Enumeration:
#0 : 0
Read
#1 : 1
Not read
End of enumeration elements list.
SENSOVF : CTSU Sensor Counter Overflow Flag
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
No overflow occurred
#1 : 1
Overflow occurred
End of enumeration elements list.
PS : CTSU Mutual Capacitance Status Flag
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
First measurement
#1 : 1
Second measurement
End of enumeration elements list.
CFCRDCH : CTSU CFC Read Channel Select
bits : 16 - 20 (5 bit)
access : read-write
Enumeration:
0x00 : 0x00
TS00
0x02 : 0x02
TS02 (CFC)
0x04 : 0x04
TS04
0x05 : 0x05
TS05
0x06 : 0x06
TS06
0x07 : 0x07
TS07
0x08 : 0x08
TS08 (CFC)
0x09 : 0x09
TS09 (CFC)
0x0a : 0x0A
TS10 (CFC)
0x0b : 0x0B
TS11 (CFC)
0x0c : 0x0C
TS12 (CFC)
0x0d : 0x0D
TS13 (CFC)
0x0e : 0x0E
TS14 (CFC)
0x0f : 0x0F
TS15 (CFC)
0x10 : 0x10
TS16 (CFC)
0x11 : 0x11
TS17
0x12 : 0x12
TS18
0x15 : 0x15
TS21
0x16 : 0x16
TS22
0x17 : 0x17
TS23
0x18 : 0x18
TS24
0x19 : 0x19
TS25
0x1a : 0x1A
TS26 (CFC)
0x1b : 0x1B
TS27 (CFC)
0x1c : 0x1C
TS28 (CFC)
0x1e : 0x1E
TS30 (CFC)
0x1f : 0x1F
TS31 (CFC)
0x20 : 0x20
TS32 (CFC)
0x21 : 0x21
TS33 (CFC)
0x22 : 0x22
TS34 (CFC)
End of enumeration elements list.
CTSU Status Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUSR
reset_Mask : 0x0
CTSU Status Register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUSR
reset_Mask : 0x0
CTSU Status Register
address_offset : 0x1D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUSR
reset_Mask : 0x0
CTSU Status Register
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUSR
reset_Mask : 0x0
CTSU Status Register
address_offset : 0x1E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUSRH
reset_Mask : 0x0
CTSU Control Register A
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCRA
reset_Mask : 0x0
CTSU Control Register A
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCRAH
reset_Mask : 0x0
CTSU Sensor Offset Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SO : CTSU Sensor Offset Adjustment
bits : 0 - 8 (9 bit)
access : read-write
SNUM : CTSU Measurement Count Setting
bits : 10 - 16 (7 bit)
access : read-write
SSDIV : CTSU Spectrum Diffusion Frequency Division Setting
bits : 20 - 22 (3 bit)
access : read-write
SDPA : CTSU Base Clock Setting
bits : 24 - 30 (7 bit)
access : read-write
CTSU Sensor Offset Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUSO
reset_Mask : 0x0
CTSU Sensor Offset Register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUSO
reset_Mask : 0x0
CTSU Sensor Counter Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SENSCNT : CTSU Sensor Counter
bits : 0 - 14 (15 bit)
access : read-only
CTSU Sensor Counter Register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : CTSUSCNT
reset_Mask : 0x0
CTSU Calibration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSOD : CTSU TS Pins Fixed Output Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Electrostatic capacitance measurement mode
#1 : 1
TS pins fix output (High output/Low output).
End of enumeration elements list.
DRV : CTSU Calibration Setting Bit 1
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Electrostatic capacitance measurement mode
#1 : 1
Calibration setting 1
End of enumeration elements list.
SUCLKEN : CTSU SUCLK Enable Control
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
SUCLK operation is disabled.
#1 : 1
SUCLK operation is enabled.
End of enumeration elements list.
TSOC : CTSU Calibration Setting Bit 2
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Electrostatic capacitance measurement mode
#1 : 1
Calibration setting 2
End of enumeration elements list.
IOC : CTSU Transfer Pins Control
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Low level
#1 : 1
High level
End of enumeration elements list.
CFCRDMD : CTSU CFC Counter Read Mode Select
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Read by DTC
#1 : 1
Read by CPU
End of enumeration elements list.
DCOFF : CTSU Down Converter Control
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation mode
#1 : 1
The down converter is off.
End of enumeration elements list.
CFCMODE : CTSU CFC Current Source Switching
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
CFC current measurement (normal mode)
#1 : 1
External current measurement for calibration
End of enumeration elements list.
DACCARRY : CTSU DAC Upper Current Source Carry Control
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not carry
#1 : 1
Carry
End of enumeration elements list.
SUCARRY : CTSU CCO Carry Control
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not carry
#1 : 1
Carry
End of enumeration elements list.
DACCLK : CTSU DAC Modulation Circuit Clock Select
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
Divided PCLK specified by CTSUCRA.CLK[1:0] bits
#1 : 1
SUCLK
End of enumeration elements list.
CCOCLK : CTSU CCO Modulation Circuit Clock Select
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Divided PCLK specified by CTSUCRA.CLK[1:0] bits
#1 : 1
SUCLK
End of enumeration elements list.
CCOCALIB : CTSU CCO Calibration Mode Select
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal mode
#1 : 1
Oscillator calibration mode
End of enumeration elements list.
CTSU Calibration Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCALIB
reset_Mask : 0x0
CTSU Calibration Register
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCALIB
reset_Mask : 0x0
CTSU Sensor Unit Clock Control Register A
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTSU Sensor Unit Clock Control Register A
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUSUCLKA
reset_Mask : 0x0
CTSU Sensor Unit Clock Control Register A
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUSUCLKA
reset_Mask : 0x0
CTSU Control Register A
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCRA
reset_Mask : 0x0
CTSU Sensor Unit Clock Control Register B
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUADJ2 : CTSU SUCLK Frequency Adjustment
bits : 0 - 6 (7 bit)
access : read-write
SUMULTI2 : CTSU SUCLK Multiplier Rate Setting
bits : 8 - 14 (7 bit)
access : read-write
SUADJ3 : CTSU SUCLK Frequency Adjustment
bits : 16 - 22 (7 bit)
access : read-write
SUMULTI3 : CTSU SUCLK Multiplier Rate Setting
bits : 24 - 30 (7 bit)
access : read-write
CTSU Sensor Unit Clock Control Register B
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUSUCLKB
reset_Mask : 0x0
CTSU Sensor Unit Clock Control Register B
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUSUCLKB
reset_Mask : 0x0
CTSU CFC Counter Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFCCNT : CTSU CFC Counter
bits : 0 - 14 (15 bit)
access : read-only
CTSU CFC Counter Register
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : CTSUCFCCNT
reset_Mask : 0x0
CTSU Control Register B
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRRATIO : CTSU Measurement Time and Pulse Count Adjustment
bits : 0 - 2 (3 bit)
access : read-write
PRMODE : CTSU Base Period and Pulse Count Setting
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
510 pulses (512 pulses when PROFF bit is 1)
#01 : 01
126 pulses (128 pulses when PROFF bit is 1)
#10 : 10
62 pulses (recommended setting) (64 pulses when PROFF bit is 1)
#11 : 11
Setting prohibited
End of enumeration elements list.
SOFF : CTSU High-Pass Noise Reduction Function Off Setting
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Turn spectrum diffusion on.
#1 : 1
Turn spectrum diffusion off.
End of enumeration elements list.
PROFF : CTSU Random Number Off Control
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
There is random number control.
#1 : 1
There is no random number control.
End of enumeration elements list.
SST : CTSU Sensor Stabilization Wait Control
bits : 8 - 14 (7 bit)
access : read-write
SSMOD : CTSU SUCLK Diffusion Mode Select
bits : 24 - 25 (2 bit)
access : read-write
SSCNT : CTSU SUCLK Diffusion Control
bits : 28 - 28 (1 bit)
access : read-write
CTSU Control Register B
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCRB
reset_Mask : 0x0
CTSU Control Register B
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCRB
reset_Mask : 0x0
CTSU Control Register B
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCRB
reset_Mask : 0x0
CTSU Control Register B
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCRB
reset_Mask : 0x0
CTSU Control Register B
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCRB
reset_Mask : 0x0
CTSU Measurement Channel Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCH0 : CTSU Measurement Channel 0
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0x00 : 0x00
TS00
0x02 : 0x02
TS02
0x04 : 0x04
TS04
0x05 : 0x05
TS05
0x06 : 0x06
TS06
0x07 : 0x07
TS07
0x08 : 0x08
TS08
0x09 : 0x09
TS09
0x0a : 0x0A
TS10
0x0b : 0x0B
TS11
0x0c : 0x0C
TS12
0x0d : 0x0D
TS13
0x0e : 0x0E
TS14
0x0f : 0x0F
TS15
0x10 : 0x10
TS16
0x11 : 0x11
TS17
0x12 : 0x12
TS18
0x15 : 0x15
TS21
0x16 : 0x16
TS22
0x17 : 0x17
TS23
0x18 : 0x18
TS24
0x19 : 0x19
TS25
0x1a : 0x1A
TS26
0x1b : 0x1B
TS27
0x1c : 0x1C
TS28
0x1e : 0x1E
TS30
0x1f : 0x1F
TS31
0x20 : 0x20
TS32
0x21 : 0x21
TS33
0x22 : 0x22
TS34
0x3f : 0x3F
Measurement is being stopped.
End of enumeration elements list.
MCH1 : CTSU Measurement Channel 1
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0x00 : 0x00
TS00
0x02 : 0x02
TS02
0x04 : 0x04
TS04
0x05 : 0x05
TS05
0x06 : 0x06
TS06
0x07 : 0x07
TS07
0x08 : 0x08
TS08
0x09 : 0x09
TS09
0x0a : 0x0A
TS10
0x0b : 0x0B
TS11
0x0c : 0x0C
TS12
0x0d : 0x0D
TS13
0x0e : 0x0E
TS14
0x0f : 0x0F
TS15
0x10 : 0x10
TS16
0x11 : 0x11
TS17
0x12 : 0x12
TS18
0x15 : 0x15
TS21
0x16 : 0x16
TS22
0x17 : 0x17
TS23
0x18 : 0x18
TS24
0x19 : 0x19
TS25
0x1a : 0x1A
TS26
0x1b : 0x1B
TS27
0x1c : 0x1C
TS28
0x1e : 0x1E
TS30
0x1f : 0x1F
TS31
0x20 : 0x20
TS32
0x21 : 0x21
TS33
0x22 : 0x22
TS34
0x3f : 0x3F
Measurement is being stopped.
End of enumeration elements list.
MCA0 : CTSU Multiple Valid Clock Control
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Valid
#1 : 1
Invalid
End of enumeration elements list.
MCA1 : CTSU Multiple Valid Clock Control
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Valid
#1 : 1
Invalid
End of enumeration elements list.
MCA2 : CTSU Multiple Valid Clock Control
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Valid
#1 : 1
Invalid
End of enumeration elements list.
MCA3 : CTSU Multiple Valid Clock Control
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Valid
#1 : 1
Invalid
End of enumeration elements list.
CTSU Measurement Channel Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUMCH
reset_Mask : 0x0
CTSU Measurement Channel Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUMCH
reset_Mask : 0x0
CTSU Measurement Channel Register
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUMCH
reset_Mask : 0x0
CTSU Measurement Channel Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUMCH
reset_Mask : 0x0
CTSU Measurement Channel Register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUMCHH
reset_Mask : 0x0
CTSU Channel Enable Control Register A
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHAC00 : CTSU Channel Enable Control A
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC02 : CTSU Channel Enable Control A
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC04 : CTSU Channel Enable Control A
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC05 : CTSU Channel Enable Control A
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC06 : CTSU Channel Enable Control A
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC07 : CTSU Channel Enable Control A
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC08 : CTSU Channel Enable Control A
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC09 : CTSU Channel Enable Control A
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC10 : CTSU Channel Enable Control A
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC11 : CTSU Channel Enable Control A
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC12 : CTSU Channel Enable Control A
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC13 : CTSU Channel Enable Control A
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC14 : CTSU Channel Enable Control A
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC15 : CTSU Channel Enable Control A
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC16 : CTSU Channel Enable Control A
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC17 : CTSU Channel Enable Control A
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC18 : CTSU Channel Enable Control A
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC21 : CTSU Channel Enable Control A
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC22 : CTSU Channel Enable Control A
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC23 : CTSU Channel Enable Control A
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC24 : CTSU Channel Enable Control A
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC25 : CTSU Channel Enable Control A
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC26 : CTSU Channel Enable Control A
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC27 : CTSU Channel Enable Control A
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC28 : CTSU Channel Enable Control A
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC30 : CTSU Channel Enable Control A
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CHAC31 : CTSU Channel Enable Control A
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not measure.
#1 : 1
Measure.
End of enumeration elements list.
CTSU Channel Enable Control Register A
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCHACA
reset_Mask : 0x0
CTSU Channel Enable Control Register A
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCHACA
reset_Mask : 0x0
CTSU Channel Enable Control Register A
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCHACA
reset_Mask : 0x0
CTSU Channel Enable Control Register A
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCHACA
reset_Mask : 0x0
CTSU Channel Enable Control Register A
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCHACAH
reset_Mask : 0x0
CTSU Channel Enable Control Register A
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CTSUCHACA
reset_Mask : 0x0
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.