\n

FLCN

Peripheral Memory Blocks

address_offset : 0x90 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x104 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x108 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x110 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x114 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x118 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x120 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x124 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x12C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x130 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x138 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x180 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x184 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x188 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x190 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1C0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1C8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1D0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1D8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1DC Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1E0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1E8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1F0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3A4 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3FB0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3FC4 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3FC8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

Registers

FPMCR

FASR

FSARL

FSARH

FCR

FEARL

FEARH

FRESETR

FSTATR1

FWBL0

FWBH0

FPR

FPSR

FRBL0

FRBH0

FSCMR

FAWSMR

FAWEMR

FISR

FEXCR

FEAML

FEAMH

FSTATR2

CTSUTRIMA

CTSUTRIMB

FENTRYR

FLDWAITR

PFBER

DFLCTL


FPMCR

Flash P/E Mode Control Register
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPMCR FPMCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FMS0 RPDIS FMS1

FMS0 : Flash Operating Mode Select 0
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

FMS1 = 0: Read mode FMS1 = 1: Data flash P/E mode.

#1 : 1

FMS1 = 0: Code flash P/E mode FMS1 = 1: Setting prohibited.

End of enumeration elements list.

RPDIS : Code Flash P/E Disable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Programming of the code flash is enabled

#1 : 1

Programming of the code flash is disabled.

End of enumeration elements list.

FMS1 : Flash Operating Mode Select 1
bits : 4 - 3 (0 bit)
access : read-write


FASR

Flash Area Select Register
address_offset : 0x104 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FASR FASR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EXS

EXS : Extra Area Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

User area or data area

#1 : 1

Extra area.

End of enumeration elements list.


FSARL

Flash Processing Start Address Register L
address_offset : 0x108 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSARL FSARL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSARL

FSARL : Flash Processing Start Address L
bits : 0 - 14 (15 bit)
access : read-write


FSARH

Flash Processing Start Address Register H
address_offset : 0x110 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSARH FSARH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSARH

FSARH : Flash Processing Start Address H
bits : 0 - 14 (15 bit)
access : read-write


FCR

Flash Control Register
address_offset : 0x114 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCR FCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD DRC STOP OPST

CMD : Software Command Setting
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x1 : 0x1

Program

0x3 : 0x3

Blank check (code flash)

0x4 : 0x4

Block erase

0x5 : 0x5

Consecutive read

0x6 : 0x6

Chip erase

0xb : 0xB

Blank check (data flash)

: Others

Setting prohibited.

End of enumeration elements list.

DRC : Data Read Completion
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data is not read or next data is requested

#1 : 1

Data reading is complete.

End of enumeration elements list.

STOP : Forced Processing Stop
bits : 6 - 5 (0 bit)
access : read-write

OPST : Processing Start
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Processing stops

#1 : 1

Processing starts.

End of enumeration elements list.


FEARL

Flash Processing End Address Register L
address_offset : 0x118 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEARL FEARL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEARL

FEARL : Flash Processing End Address L
bits : 0 - 14 (15 bit)
access : read-write


FEARH

Flash Processing End Address Register H
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEARH FEARH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEARH

FEARH : Flash Processing End Address H
bits : 0 - 14 (15 bit)
access : read-write


FRESETR

Flash Reset Register
address_offset : 0x124 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRESETR FRESETR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FRESET

FRESET : Software reset of the registers
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The registers related to the flash programming are not reset

#1 : 1

The registers related to the flash programming are reset.

End of enumeration elements list.


FSTATR1

Flash Status Register 1
address_offset : 0x12C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FSTATR1 FSTATR1 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DRRDY FRDY EXRDY

DRRDY : Data Read Ready Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

The read processing of the consecutive read command at each address is not terminated.

#1 : 1

The read processing of the consecutive read command at each address is terminated and read data is stored to the FRBH and FRBL registers.

End of enumeration elements list.

FRDY : Flash Ready Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

The software command of the FCR register is not terminated.

#1 : 1

The software command of the FCR register is terminated.

End of enumeration elements list.

EXRDY : Extra Area Ready Flag
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

The software command of the FEXCR register is not terminated.

#1 : 1

The software command of the FEXCR register is terminated.

End of enumeration elements list.


FWBL0

Flash Write Buffer Register L0
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FWBL0 FWBL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : Flash Write Buffer L0
bits : 0 - 14 (15 bit)
access : read-write


FWBH0

Flash Write Buffer Register H0
address_offset : 0x138 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FWBH0 FWBH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : Flash Write Buffer H0
bits : 0 - 14 (15 bit)
access : read-write


FPR

Protection Unlock Register
address_offset : 0x180 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPR FPR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FPR

FPR : Protection Unlock
bits : 0 - 6 (7 bit)
access : read-write


FPSR

Protection Unlock Status Register
address_offset : 0x184 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FPSR FPSR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PERR

PERR : Protect Error Flag
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error

#1 : 1

An error occurs

End of enumeration elements list.


FRBL0

Flash Read Buffer Register L0
address_offset : 0x188 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FRBL0 FRBL0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA

RDATA : Flash Read Buffer L0
bits : 0 - 14 (15 bit)
access : read-only


FRBH0

Flash Read Buffer Register H0
address_offset : 0x190 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FRBH0 FRBH0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA

RDATA : Flash Read Buffer H0
bits : 0 - 14 (15 bit)
access : read-only


FSCMR

Flash Start-Up Setting Monitor Register
address_offset : 0x1C0 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FSCMR FSCMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASMF FSPR

SASMF : Startup Area Setting Monitor Flag
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : 0

Setting to start up using the alternative area

#1 : 1

Setting to start up using the default area

End of enumeration elements list.

FSPR : Access Window Protection Flag
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : 0

Access window setting disabled.

#1 : 1

Access window setting enabled.

End of enumeration elements list.


FAWSMR

Flash Access Window Start Address Monitor Register
address_offset : 0x1C8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FAWSMR FAWSMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAWS FSPR

FAWS : Access Window Start Address
bits : 0 - 9 (10 bit)
access : read-only

FSPR : Access Window Protection Flag
bits : 15 - 14 (0 bit)
access : read-only


FAWEMR

Flash Access Window End Address Monitor Register
address_offset : 0x1D0 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FAWEMR FAWEMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAWE SASMF

FAWE : Access Window End Address
bits : 0 - 9 (10 bit)
access : read-only

SASMF : Startup Area Setting Monitor Flag
bits : 15 - 14 (0 bit)
access : read-only


FISR

Flash Initial Setting Register
address_offset : 0x1D8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FISR FISR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PCKA SAS

PCKA : Flash-IF Clock Notification
bits : 0 - 4 (5 bit)
access : read-write

SAS : Startup Area Select
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#10 : 10

The startup area is switched to the default area temporarily

#11 : 11

The startup area is switched to the alternate area temporarily.

: Others

The startup area is selected according to the settings of the extra area.

End of enumeration elements list.


FEXCR

Flash Extra Area Control Register
address_offset : 0x1DC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEXCR FEXCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD OPST

CMD : Software Command Setting
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#010 : 010

Access window information program Startup area selection and security setting

#011 : 011

OCDID1 program

#100 : 100

OCDID2 program

#101 : 101

OCDID3 program

#110 : 110

OCDID4 program

: Others

Setting prohibited.

End of enumeration elements list.

OPST : Processing Start
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Processing stops

#1 : 1

Processing starts.

End of enumeration elements list.


FEAML

Flash Error Address Monitor Register L
address_offset : 0x1E0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEAML FEAML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEAML

FEAML : Flash Error Address Monitor Register L
bits : 0 - 14 (15 bit)
access : read-write


FEAMH

Flash Error Address Monitor Register H
address_offset : 0x1E8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FEAMH FEAMH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEAMH

FEAMH : Flash Error Address Monitor Register H
bits : 0 - 14 (15 bit)
access : read-write


FSTATR2

Flash Status Register 2
address_offset : 0x1F0 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FSTATR2 FSTATR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERERR PRGERR PRGERR01 BCERR ILGLERR EILGLERR

ERERR : Erase Error Flag
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Erasure terminates normally

#1 : 1

An error occurs during erasure

End of enumeration elements list.

PRGERR : Program Error Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Programming terminates normally

#1 : 1

An error occurs during programming.

End of enumeration elements list.

PRGERR01 : Program Error Flag 01
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Programming by the FEXCR register terminates normally

#1 : 1

An error occurs during programming.

End of enumeration elements list.

BCERR : Blank Check Error Flag
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

Blank checking terminates normally

#1 : 1

An error occurs during blank checking.

End of enumeration elements list.

ILGLERR : Illegal Command Error Flag
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

No illegal software command or illegal access is detected

#1 : 1

An illegal command or illegal access is detected.

End of enumeration elements list.

EILGLERR : Extra Area Illegal Command Error Flag
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

No illegal command or illegal access to the extra area is detected

#1 : 1

An illegal command or illegal access to the extra area is detected.

End of enumeration elements list.


CTSUTRIMA

CTSU Trimming Register A
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUTRIMA CTSUTRIMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTRIM DACTRIM SUADJD SUADJTRIM

RTRIM : CTSU Reference Resistance Adjustment
bits : 0 - 6 (7 bit)
access : read-write

DACTRIM : Linearity Adjustment of Offset Current
bits : 8 - 14 (7 bit)
access : read-write

SUADJD : CTSU SUCLK Frequency Adjustment
bits : 16 - 22 (7 bit)
access : read-write

SUADJTRIM : CTSU Current DAC Matching Coefficient Adjustment 2
bits : 24 - 30 (7 bit)
access : read-write


CTSUTRIMB

CTSU Trimming Register B
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUTRIMB CTSUTRIMB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRESULT0 TRESULT1 TRESULT2 TRESULT3

TRESULT0 : The coefficient of variation for the 7.5 kΩ reference load resistance is stored.
bits : 0 - 6 (7 bit)
access : read-write

TRESULT1 : The coefficient of variation for the 15 kΩ reference load resistance is stored.
bits : 8 - 14 (7 bit)
access : read-write

TRESULT2 : The coefficient of variation for the 30 kΩ reference load resistance is stored.
bits : 16 - 22 (7 bit)
access : read-write

TRESULT3 : The coefficient of variation for the 60 kΩ reference load resistance is stored.
bits : 24 - 30 (7 bit)
access : read-write


FENTRYR

Flash P/E Mode Entry Register
address_offset : 0x3FB0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FENTRYR FENTRYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FENTRY0 FENTRYD FEKEY

FENTRY0 : Code Flash P/E Mode Entry 0
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The code flash is the read mode

#1 : 1

The code flash is the P/E mode.

End of enumeration elements list.

FENTRYD : Data Flash P/E Mode Entry
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

The data flash is the read mode

#1 : 1

The data flash is the P/E mode.

End of enumeration elements list.

FEKEY : Key Code
bits : 8 - 14 (7 bit)
access : write-only


FLDWAITR

Memory Wait Cycle Control Register for Data Flash
address_offset : 0x3FC4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLDWAITR FLDWAITR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FLDWAIT1

FLDWAIT1 : Memory Wait Cycle Select for Data Flash
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

1 wait access (Default)

#1 : 1

2 wait access

End of enumeration elements list.


PFBER

Prefetch Buffer Enable Register
address_offset : 0x3FC8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFBER PFBER read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PFBE

PFBE : Prefetch Buffer Enable bit
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Prefetch buffer is disabled

#1 : 1

Prefetch buffer is enabled

End of enumeration elements list.


DFLCTL

Data Flash Control Register
address_offset : 0x90 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFLCTL DFLCTL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DFLEN

DFLEN : Data Flash Access Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Access to the data flash is disabled

#1 : 1

Access to the data flash is enabled

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.