\n
address_offset : 0x1100 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1104 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1110 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1120 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1130 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1134 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1140 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1800 Bytes (0x0)
size : 0x34 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1900 Bytes (0x0)
size : 0x34 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1A00 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection : not protected
Slave Bus Control Register
address_offset : 0x1100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBS : Arbitration Select for two masters
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
DMAC/DTC > CPU
#01 : 01
DMAC/DTC ↔ CPU
#10 : 10
Setting prohibited
#11 : 11
Setting prohibited
End of enumeration elements list.
Slave Bus Control Register
address_offset : 0x1104 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBS : Arbitration Select for two masters
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
DMAC/DTC > CPU
#01 : 01
DMAC/DTC ↔ CPU
#10 : 10
Setting prohibited
#11 : 11
Setting prohibited
End of enumeration elements list.
Slave Bus Control Register
address_offset : 0x1110 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBS : Arbitration Select for two masters
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
DMAC/DTC > CPU
#01 : 01
DMAC/DTC ↔ CPU
#10 : 10
Setting prohibited
#11 : 11
Setting prohibited
End of enumeration elements list.
Slave Bus Control Register
address_offset : 0x1120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBS : Arbitration Select for two masters
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMAC/DTC > CPU
#1 : 1
DMAC/DTC ↔ CPU
End of enumeration elements list.
Slave Bus Control Register
address_offset : 0x1130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBS : Arbitration Select for two masters
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMAC/DTC > CPU
#1 : 1
DMAC/DTC ↔ CPU
End of enumeration elements list.
Slave Bus Control Register
address_offset : 0x1134 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBS : Arbitration Select for two masters
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMAC/DTC > CPU
#1 : 1
DMAC/DTC ↔ CPU
End of enumeration elements list.
Slave Bus Control Register
address_offset : 0x1140 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBS : Arbitration Select for two masters
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
DMAC/DTC > CPU
#01 : 01
DMAC/DTC ↔ CPU
#10 : 10
Setting prohibited
#11 : 11
Setting prohibited
End of enumeration elements list.
BUS Error Address Register
address_offset : 0x1800 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BERAD : Bus Error Address
bits : 0 - 30 (31 bit)
access : read-only
BUS Error Read Write Register
address_offset : 0x1804 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RWSTAT : Error Access Read/Write Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Read access
#1 : 1
Write access
End of enumeration elements list.
BUS Error Address Register
address_offset : 0x1810 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BERAD : Bus Error Address
bits : 0 - 30 (31 bit)
access : read-only
BUS Error Read Write Register
address_offset : 0x1814 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RWSTAT : Error Access Read/Write Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Read access
#1 : 1
Write access
End of enumeration elements list.
BUS Error Address Register
address_offset : 0x1820 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BERAD : Bus Error Address
bits : 0 - 30 (31 bit)
access : read-only
BUS Error Read Write Register
address_offset : 0x1824 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RWSTAT : Error Access Read/Write Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Read access
#1 : 1
Write access
End of enumeration elements list.
BUS TZF Error Address Register
address_offset : 0x1900 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BTZFERAD : Bus TrustZone Filter Error Address
bits : 0 - 30 (31 bit)
access : read-only
BUS TZF Error Read Write Register
address_offset : 0x1904 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRWSTAT : TrustZone filter error access Read/Write Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Read access
#1 : 1
Write access
End of enumeration elements list.
BUS TZF Error Address Register
address_offset : 0x1910 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BTZFERAD : Bus TrustZone Filter Error Address
bits : 0 - 30 (31 bit)
access : read-only
BUS TZF Error Read Write Register
address_offset : 0x1914 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRWSTAT : TrustZone filter error access Read/Write Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Read access
#1 : 1
Write access
End of enumeration elements list.
BUS TZF Error Address Register
address_offset : 0x1920 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BTZFERAD : Bus TrustZone Filter Error Address
bits : 0 - 30 (31 bit)
access : read-only
BUS TZF Error Read Write Register
address_offset : 0x1924 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRWSTAT : TrustZone filter error access Read/Write Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Read access
#1 : 1
Write access
End of enumeration elements list.
BUS Error Status Register %s
address_offset : 0x1A00 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SLERRSTAT : Slave bus Error Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No error occurred
#1 : 1
Error occurred
End of enumeration elements list.
STERRSTAT : Slave TrustZone filter Error Status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
No error occurred
#1 : 1
Error occurred
End of enumeration elements list.
MMERRSTAT : Master MPU Error Status
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
No error occurred
#1 : 1
Error occurred
End of enumeration elements list.
ILERRSTAT : Illegal address access Error Status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
No error occurred
#1 : 1
Error occurred
End of enumeration elements list.
BUS Error Clear Register %s
address_offset : 0x1A08 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLERRCLR : Slave bus Error Clear
bits : 0 - -1 (0 bit)
access : read-write
STERRCLR : Slave TrustZone filter Error Clear
bits : 1 - 0 (0 bit)
access : read-write
MMERRCLR : Master MPU Error Clear
bits : 3 - 2 (0 bit)
access : read-write
ILERRCLR : Illegal Address Access Error Clear
bits : 4 - 3 (0 bit)
access : read-write
BUS Error Status Register %s
address_offset : 0x1A10 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SLERRSTAT : Slave bus Error Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No error occurred
#1 : 1
Error occurred
End of enumeration elements list.
STERRSTAT : Slave TrustZone filter Error Status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
No error occurred
#1 : 1
Error occurred
End of enumeration elements list.
MMERRSTAT : Master MPU Error Status
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
No error occurred
#1 : 1
Error occurred
End of enumeration elements list.
ILERRSTAT : Illegal address access Error Status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
No error occurred
#1 : 1
Error occurred
End of enumeration elements list.
BUS Error Clear Register %s
address_offset : 0x1A18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLERRCLR : Slave bus Error Clear
bits : 0 - -1 (0 bit)
access : read-write
STERRCLR : Slave TrustZone filter Error Clear
bits : 1 - 0 (0 bit)
access : read-write
MMERRCLR : Master MPU Error Clear
bits : 3 - 2 (0 bit)
access : read-write
ILERRCLR : Illegal Address Access Error Clear
bits : 4 - 3 (0 bit)
access : read-write
BUS Error Status Register %s
address_offset : 0x1A20 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SLERRSTAT : Slave bus Error Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No error occurred
#1 : 1
Error occurred
End of enumeration elements list.
STERRSTAT : Slave TrustZone filter Error Status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
No error occurred
#1 : 1
Error occurred
End of enumeration elements list.
MMERRSTAT : Master MPU Error Status
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
No error occurred
#1 : 1
Error occurred
End of enumeration elements list.
ILERRSTAT : Illegal address access Error Status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
No error occurred
#1 : 1
Error occurred
End of enumeration elements list.
DMAC/DTC Error Status Register
address_offset : 0x1A24 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MTERRSTAT : Master TrustZone Filter Error Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No error occurred
#1 : 1
Error occurred
End of enumeration elements list.
BUS Error Clear Register %s
address_offset : 0x1A28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLERRCLR : Slave bus Error Clear
bits : 0 - -1 (0 bit)
access : read-write
STERRCLR : Slave TrustZone filter Error Clear
bits : 1 - 0 (0 bit)
access : read-write
MMERRCLR : Master MPU Error Clear
bits : 3 - 2 (0 bit)
access : read-write
ILERRCLR : Illegal Address Access Error Clear
bits : 4 - 3 (0 bit)
access : read-write
DMAC/DTC Error Clear Register
address_offset : 0x1A2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MTERRCLR : Master TrustZone filter Error Clear
bits : 0 - -1 (0 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.