\n

BUS

Peripheral Memory Blocks

address_offset : 0x1100 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1104 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1110 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1120 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1130 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1134 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1140 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1800 Bytes (0x0)
size : 0x34 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1900 Bytes (0x0)
size : 0x34 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1A00 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection : not protected

Registers

BUSSCNTFHBIU

BUSSCNTFLBIU

BUSSCNTS0BIU

BUSSCNTPSBIU

BUSSCNTPLBIU

BUSSCNTPHBIU

BUSSCNTEQBIU

BUS1ERRADD

BUS1ERRRW

BUS2ERRADD

BUS2ERRRW

BUS3ERRADD

BUS3ERRRW

BTZF1ERRADD

BTZF1ERRRW

BTZF2ERRADD

BTZF2ERRRW

BTZF3ERRADD

BTZF3ERRRW

BUS1ERRSTAT

BUS1ERRCLR

BUS2ERRSTAT

BUS2ERRCLR

BUS3ERRSTAT

DMACDTCERRSTAT

BUS3ERRCLR

DMACDTCERRCLR


BUSSCNTFHBIU

Slave Bus Control Register
address_offset : 0x1100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSSCNTFHBIU BUSSCNTFHBIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBS

ARBS : Arbitration Select for two masters
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

DMAC/DTC > CPU

#01 : 01

DMAC/DTC ↔ CPU

#10 : 10

Setting prohibited

#11 : 11

Setting prohibited

End of enumeration elements list.


BUSSCNTFLBIU

Slave Bus Control Register
address_offset : 0x1104 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSSCNTFLBIU BUSSCNTFLBIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBS

ARBS : Arbitration Select for two masters
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

DMAC/DTC > CPU

#01 : 01

DMAC/DTC ↔ CPU

#10 : 10

Setting prohibited

#11 : 11

Setting prohibited

End of enumeration elements list.


BUSSCNTS0BIU

Slave Bus Control Register
address_offset : 0x1110 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSSCNTS0BIU BUSSCNTS0BIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBS

ARBS : Arbitration Select for two masters
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

DMAC/DTC > CPU

#01 : 01

DMAC/DTC ↔ CPU

#10 : 10

Setting prohibited

#11 : 11

Setting prohibited

End of enumeration elements list.


BUSSCNTPSBIU

Slave Bus Control Register
address_offset : 0x1120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSSCNTPSBIU BUSSCNTPSBIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBS

ARBS : Arbitration Select for two masters
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

DMAC/DTC > CPU

#1 : 1

DMAC/DTC ↔ CPU

End of enumeration elements list.


BUSSCNTPLBIU

Slave Bus Control Register
address_offset : 0x1130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSSCNTPLBIU BUSSCNTPLBIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBS

ARBS : Arbitration Select for two masters
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

DMAC/DTC > CPU

#1 : 1

DMAC/DTC ↔ CPU

End of enumeration elements list.


BUSSCNTPHBIU

Slave Bus Control Register
address_offset : 0x1134 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSSCNTPHBIU BUSSCNTPHBIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBS

ARBS : Arbitration Select for two masters
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

DMAC/DTC > CPU

#1 : 1

DMAC/DTC ↔ CPU

End of enumeration elements list.


BUSSCNTEQBIU

Slave Bus Control Register
address_offset : 0x1140 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSSCNTEQBIU BUSSCNTEQBIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBS

ARBS : Arbitration Select for two masters
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

DMAC/DTC > CPU

#01 : 01

DMAC/DTC ↔ CPU

#10 : 10

Setting prohibited

#11 : 11

Setting prohibited

End of enumeration elements list.


BUS1ERRADD

BUS Error Address Register
address_offset : 0x1800 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS1ERRADD BUS1ERRADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error Address
bits : 0 - 30 (31 bit)
access : read-only


BUS1ERRRW

BUS Error Read Write Register
address_offset : 0x1804 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUS1ERRRW BUS1ERRRW read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RWSTAT

RWSTAT : Error Access Read/Write Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write access

End of enumeration elements list.


BUS2ERRADD

BUS Error Address Register
address_offset : 0x1810 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS2ERRADD BUS2ERRADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error Address
bits : 0 - 30 (31 bit)
access : read-only


BUS2ERRRW

BUS Error Read Write Register
address_offset : 0x1814 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUS2ERRRW BUS2ERRRW read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RWSTAT

RWSTAT : Error Access Read/Write Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write access

End of enumeration elements list.


BUS3ERRADD

BUS Error Address Register
address_offset : 0x1820 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS3ERRADD BUS3ERRADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error Address
bits : 0 - 30 (31 bit)
access : read-only


BUS3ERRRW

BUS Error Read Write Register
address_offset : 0x1824 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUS3ERRRW BUS3ERRRW read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RWSTAT

RWSTAT : Error Access Read/Write Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write access

End of enumeration elements list.


BTZF1ERRADD

BUS TZF Error Address Register
address_offset : 0x1900 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BTZF1ERRADD BTZF1ERRADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTZFERAD

BTZFERAD : Bus TrustZone Filter Error Address
bits : 0 - 30 (31 bit)
access : read-only


BTZF1ERRRW

BUS TZF Error Read Write Register
address_offset : 0x1904 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTZF1ERRRW BTZF1ERRRW read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRWSTAT

TRWSTAT : TrustZone filter error access Read/Write Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write access

End of enumeration elements list.


BTZF2ERRADD

BUS TZF Error Address Register
address_offset : 0x1910 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BTZF2ERRADD BTZF2ERRADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTZFERAD

BTZFERAD : Bus TrustZone Filter Error Address
bits : 0 - 30 (31 bit)
access : read-only


BTZF2ERRRW

BUS TZF Error Read Write Register
address_offset : 0x1914 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTZF2ERRRW BTZF2ERRRW read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRWSTAT

TRWSTAT : TrustZone filter error access Read/Write Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write access

End of enumeration elements list.


BTZF3ERRADD

BUS TZF Error Address Register
address_offset : 0x1920 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BTZF3ERRADD BTZF3ERRADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTZFERAD

BTZFERAD : Bus TrustZone Filter Error Address
bits : 0 - 30 (31 bit)
access : read-only


BTZF3ERRRW

BUS TZF Error Read Write Register
address_offset : 0x1924 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTZF3ERRRW BTZF3ERRRW read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRWSTAT

TRWSTAT : TrustZone filter error access Read/Write Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write access

End of enumeration elements list.


BUS1ERRSTAT

BUS Error Status Register %s
address_offset : 0x1A00 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS1ERRSTAT BUS1ERRSTAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLERRSTAT STERRSTAT MMERRSTAT ILERRSTAT

SLERRSTAT : Slave bus Error Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

STERRSTAT : Slave TrustZone filter Error Status
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

MMERRSTAT : Master MPU Error Status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

ILERRSTAT : Illegal address access Error Status
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.


BUS1ERRCLR

BUS Error Clear Register %s
address_offset : 0x1A08 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUS1ERRCLR BUS1ERRCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLERRCLR STERRCLR MMERRCLR ILERRCLR

SLERRCLR : Slave bus Error Clear
bits : 0 - -1 (0 bit)
access : read-write

STERRCLR : Slave TrustZone filter Error Clear
bits : 1 - 0 (0 bit)
access : read-write

MMERRCLR : Master MPU Error Clear
bits : 3 - 2 (0 bit)
access : read-write

ILERRCLR : Illegal Address Access Error Clear
bits : 4 - 3 (0 bit)
access : read-write


BUS2ERRSTAT

BUS Error Status Register %s
address_offset : 0x1A10 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS2ERRSTAT BUS2ERRSTAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLERRSTAT STERRSTAT MMERRSTAT ILERRSTAT

SLERRSTAT : Slave bus Error Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

STERRSTAT : Slave TrustZone filter Error Status
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

MMERRSTAT : Master MPU Error Status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

ILERRSTAT : Illegal address access Error Status
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.


BUS2ERRCLR

BUS Error Clear Register %s
address_offset : 0x1A18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUS2ERRCLR BUS2ERRCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLERRCLR STERRCLR MMERRCLR ILERRCLR

SLERRCLR : Slave bus Error Clear
bits : 0 - -1 (0 bit)
access : read-write

STERRCLR : Slave TrustZone filter Error Clear
bits : 1 - 0 (0 bit)
access : read-write

MMERRCLR : Master MPU Error Clear
bits : 3 - 2 (0 bit)
access : read-write

ILERRCLR : Illegal Address Access Error Clear
bits : 4 - 3 (0 bit)
access : read-write


BUS3ERRSTAT

BUS Error Status Register %s
address_offset : 0x1A20 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS3ERRSTAT BUS3ERRSTAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLERRSTAT STERRSTAT MMERRSTAT ILERRSTAT

SLERRSTAT : Slave bus Error Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

STERRSTAT : Slave TrustZone filter Error Status
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

MMERRSTAT : Master MPU Error Status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

ILERRSTAT : Illegal address access Error Status
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.


DMACDTCERRSTAT

DMAC/DTC Error Status Register
address_offset : 0x1A24 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACDTCERRSTAT DMACDTCERRSTAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MTERRSTAT

MTERRSTAT : Master TrustZone Filter Error Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.


BUS3ERRCLR

BUS Error Clear Register %s
address_offset : 0x1A28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUS3ERRCLR BUS3ERRCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLERRCLR STERRCLR MMERRCLR ILERRCLR

SLERRCLR : Slave bus Error Clear
bits : 0 - -1 (0 bit)
access : read-write

STERRCLR : Slave TrustZone filter Error Clear
bits : 1 - 0 (0 bit)
access : read-write

MMERRCLR : Master MPU Error Clear
bits : 3 - 2 (0 bit)
access : read-write

ILERRCLR : Illegal Address Access Error Clear
bits : 4 - 3 (0 bit)
access : read-write


DMACDTCERRCLR

DMAC/DTC Error Clear Register
address_offset : 0x1A2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACDTCERRCLR DMACDTCERRCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MTERRCLR

MTERRCLR : Master TrustZone filter Error Clear
bits : 0 - -1 (0 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.