\n
address_offset : 0x0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xE Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
DTC Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRS : DTC Transfer Information Read Skip Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transfer information read is not skipped
#1 : 1
Transfer information read is skipped when vector numbers match
End of enumeration elements list.
DTC Control Register for secure Region
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRS : DTC Transfer Information Read Skip Enable for Secure
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transfer information read is not skipped.
#1 : 1
Transfer information read is skipped when vector numbers match.
End of enumeration elements list.
DTC Vector Base Register for secure Region
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTC Error Vector Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTEV : DTC Error Vector Number
bits : 0 - 6 (7 bit)
access : read-only
DTEVSAM : DTC Error Vector Number SA Monitor
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : 0
Secure vector number
#1 : 1
Non-Secure vector number
End of enumeration elements list.
DTESTA : DTC Error Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No DTC transfer error occurred
#1 : 1
DTC transfer error occurred
End of enumeration elements list.
DTC Vector Base Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTC Module Start Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCST : DTC Module Start
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC module stopped
#1 : 1
DTC module started
End of enumeration elements list.
DTC Status Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VECN : DTC-Activating Vector Number Monitoring
bits : 0 - 6 (7 bit)
access : read-only
ACT : DTC Active Flag
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
DTC transfer operation is not in progress
#1 : 1
DTC transfer operation is in progress
End of enumeration elements list.
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