Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
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mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
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mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x36 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x46 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
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mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
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size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x6C Bytes (0x0)
size : 0x16 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x90 Bytes (0x0)
size : 0x16 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xB0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x400 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
System Configuration Control Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBE : USBFS Operation Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
DPRPU : D+ Line Resistor Control
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable line pull-up
#1 : 1
Enable line pull-up
End of enumeration elements list.
DRPD : D+/D– Line Resistor Control
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable line pull-down
#1 : 1
Enable line pull-down
End of enumeration elements list.
DCFM : Controller Function Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Select device controller
#1 : 1
Select host controller
End of enumeration elements list.
SCKE : USB Clock Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stop clock supply to the USBFS
#1 : 1
Enable clock supply to the USBFS
End of enumeration elements list.
CFIFO Port Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOPORT : FIFO Port
bits : 0 - 14 (15 bit)
access : read-write
CFIFO Port Register
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CFIFO
reset_Mask : 0x0
D%sFIFO Port Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOPORT : FIFO Port
bits : 0 - 14 (15 bit)
access : read-write
D%sFIFO Port Register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : D%sFIFO
reset_Mask : 0x0
D%sFIFO Port Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOPORT : FIFO Port
bits : 0 - 14 (15 bit)
access : read-write
D%sFIFO Port Register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : D%sFIFO
reset_Mask : 0x0
CFIFO Port Select Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURPIPE : CFIFO Port Access Pipe Specification
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
Default Control Pipe
0x1 : 0x1
Pipe 1
0x2 : 0x2
Pipe 2
0x3 : 0x3
Pipe 3
0x4 : 0x4
Pipe 4
0x5 : 0x5
Pipe 5
0x6 : 0x6
Pipe 6
0x7 : 0x7
Pipe 7
0x8 : 0x8
Pipe 8
0x9 : 0x9
Pipe 9
: Others
Setting prohibited
End of enumeration elements list.
ISEL : CFIFO Port Access Direction When DCP Is Selected
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Select reading from the FIFO buffer
#1 : 1
Select writing to the FIFO buffer
End of enumeration elements list.
BIGEND : CFIFO Port Endian Control
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Little endian
#1 : 1
Big endian
End of enumeration elements list.
MBW : CFIFO Port Access Bit Width
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
8-bit width
#1 : 1
16-bit width
End of enumeration elements list.
REW : Buffer Pointer Rewind
bits : 14 - 13 (0 bit)
access : write-only
Enumeration:
#0 : 0
Do not rewind buffer pointer
#1 : 1
Rewind buffer pointer
End of enumeration elements list.
RCNT : Read Count Mode
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
The DTLN[8:0] bits (CFIFOCTR.DTLN[8:0], D0FIFOCTR.DTLN[8:0], D1FIFOCTR.DTLN[8:0]) are cleared when all receive data is read from the CFIFO. In double buffer mode, the DTLN[8:0] value is cleared when all data is read from only a single plane.
#1 : 1
The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO.
End of enumeration elements list.
CFIFO Port Control Register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTLN : Receive Data Length
bits : 0 - 7 (8 bit)
access : read-only
FRDY : FIFO Port Ready
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO port access disabled
#1 : 1
FIFO port access enabled
End of enumeration elements list.
BCLR : CPU Buffer Clear
bits : 14 - 13 (0 bit)
access : write-only
Enumeration:
#0 : 0
No operation
#1 : 1
Clear FIFO buffer on the CPU side
End of enumeration elements list.
BVAL : Buffer Memory Valid Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Writing ended
End of enumeration elements list.
D%sFIFO Port Select Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURPIPE : FIFO Port Access Pipe Specification
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
Default Control Pipe
0x1 : 0x1
Pipe 1
0x2 : 0x2
Pipe 2
0x3 : 0x3
Pipe 3
0x4 : 0x4
Pipe 4
0x5 : 0x5
Pipe 5
0x6 : 0x6
Pipe 6
0x7 : 0x7
Pipe 7
0x8 : 0x8
Pipe 8
0x9 : 0x9
Pipe 9
: Others
Setting prohibited
End of enumeration elements list.
BIGEND : FIFO Port Endian Control
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Little endian
#1 : 1
Big endian
End of enumeration elements list.
MBW : FIFO Port Access Bit Width
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
8-bit width
#1 : 1
16-bit width
End of enumeration elements list.
DREQE : DMA/DTC Transfer Request Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA/DTC transfer request
#1 : 1
Enable DMA/DTC transfer request
End of enumeration elements list.
DCLRM : Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable auto buffer clear mode
#1 : 1
Enable auto buffer clear mode
End of enumeration elements list.
REW : Buffer Pointer Rewind
bits : 14 - 13 (0 bit)
access : write-only
Enumeration:
#0 : 0
Do not rewind buffer pointer
#1 : 1
Rewind buffer pointer
End of enumeration elements list.
RCNT : Read Count Mode
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Clear DTLN[8:0] bits in (CFIFOCTR.DTLN[8:0], D0FIFOCTR.DTLN[8:0], D1FIFOCTR.DTLN[8:0]) when all receive data is read from DnFIFO (after read of a single plane in double buffer mode)
#1 : 1
Decrement DTLN[8:0] bits each time receive data is read from DnFIFO
End of enumeration elements list.
D%sFIFO Port Control Register
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTLN : Receive Data Length
bits : 0 - 7 (8 bit)
access : read-only
FRDY : FIFO Port Ready
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO port access disabled
#1 : 1
FIFO port access enabled
End of enumeration elements list.
BCLR : CPU Buffer Clear
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
No operation
#1 : 1
Clear FIFO buffer on the CPU side
End of enumeration elements list.
BVAL : Buffer Memory Valid Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Writing ended
End of enumeration elements list.
D%sFIFO Port Select Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURPIPE : FIFO Port Access Pipe Specification
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
Default Control Pipe
0x1 : 0x1
Pipe 1
0x2 : 0x2
Pipe 2
0x3 : 0x3
Pipe 3
0x4 : 0x4
Pipe 4
0x5 : 0x5
Pipe 5
0x6 : 0x6
Pipe 6
0x7 : 0x7
Pipe 7
0x8 : 0x8
Pipe 8
0x9 : 0x9
Pipe 9
: Others
Setting prohibited
End of enumeration elements list.
BIGEND : FIFO Port Endian Control
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Little endian
#1 : 1
Big endian
End of enumeration elements list.
MBW : FIFO Port Access Bit Width
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
8-bit width
#1 : 1
16-bit width
End of enumeration elements list.
DREQE : DMA/DTC Transfer Request Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA/DTC transfer request
#1 : 1
Enable DMA/DTC transfer request
End of enumeration elements list.
DCLRM : Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable auto buffer clear mode
#1 : 1
Enable auto buffer clear mode
End of enumeration elements list.
REW : Buffer Pointer Rewind
bits : 14 - 13 (0 bit)
access : write-only
Enumeration:
#0 : 0
Do not rewind buffer pointer
#1 : 1
Rewind buffer pointer
End of enumeration elements list.
RCNT : Read Count Mode
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Clear DTLN[8:0] bits in (CFIFOCTR.DTLN[8:0], D0FIFOCTR.DTLN[8:0], D1FIFOCTR.DTLN[8:0]) when all receive data is read from DnFIFO (after read of a single plane in double buffer mode)
#1 : 1
Decrement DTLN[8:0] bits each time receive data is read from DnFIFO
End of enumeration elements list.
D%sFIFO Port Control Register
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTLN : Receive Data Length
bits : 0 - 7 (8 bit)
access : read-only
FRDY : FIFO Port Ready
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO port access disabled
#1 : 1
FIFO port access enabled
End of enumeration elements list.
BCLR : CPU Buffer Clear
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
No operation
#1 : 1
Clear FIFO buffer on the CPU side
End of enumeration elements list.
BVAL : Buffer Memory Valid Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Writing ended
End of enumeration elements list.
Interrupt Enable Register 0
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRDYE : Buffer Ready Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
NRDYE : Buffer Not Ready Response Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
BEMPE : Buffer Empty Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
CTRE : Control Transfer Stage Transition Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
DVSE : Device State Transition Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
SOFE : Frame Number Update Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
RSME : Resume Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
VBSE : VBUS Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
Interrupt Enable Register 1
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDDETINTE : PDDETINT Detection Interrupt Request Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
SACKE : Setup Transaction Normal Response Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
SIGNE : Setup Transaction Error Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
EOFERRE : EOF Error Detection Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
ATTCHE : Connection Detection Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
DTCHE : Disconnection Detection Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
BCHGE : USB Bus Change Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
OVRCRE : Overcurrent Input Change Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
BRDY Interrupt Enable Register
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0BRDYE : BRDY Interrupt Enable for Pipe 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE1BRDYE : BRDY Interrupt Enable for Pipe 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE2BRDYE : BRDY Interrupt Enable for Pipe 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE3BRDYE : BRDY Interrupt Enable for Pipe 3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE4BRDYE : BRDY Interrupt Enable for Pipe 4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE5BRDYE : BRDY Interrupt Enable for Pipe 5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE6BRDYE : BRDY Interrupt Enable for Pipe 6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE7BRDYE : BRDY Interrupt Enable for Pipe 7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE8BRDYE : BRDY Interrupt Enable for Pipe 8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE9BRDYE : BRDY Interrupt Enable for Pipe 9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
NRDY Interrupt Enable Register
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0NRDYE : NRDY Interrupt Enable for Pipe 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE1NRDYE : NRDY Interrupt Enable for Pipe 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE2NRDYE : NRDY Interrupt Enable for Pipe 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE3NRDYE : NRDY Interrupt Enable for Pipe 3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE4NRDYE : NRDY Interrupt Enable for Pipe 4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE5NRDYE : NRDY Interrupt Enable for Pipe 5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE6NRDYE : NRDY Interrupt Enable for Pipe 6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE7NRDYE : NRDY Interrupt Enable for Pipe 7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE8NRDYE : NRDY Interrupt Enable for Pipe 8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE9NRDYE : NRDY Interrupt Enable for Pipe 9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
BEMP Interrupt Enable Register
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0BEMPE : BEMP Interrupt Enable for Pipe 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE1BEMPE : BEMP Interrupt Enable for Pipe 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE2BEMPE : BEMP Interrupt Enable for Pipe 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE3BEMPE : BEMP Interrupt Enable for Pipe 3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE4BEMPE : BEMP Interrupt Enable for Pipe 4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE5BEMPE : BEMP Interrupt Enable for Pipe 5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE6BEMPE : BEMP Interrupt Enable for Pipe 6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE7BEMPE : BEMP Interrupt Enable for Pipe 7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE8BEMPE : BEMP Interrupt Enable for Pipe 8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
PIPE9BEMPE : BEMP Interrupt Enable for Pipe 9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt request
#1 : 1
Enable interrupt request
End of enumeration elements list.
SOF Output Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGESTS : Edge Interrupt Output Status Monitor
bits : 4 - 3 (0 bit)
access : read-only
BRDYM : BRDY Interrupt Status Clear Timing
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Clear BRDY flag by software
#1 : 1
Clear BRDY flag by the USBFS through a data read from the FIFO buffer or data write to the FIFO buffer
End of enumeration elements list.
TRNENSEL : Transaction-Enabled Time Select
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not low-speed communication
#1 : 1
Low-speed communication
End of enumeration elements list.
System Configuration Status Register 0
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LNST : USB Data Line Status Monitor
bits : 0 - 0 (1 bit)
access : read-only
IDMON : External ID0 Input Pin Monitor
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
USB_ID pin is low
#1 : 1
USB_ID pin is high
End of enumeration elements list.
SOFEA : Active Monitor When the Host Controller Is Selected
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
SOF output stopped
#1 : 1
SOF output operating
End of enumeration elements list.
HTACT : USB Host Sequencer Status Monitor
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
Host sequencer completely stopped
#1 : 1
Host sequencer not completely stopped
End of enumeration elements list.
OVCMON : External USB_OVRCURA/ USB_OVRCURB Input Pin Monitor
bits : 14 - 14 (1 bit)
access : read-only
Interrupt Status Register 0
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTSQ : Control Transfer Stage
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
#000 : 000
Idle or setup stage
#001 : 001
Control read data stage
#010 : 010
Control read status stage
#011 : 011
Control write data stage
#100 : 100
Control write status stage
#101 : 101
Control write (no data) status stage
#110 : 110
Control transfer sequence error
End of enumeration elements list.
VALID : USB Request Reception
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Setup packet not received
#1 : 1
Setup packet received
End of enumeration elements list.
DVSQ : Device State
bits : 4 - 5 (2 bit)
access : read-only
Enumeration:
#000 : 000
Powered state
#001 : 001
Default state
#010 : 010
Address state
#011 : 011
Configured state
: Others
Suspend state
End of enumeration elements list.
VBSTS : VBUS Input Status
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
USB_VBUS pin is low
#1 : 1
USB_VBUS pin is high
End of enumeration elements list.
BRDY : Buffer Ready Interrupt Status
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : 0
No BRDY interrupt occurred
#1 : 1
BRDY interrupt occurred
End of enumeration elements list.
NRDY : Buffer Not Ready Interrupt Status
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : 0
No NRDY interrupt occurred
#1 : 1
NRDY interrupt occurred
End of enumeration elements list.
BEMP : Buffer Empty Interrupt Status
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : 0
No BEMP interrupt occurred
#1 : 1
BEMP interrupt occurred
End of enumeration elements list.
CTRT : Control Transfer Stage Transition Interrupt Status
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
No control transfer stage transition interrupt occurred
#1 : 1
Control transfer stage transition interrupt occurred
End of enumeration elements list.
DVST : Device State Transition Interrupt Status
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
No device state transition interrupt occurred
#1 : 1
Device state transition interrupt occurred
End of enumeration elements list.
SOFR : Frame Number Refresh Interrupt Status
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
No SOF interrupt occurred
#1 : 1
SOF interrupt occurred
End of enumeration elements list.
RESM : Resume Interrupt Status
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
No resume interrupt occurred
#1 : 1
Resume interrupt occurred
End of enumeration elements list.
VBINT : VBUS Interrupt Status
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
No VBUS interrupt occurred
#1 : 1
VBUS interrupt occurred
End of enumeration elements list.
Deep Software Standby USB Transceiver Control/Pin Monitor Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRPC0 : USB Single-ended Receiver Control
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable input through DP and DM inputs
#1 : 1
Enable input through DP and DM inputs
End of enumeration elements list.
RPUE0 : DP Pull-Up Resistor Control
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable DP pull-up resistor
#1 : 1
Enable DP pull-up resistor
End of enumeration elements list.
DRPD0 : D+/D– Pull-Down Resistor Control
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable DP/DM pull-down resistor
#1 : 1
Enable DP/DM pull-down resistor
End of enumeration elements list.
FIXPHY0 : USB Transceiver Output Fix
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Fix outputs in Normal mode and on return from Deep Software Standby mode
#1 : 1
Fix outputs on transition to Deep Software Standby mode
End of enumeration elements list.
DP0 : USB D+ Input
bits : 16 - 15 (0 bit)
access : read-only
DM0 : USB D– Input
bits : 17 - 16 (0 bit)
access : read-only
DOVCA0 : USB OVRCURA Input
bits : 20 - 19 (0 bit)
access : read-only
DOVCB0 : USB OVRCURB Input
bits : 21 - 20 (0 bit)
access : read-only
DPDDET0 : USB PDDET Input
bits : 22 - 21 (0 bit)
access : read-only
DVBSTS0 : USB VBUS Input
bits : 23 - 22 (0 bit)
access : read-only
Deep Software Standby USB Suspend/Resume Interrupt Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPINTE0 : USB DP Interrupt Enable/Clear
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable recovery from Deep Software Standby mode by DP input
#1 : 1
Enable recovery from Deep Software Standby mode by DP input
End of enumeration elements list.
DMINTE0 : USB DM Interrupt Enable/Clear
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable recovery from Deep Software Standby mode by DM input
#1 : 1
Enable recovery from Deep Software Standby mode by DM input
End of enumeration elements list.
DOVRCRAE0 : USB OVRCURA Interrupt Enable/Clear
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable recovery from Deep Software Standby mode by OVRCURA input
#1 : 1
Enable recovery from Deep Software Standby mode by OVRCURA input
End of enumeration elements list.
DOVRCRBE0 : USB OVRCURB Interrupt Enable/Clear
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable recovery from Deep Software Standby mode by OVRCURB input
#1 : 1
Enable recovery from Deep Software Standby mode by OVRCURB input
End of enumeration elements list.
DPDDETE0 : USB PDDET Interrupt Enable/Clear
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable recovery from Deep Software Standby mode by PDDET input
#1 : 1
Enable recovery from Deep Software Standby mode by PDDET input
End of enumeration elements list.
DVBSE0 : USB VBUS Interrupt Enable/Clear
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable recovery from Deep Software Standby mode by VBUS input
#1 : 1
Enable recovery from Deep Software Standby mode by VBUS input
End of enumeration elements list.
DPINT0 : USB DP Interrupt Source Recovery
bits : 16 - 15 (0 bit)
access : read-only
Enumeration:
#0 : 0
System has not recovered from Deep Software Standby mode
#1 : 1
System recovered from Deep Software Standby mode because of DP
End of enumeration elements list.
DMINT0 : USB DM Interrupt Source Recovery
bits : 17 - 16 (0 bit)
access : read-only
Enumeration:
#0 : 0
System has not recovered from Deep Software Standby mode
#1 : 1
System recovered from Deep Software Standby mode because of DM input
End of enumeration elements list.
DOVRCRA0 : USB OVRCURA Interrupt Source Recovery
bits : 20 - 19 (0 bit)
access : read-only
Enumeration:
#0 : 0
System has not recovered from Deep Software Standby mode
#1 : 1
System recovered from Deep Software Standby mode because of OVRCURA input
End of enumeration elements list.
DOVRCRB0 : USB OVRCURB Interrupt Source Recovery
bits : 21 - 20 (0 bit)
access : read-only
Enumeration:
#0 : 0
System has not recovered from Deep Software Standby mode
#1 : 1
System recovered from Deep Software Standby mode because of OVRCURB input
End of enumeration elements list.
DPDDETINT0 : USB PDDET Interrupt Source Recovery
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
System has not recovered from Deep Software Standby mode
#1 : 1
System recovered from Deep Software Standby mode because of PDDET input
End of enumeration elements list.
DVBINT0 : USB VBUS Interrupt Source Recovery
bits : 23 - 22 (0 bit)
access : read-only
Enumeration:
#0 : 0
System has not recovered from Deep Software Standby mode
#1 : 1
System recovered from Deep Software Standby mode because of VBUS input
End of enumeration elements list.
Deep Software Standby USB Battery Charging Control Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPPDDETE : PDDET Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable PDDET
#1 : 1
Enable PDDET
End of enumeration elements list.
DPDCPMODE : DCP Mode Control
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable DCP
#1 : 1
Enable DCP
End of enumeration elements list.
DPBATCHGE : Battery Charging Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable Battery Charging
#1 : 1
Enable Battery Charging
End of enumeration elements list.
DPPHYDET : Adjusts the detect sensitivity of Portable Device and Charging D- Port
bits : 12 - 12 (1 bit)
access : read-write
Interrupt Status Register 1
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDDETINT : PDDET Detection Interrupt Status Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No PDDET interrupt occurred
#1 : 1
PDDET interrupt occurred
End of enumeration elements list.
SACK : Setup Transaction Normal Response Interrupt Status
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No SACK interrupt occurred
#1 : 1
SACK interrupt occurred
End of enumeration elements list.
SIGN : Setup Transaction Error Interrupt Status
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
No SIGN interrupt occurred
#1 : 1
SIGN interrupt occurred
End of enumeration elements list.
EOFERR : EOF Error Detection Interrupt Status
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No EOFERR interrupt occurred
#1 : 1
EOFERR interrupt occurred
End of enumeration elements list.
ATTCH : ATTCH Interrupt Status
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
No ATTCH interrupt occurred
#1 : 1
ATTCH interrupt occurred
End of enumeration elements list.
DTCH : USB Disconnection Detection Interrupt Status
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
No DTCH interrupt occurred
#1 : 1
DTCH interrupt occurred
End of enumeration elements list.
BCHG : USB Bus Change Interrupt Status
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BCHG interrupt occurred
#1 : 1
BCHG interrupt occurred
End of enumeration elements list.
OVRCR : Overcurrent Input Change Interrupt Status
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
No OVRCR interrupt occurred
#1 : 1
OVRCR interrupt occurred
End of enumeration elements list.
BRDY Interrupt Status Register
address_offset : 0x46 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0BRDY : BRDY Interrupt Status for Pipe 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BRDY interrupt occurred
#1 : 1
BRDY interrupt occurred
End of enumeration elements list.
PIPE1BRDY : BRDY Interrupt Status for Pipe 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BRDY interrupt occurred
#1 : 1
BRDY interrupt occurred
End of enumeration elements list.
PIPE2BRDY : BRDY Interrupt Status for Pipe 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BRDY interrupt occurred
#1 : 1
BRDY interrupt occurred
End of enumeration elements list.
PIPE3BRDY : BRDY Interrupt Status for Pipe 3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BRDY interrupt occurred
#1 : 1
BRDY interrupt occurred
End of enumeration elements list.
PIPE4BRDY : BRDY Interrupt Status for Pipe 4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BRDY interrupt occurred
#1 : 1
BRDY interrupt occurred
End of enumeration elements list.
PIPE5BRDY : BRDY Interrupt Status for Pipe 5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BRDY interrupt occurred
#1 : 1
BRDY interrupt occurred
End of enumeration elements list.
PIPE6BRDY : BRDY Interrupt Status for Pipe 6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BRDY interrupt occurred
#1 : 1
BRDY interrupt occurred
End of enumeration elements list.
PIPE7BRDY : BRDY Interrupt Status for Pipe 7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BRDY interrupt occurred
#1 : 1
BRDY interrupt occurred
End of enumeration elements list.
PIPE8BRDY : BRDY Interrupt Status for Pipe 8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BRDY interrupt occurred
#1 : 1
BRDY interrupt occurred
End of enumeration elements list.
PIPE9BRDY : BRDY Interrupt Status for Pipe 9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BRDY interrupt occurred
#1 : 1
BRDY interrupt occurred
End of enumeration elements list.
NRDY Interrupt Status Register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0NRDY : NRDY Interrupt Status for Pipe 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No NRDY interrupt occurred
#1 : 1
NRDY interrupt occurred
End of enumeration elements list.
PIPE1NRDY : NRDY Interrupt Status for Pipe 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
No NRDY interrupt occurred
#1 : 1
NRDY interrupt occurred
End of enumeration elements list.
PIPE2NRDY : NRDY Interrupt Status for Pipe 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No NRDY interrupt occurred
#1 : 1
NRDY interrupt occurred
End of enumeration elements list.
PIPE3NRDY : NRDY Interrupt Status for Pipe 3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No NRDY interrupt occurred
#1 : 1
NRDY interrupt occurred
End of enumeration elements list.
PIPE4NRDY : NRDY Interrupt Status for Pipe 4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No NRDY interrupt occurred
#1 : 1
NRDY interrupt occurred
End of enumeration elements list.
PIPE5NRDY : NRDY Interrupt Status for Pipe 5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
No NRDY interrupt occurred
#1 : 1
NRDY interrupt occurred
End of enumeration elements list.
PIPE6NRDY : NRDY Interrupt Status for Pipe 6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No NRDY interrupt occurred
#1 : 1
NRDY interrupt occurred
End of enumeration elements list.
PIPE7NRDY : NRDY Interrupt Status for Pipe 7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
No NRDY interrupt occurred
#1 : 1
NRDY interrupt occurred
End of enumeration elements list.
PIPE8NRDY : NRDY Interrupt Status for Pipe 8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
No NRDY interrupt occurred
#1 : 1
NRDY interrupt occurred
End of enumeration elements list.
PIPE9NRDY : NRDY Interrupt Status for Pipe 9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
No NRDY interrupt occurred
#1 : 1
NRDY interrupt occurred
End of enumeration elements list.
BEMP Interrupt Status Register
address_offset : 0x4A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0BEMP : BEMP Interrupt Status for Pipe 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BEMP interrupt occurred
#1 : 1
BEMP interrupt occurred
End of enumeration elements list.
PIPE1BEMP : BEMP Interrupt Status for Pipe 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BEMP interrupt occurred
#1 : 1
BEMP interrupt occurred
End of enumeration elements list.
PIPE2BEMP : BEMP Interrupt Status for Pipe 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BEMP interrupt occurred
#1 : 1
BEMP interrupt occurred
End of enumeration elements list.
PIPE3BEMP : BEMP Interrupt Status for Pipe 3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BEMP interrupt occurred
#1 : 1
BEMP interrupt occurred
End of enumeration elements list.
PIPE4BEMP : BEMP Interrupt Status for Pipe 4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BEMP interrupt occurred
#1 : 1
BEMP interrupt occurred
End of enumeration elements list.
PIPE5BEMP : BEMP Interrupt Status for Pipe 5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BEMP interrupt occurred
#1 : 1
BEMP interrupt occurred
End of enumeration elements list.
PIPE6BEMP : BEMP Interrupt Status for Pipe 6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BEMP interrupt occurred
#1 : 1
BEMP interrupt occurred
End of enumeration elements list.
PIPE7BEMP : BEMP Interrupt Status for Pipe 7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BEMP interrupt occurred
#1 : 1
BEMP interrupt occurred
End of enumeration elements list.
PIPE8BEMP : BEMP Interrupt Status for Pipe 8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BEMP interrupt occurred
#1 : 1
BEMP interrupt occurred
End of enumeration elements list.
PIPE9BEMP : BEMP Interrupt Status for Pipe 9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
No BEMP interrupt occurred
#1 : 1
BEMP interrupt occurred
End of enumeration elements list.
Frame Number Register
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRNM : Frame Number
bits : 0 - 9 (10 bit)
access : read-only
CRCE : Receive Data Error
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
No error occurred
#1 : 1
Error occurred
End of enumeration elements list.
OVRN : Overrun/Underrun Detection Status
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
No error occurred
#1 : 1
Error occurred
End of enumeration elements list.
Device State Change Register
address_offset : 0x4E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DVCHG : Device State Change
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable writes to the USBADDR.STSRECOV[3:0] and USBADDR.USBADDR[6:0] bits
#1 : 1
Enable writes to the USBADDR.STSRECOV[3:0] and USBADDR.USBADDR[6:0] bits
End of enumeration elements list.
USB Address Register
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBADDR : USB Address
bits : 0 - 5 (6 bit)
access : read-write
STSRECOV : Status Recovery
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x4 : 0x4
Recovery in device controller mode: Setting prohibited Recovery in host controller mode: Return to the low-speed state (bits DVSTCTR0.RHST[2:0] = 001b)
0x8 : 0x8
Recovery in device controller mode: Setting prohibited Recovery in host controller mode: Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b)
0x9 : 0x9
Recovery in device controller mode: Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 001b (default state) Recovery in host controller mode: Setting prohibited
0xa : 0xA
Recovery in device controller mode: Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 010b (address state) Recovery in host controller mode: Setting prohibited
0xb : 0xB
Recovery in device controller mode: Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 011b (configured state) Recovery in host controller mode: Setting prohibited
: Others
Setting prohibited
End of enumeration elements list.
USB Request Type Register
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BMREQUESTTYPE : Request Type
bits : 0 - 6 (7 bit)
access : read-write
BREQUEST : Request
bits : 8 - 14 (7 bit)
access : read-write
USB Request Value Register
address_offset : 0x56 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WVALUE : Value
bits : 0 - 14 (15 bit)
access : read-write
USB Request Index Register
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WINDEX : Index
bits : 0 - 14 (15 bit)
access : read-write
USB Request Length Register
address_offset : 0x5A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLENTUH : Length
bits : 0 - 14 (15 bit)
access : read-write
DCP Configuration Register
address_offset : 0x5C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Transfer Direction
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data receiving direction
#1 : 1
Data transmitting direction
End of enumeration elements list.
SHTNAK : Pipe Disabled at End of Transfer
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Keep pipe open after transfer ends
#1 : 1
Disable pipe after transfer ends
End of enumeration elements list.
DCP Maximum Packet Size Register
address_offset : 0x5E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MXPS : Maximum Packet Size
bits : 0 - 5 (6 bit)
access : read-write
DEVSEL : Device Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
Address 0000b
0x1 : 0x1
Address 0001b
0x2 : 0x2
Address 0010b
0x3 : 0x3
Address 0011b
0x4 : 0x4
Address 0100b
0x5 : 0x5
Address 0101b
: Others
Setting prohibited
End of enumeration elements list.
DCP Control Register
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depends on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
CCPL : Control Transfer End Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable control transfer completion
#1 : 1
Enable control transfer completion
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
DCP not used for the USB bus
#1 : 1
DCP in use for the USB bus
End of enumeration elements list.
SQMON : Sequence Toggle Bit Monitor
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
ATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Set the expected value for the next transaction to DATA1
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Clear the expected value for the next transaction to DATA0
End of enumeration elements list.
SUREQCLR : SUREQ Bit Clear
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Clear SUREQ to 0
End of enumeration elements list.
SUREQ : Setup Token Transmission
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Transmit setup packet
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access disabled
#1 : 1
Buffer access enabled
End of enumeration elements list.
Pipe Window Select Register
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPESEL : Pipe Window Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
No pipe selected
0x1 : 0x1
Pipe 1
0x2 : 0x2
Pipe 2
0x3 : 0x3
Pipe 3
0x4 : 0x4
Pipe 4
0x5 : 0x5
Pipe 5
0x6 : 0x6
Pipe 6
0x7 : 0x7
Pipe 7
0x8 : 0x8
Pipe 8
0x9 : 0x9
Pipe 9
: Others
Setting prohibited
End of enumeration elements list.
Pipe Configuration Register
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPNUM : Endpoint Number
bits : 0 - 2 (3 bit)
access : read-write
DIR : Transfer Direction
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Receiving direction
#1 : 1
Transmitting direction
End of enumeration elements list.
SHTNAK : Pipe Disabled at End of Transfer
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Continue pipe operation after transfer ends
#1 : 1
Disable pipe after transfer ends
End of enumeration elements list.
DBLB : Double Buffer Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Single buffer
#1 : 1
Double buffer
End of enumeration elements list.
BFRE : BRDY Interrupt Operation Specification
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Generate BRDY interrupt on transmitting or receiving data
#1 : 1
Generate BRDY interrupt on completion of reading data
End of enumeration elements list.
TYPE : Transfer Type
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#00 : 00
Pipe not used
#01 : 01
Pipes 1 and 2: Bulk transfer Pipes 3 to 5: Bulk transfer Pipes 6 to 9: Setting prohibited
#10 : 10
Pipes 1 and 2: Setting prohibited Pipes 3 to 5: Setting prohibited Pipes 6 to 9: Interrupt transfer
#11 : 11
Pipes 1 and 2: Isochronous transfer Pipes 3 to 5: Setting prohibited Pipes 6 to 9: Setting prohibited
End of enumeration elements list.
Pipe Maximum Packet Size Register
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MXPS : Maximum Packet Size
bits : 0 - 7 (8 bit)
access : read-write
DEVSEL : Device Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
Address 0000b
0x1 : 0x1
Address 0001b
0x2 : 0x2
Address 0010b
0x3 : 0x3
Address 0011b
0x4 : 0x4
Address 0100b
0x5 : 0x5
Address 0101b
: Others
Setting prohibited
End of enumeration elements list.
Pipe Cycle Control Register
address_offset : 0x6E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IITV : Interval Error Detection Interval
bits : 0 - 1 (2 bit)
access : read-write
IFIS : Isochronous IN Buffer Flush
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not flush buffer
#1 : 1
Flush buffer
End of enumeration elements list.
PIPE%s Control Registers
address_offset : 0x70 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depends buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Set the expected value for the next transaction to DATA1
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Clear the expected value for the next transaction to DATA0
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable (initialize all buffers)
End of enumeration elements list.
ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable auto response mode
#1 : 1
Enable auto response mode
End of enumeration elements list.
INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
No data to be transmitted is in the FIFO buffer
#1 : 1
Data to be transmitted is in the FIFO buffer
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access by the CPU disabled
#1 : 1
Buffer access by the CPU enabled
End of enumeration elements list.
PIPE%s Control Registers
address_offset : 0x72 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depends buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Set the expected value for the next transaction to DATA1
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Clear the expected value for the next transaction to DATA0
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable (initialize all buffers)
End of enumeration elements list.
ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable auto response mode
#1 : 1
Enable auto response mode
End of enumeration elements list.
INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
No data to be transmitted is in the FIFO buffer
#1 : 1
Data to be transmitted is in the FIFO buffer
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access by the CPU disabled
#1 : 1
Buffer access by the CPU enabled
End of enumeration elements list.
PIPE%s Control Registers
address_offset : 0x74 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depends buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Set the expected value for the next transaction to DATA1
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Clear the expected value for the next transaction to DATA0
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable (initialize all buffers)
End of enumeration elements list.
ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable auto response mode
#1 : 1
Enable auto response mode
End of enumeration elements list.
INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
No data to be transmitted is in the FIFO buffer
#1 : 1
Data to be transmitted is in the FIFO buffer
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access by the CPU disabled
#1 : 1
Buffer access by the CPU enabled
End of enumeration elements list.
PIPE%s Control Registers
address_offset : 0x76 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depends buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Set the expected value for the next transaction to DATA1
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Clear the expected value for the next transaction to DATA0
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable (initialize all buffers)
End of enumeration elements list.
ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable auto response mode
#1 : 1
Enable auto response mode
End of enumeration elements list.
INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
No data to be transmitted is in the FIFO buffer
#1 : 1
Data to be transmitted is in the FIFO buffer
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access by the CPU disabled
#1 : 1
Buffer access by the CPU enabled
End of enumeration elements list.
PIPE%s Control Registers
address_offset : 0x78 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depends buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Set the expected value for the next transaction to DATA1
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Clear the expected value for the next transaction to DATA0
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable (initialize all buffers)
End of enumeration elements list.
ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable auto response mode
#1 : 1
Enable auto response mode
End of enumeration elements list.
INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
No data to be transmitted is in the FIFO buffer
#1 : 1
Data to be transmitted is in the FIFO buffer
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access by the CPU disabled
#1 : 1
Buffer access by the CPU enabled
End of enumeration elements list.
PIPE%s Control Registers
address_offset : 0x7A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depends buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Set the expected value for the next transaction to DATA0
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Clear the expected value for the next transaction to DATA0
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable (all buffers initialized)
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access disabled
#1 : 1
Buffer access enabled
End of enumeration elements list.
PIPE%s Control Registers
address_offset : 0x7C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depends buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Set the expected value for the next transaction to DATA0
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Clear the expected value for the next transaction to DATA0
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable (all buffers initialized)
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access disabled
#1 : 1
Buffer access enabled
End of enumeration elements list.
PIPE%s Control Registers
address_offset : 0x7E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depends buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Set the expected value for the next transaction to DATA0
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Clear the expected value for the next transaction to DATA0
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable (all buffers initialized)
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access disabled
#1 : 1
Buffer access enabled
End of enumeration elements list.
Device State Control Register 0
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RHST : USB Bus Reset Status
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
#000 : 000
In host controller mode: Communication speed indeterminate (powered state or no connection) In device controller mode: Communication speed indeterminate
#001 : 001
In host controller mode: Low-speed connection In device controller mode: USB bus reset in progress
#010 : 010
In host controller mode: Full-speed connection In device controller mode: USB bus reset in progress or full-speed connection
#011 : 011
Setting prohibited
: Others
In host controller mode: USB bus reset in progress In device controller mode: Setting prohibited
End of enumeration elements list.
UACT : USB Bus Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable downstream port (disable SOF transmission)
#1 : 1
Enable downstream port (enable SOF transmission)
End of enumeration elements list.
RESUME : Resume Output
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not output resume signal
#1 : 1
Output resume signal
End of enumeration elements list.
USBRST : USB Bus Reset Output
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not output USB bus reset signal
#1 : 1
Output USB bus reset signal
End of enumeration elements list.
RWUPE : Wakeup Detection Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable downstream port remote wakeup
#1 : 1
Enable downstream port remote wakeup
End of enumeration elements list.
WKUP : Wakeup Output
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Do not output remote wakeup signal
#1 : 1
Output remote wakeup signal
End of enumeration elements list.
VBUSEN : USB_VBUSEN Output Pin Control
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output low on external USB_VBUSEN pin
#1 : 1
Output high on external USB_VBUSEN pin
End of enumeration elements list.
EXICEN : USB_EXICEN Output Pin Control
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output low on external USB_EXICEN pin
#1 : 1
Output high on external USB_EXICEN pin
End of enumeration elements list.
HNPBTOA : Host Negotiation Protocol (HNP) Control
bits : 11 - 10 (0 bit)
access : read-write
PIPE%s Control Registers
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depends buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Set the expected value for the next transaction to DATA0
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Clear the expected value for the next transaction to DATA0
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable (all buffers initialized)
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access disabled
#1 : 1
Buffer access enabled
End of enumeration elements list.
PIPE%s Transaction Counter Enable Register
address_offset : 0x90 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Clear counter value
End of enumeration elements list.
TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable transaction counter
#1 : 1
Enable transaction counter
End of enumeration elements list.
PIPE%s Transaction Counter Register
address_offset : 0x92 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write
PIPE%s Transaction Counter Enable Register
address_offset : 0x94 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Clear counter value
End of enumeration elements list.
TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable transaction counter
#1 : 1
Enable transaction counter
End of enumeration elements list.
PIPE%s Transaction Counter Register
address_offset : 0x96 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write
PIPE%s Transaction Counter Enable Register
address_offset : 0x98 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Clear counter value
End of enumeration elements list.
TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable transaction counter
#1 : 1
Enable transaction counter
End of enumeration elements list.
PIPE%s Transaction Counter Register
address_offset : 0x9A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write
PIPE%s Transaction Counter Enable Register
address_offset : 0x9C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Clear counter value
End of enumeration elements list.
TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable transaction counter
#1 : 1
Enable transaction counter
End of enumeration elements list.
PIPE%s Transaction Counter Register
address_offset : 0x9E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write
PIPE%s Transaction Counter Enable Register
address_offset : 0xA0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid (writing 0 has no effect)
#1 : 1
Clear counter value
End of enumeration elements list.
TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable transaction counter
#1 : 1
Enable transaction counter
End of enumeration elements list.
PIPE%s Transaction Counter Register
address_offset : 0xA2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write
Battery Charging Control Register 1
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RPDME : UDM Pull-down Control
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable UDM Pull-down
#1 : 1
Enable UDM Pull-down
End of enumeration elements list.
IDPSRCE : IDPSRC Control
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable IDP_SRC circuit
#1 : 1
Enable IDP_SRC circuit
End of enumeration elements list.
VDMSRCE : VDMSRC Control
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable VDM_SRC circuit
#1 : 1
Enable VDM_SRC circuit
End of enumeration elements list.
VDPSRCE : VDPSRC Control
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable VDP_SRC circuit
#1 : 1
Enable VDP_SRC circuit
End of enumeration elements list.
PDDETE : PDDET Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable PDDET
#1 : 1
Enable PDDET
End of enumeration elements list.
CHGDETE : CHGDET Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable CHGDET
#1 : 1
Enable CHGDET
End of enumeration elements list.
PDDETSTS : PDDET Status Flag
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : 0
The PDDET pin is at low level
#1 : 1
The PDDET pin is at high level
End of enumeration elements list.
CHGDETST : CHGDET Status Flag
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : 0
The CHGDET pin is at low level
#1 : 1
The CHGDET pin is at high level
End of enumeration elements list.
Battery Charging Control Register 2
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCPMODE : DCP Mode Control
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable DCP
#1 : 1
Enable DCP
End of enumeration elements list.
BATCHGE : Battery Charging Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable Battery Charging
#1 : 1
Enable Battery Charging
End of enumeration elements list.
PHYDET : Detect Sensitivity Adjustment
bits : 12 - 12 (1 bit)
access : read-write
Device Address %s Configuration Register
address_offset : 0xD0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
Do not use DEVADDn
#01 : 01
Low-speed
#10 : 10
Full-speed
#11 : 11
Setting prohibited
End of enumeration elements list.
Device Address %s Configuration Register
address_offset : 0xD2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
Do not use DEVADDn
#01 : 01
Low-speed
#10 : 10
Full-speed
#11 : 11
Setting prohibited
End of enumeration elements list.
Device Address %s Configuration Register
address_offset : 0xD4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
Do not use DEVADDn
#01 : 01
Low-speed
#10 : 10
Full-speed
#11 : 11
Setting prohibited
End of enumeration elements list.
Device Address %s Configuration Register
address_offset : 0xD6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
Do not use DEVADDn
#01 : 01
Low-speed
#10 : 10
Full-speed
#11 : 11
Setting prohibited
End of enumeration elements list.
Device Address %s Configuration Register
address_offset : 0xD8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
Do not use DEVADDn
#01 : 01
Low-speed
#10 : 10
Full-speed
#11 : 11
Setting prohibited
End of enumeration elements list.
Device Address %s Configuration Register
address_offset : 0xDA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
Do not use DEVADDn
#01 : 01
Low-speed
#10 : 10
Full-speed
#11 : 11
Setting prohibited
End of enumeration elements list.
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