Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REN : Reception Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables reception
#1 : 1
Enables reception (starts reception)
End of enumeration elements list.
TEN : Transmission Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables transmission
#1 : 1
Enables transmission (starts transmission)
End of enumeration elements list.
MUEN : Mute Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables muting on the next frame boundary
#1 : 1
Enables muting on the next frame boundary
End of enumeration elements list.
CKDV : Selects Bit Clock Division Ratio
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
AUDIO_MCK
0x1 : 0x1
AUDIO_MCK/2
0x2 : 0x2
AUDIO_MCK/4
0x3 : 0x3
AUDIO_MCK/8
0x4 : 0x4
AUDIO_MCK/16
0x5 : 0x5
AUDIO_MCK/32
0x6 : 0x6
AUDIO_MCK/64
0x7 : 0x7
AUDIO_MCK/128
0x8 : 0x8
AUDIO_MCK/6
0x9 : 0x9
AUDIO_MCK/12
0xa : 0xA
AUDIO_MCK/24
0xb : 0xB
AUDIO_MCK/48
0xc : 0xC
AUDIO_MCK/96
: Others
Setting prohibited
End of enumeration elements list.
DEL : Selects Serial Data Delay
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Delay of 1 cycle of SSIBCK between SSILRCK/SSIFS and SSITXD0/SSIRXD0
#1 : 1
No delay between SSILRCK/SSIFS and SSITXD0/SSIRXD0
End of enumeration elements list.
PDTA : Selects Placement Data Alignment
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Left-justifies placement data (SSIFTDR, SSIFRDR)
#1 : 1
Right-justifies placement data (SSIFTDR, SSIFRDR)
End of enumeration elements list.
SDTA : Selects Serial Data Alignment
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmits and receives serial data first and then padding bits
#1 : 1
Transmit and receives padding bits first and then serial data
End of enumeration elements list.
SPDP : Selects Serial Padding Polarity
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Padding data is at a low level
#1 : 1
Padding data is at a high level
End of enumeration elements list.
LRCKP : Selects the Initial Value and Polarity of LR Clock/Frame Synchronization Signal
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
The initial value is at a high level. The start trigger for a frame is synchronized with a falling edge of SSILRCK/SSIFS.
#1 : 1
The initial value is at a low level. The start trigger for a frame is synchronized with a rising edge of SSILRCK/SSIFS.
End of enumeration elements list.
BCKP : Selects Bit Clock Polarity
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
SSILRCK/SSIFS and SSITXD0/SSIRXD0 change at a falling edge (SSILRCK/SSIFS and SSIRXD0 are sampled at a rising edge of SSIBCK).
#1 : 1
SSILRCK/SSIFS and SSITXD0/SSIRXD0 change at a rising edge (SSILRCK/SSIFS and SSIRXD0 are sampled at a falling edge of SSIBCK).
End of enumeration elements list.
MST : Master Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Slave-mode communication
#1 : 1
Master-mode communication
End of enumeration elements list.
SWL : Selects System Word Length
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 bits
#001 : 001
16 bits
#010 : 010
24 bits
#011 : 011
32 bits
#100 : 100
48 bits
#101 : 101
64 bits
#110 : 110
128 bits
#111 : 111
256 bits
End of enumeration elements list.
DWL : Selects Data Word Length
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 bits
#001 : 001
16 bits
#010 : 010
18 bits
#011 : 011
20 bits
#100 : 100
22 bits
#101 : 101
24 bits
#110 : 110
32 bits
#111 : 111
Setting prohibited
End of enumeration elements list.
FRM : Selects Frame Word Number
bits : 22 - 22 (1 bit)
access : read-write
IIEN : Idle Mode Interrupt Output Enable
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables idle mode interrupt output
#1 : 1
Enables idle mode interrupt output
End of enumeration elements list.
ROIEN : Receive Overflow Interrupt Output Enable
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables receive overflow interrupt output
#1 : 1
Enables receive overflow interrupt output
End of enumeration elements list.
RUIEN : Receive Underflow Interrupt Output Enable
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables receive underflow interrupt output
#1 : 1
Enables receive underflow interrupt output
End of enumeration elements list.
TOIEN : Transmit Overflow Interrupt Output Enable
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables transmit overflow interrupt output
#1 : 1
Enables transmit overflow interrupt output
End of enumeration elements list.
TUIEN : Transmit Underflow Interrupt Output Enable
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables transmit underflow interrupt output
#1 : 1
Enables transmit underflow interrupt output
End of enumeration elements list.
CKS : Selects an Audio Clock for Master-mode Communication
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Selects the AUDIO_CLK input
#1 : 1
Selects the GTIOC2A (GPT output)
End of enumeration elements list.
FIFO Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFRST : Receive FIFO Data Register Reset
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Clears a receive data FIFO reset condition
#1 : 1
Sets a receive data FIFO reset condition
End of enumeration elements list.
TFRST : Transmit FIFO Data Register Reset
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Clears a transmit data FIFO reset condition
#1 : 1
Sets a transmit data FIFO reset condition
End of enumeration elements list.
RIE : Receive Data Full Interrupt Output Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables receive data full interrupts
#1 : 1
Enables receive data full interrupts
End of enumeration elements list.
TIE : Transmit Data Empty Interrupt Output Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables transmit data empty interrupts
#1 : 1
Enables transmit data empty interrupts
End of enumeration elements list.
BSW : Byte Swap Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables byte swap
#1 : 1
Enables byte swap
End of enumeration elements list.
SSIRST : Software Reset
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Clears a software reset condition
#1 : 1
Sets a software reset condition
End of enumeration elements list.
AUCKE : AUDIO_MCK Enable in Mastermode Communication
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables supply of AUDIO_MCK
#1 : 1
Enables supply of AUDIO_MCK
End of enumeration elements list.
FIFO Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDF : Receive Data Full Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The size of received data in SSIFRDR is not more than the value of SSISCR.RDFS.
#1 : 1
The size of received data in SSIFRDR is not less than the value of SSISCR.RDFS plus one.
End of enumeration elements list.
RDC : Number of Receive FIFO Data Indication Flag
bits : 8 - 12 (5 bit)
access : read-only
TDE : Transmit Data Empty Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
The free space of SSIFTDR is not more than the value of SSISCR.TDES.
#1 : 1
The free space of SSIFTDR is not less than the value of SSISCR.TDES plus one.
End of enumeration elements list.
TDC : Number of Transmit FIFO Data Indication Flag
bits : 24 - 28 (5 bit)
access : read-only
Transmit FIFO Data Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SSIFTDR : Transmit FIFO Data
bits : 0 - 30 (31 bit)
access : write-only
Receive FIFO Data Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SSIFRDR : Receive FIFO Data
bits : 0 - 30 (31 bit)
access : read-only
Audio Format Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OMOD : Audio Format Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
I2S format
#01 : 01
TDM format
#10 : 10
Monaural format
#11 : 11
Setting prohibited
End of enumeration elements list.
LRCONT : Whether to Enable LRCK/FS Continuation
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables LRCK/FS continuation
#1 : 1
Enables LRCK/FS continuation
End of enumeration elements list.
BCKASTP : Whether to Enable Stopping BCK Output When SSIE is in Idle Status
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Always outputs BCK to the SSIBCK pin
#1 : 1
Automatically controls output of BCK to the SSIBCK pin
End of enumeration elements list.
Status Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDFS : RDF Setting Condition Select
bits : 0 - 3 (4 bit)
access : read-write
TDES : TDE Setting Condition Select
bits : 8 - 11 (4 bit)
access : read-write
Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IIRQ : Idle Mode Status Flag
bits : 25 - 24 (0 bit)
access : read-only
Enumeration:
#0 : 0
In the communication state
#1 : 1
In the idle state
End of enumeration elements list.
ROIRQ : Receive Overflow Error Status Flag
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
No receive overflow error is generated.
#1 : 1
A receive overflow error is generated.
End of enumeration elements list.
RUIRQ : Receive Underflow Error Status Flag
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
No receive underflow error is generated.
#1 : 1
A receive underflow error is generated.
End of enumeration elements list.
TOIRQ : Transmit Overflow Error Status Flag
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
No transmit overflow error is generated.
#1 : 1
A transmit overflow error is generated.
End of enumeration elements list.
TUIRQ : Transmit Underflow Error Status flag
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
No transmit underflow error is generated.
#1 : 1
A transmit underflow error is generated.
End of enumeration elements list.
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