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SCI1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x13 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SMR

SMR_SMCI

BRR

RDRHL

MDDR

SCR

SCR_SMCI

ESMER

CR0

CR1

CR2

CR3

PCR

ICR

STR

STCR

CF0DR

CF0CR

CF0RR

PCF1DR

SCF1DR

CF1CR

CF1RR

TDR

TCR

TMR

TPRE

TCNT

SSR

SSR_SMCI

RDR

SCMR

SEMR

SNFR

SIMR1

SIMR2

SIMR3

SISR

SPMR

TDRHL


SMR

Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMR SMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKS MP STOP PM PE CHR CM

CKS : Clock Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLK clock (n = 0)

#01 : 01

PCLK/4 clock (n = 1)

#10 : 10

PCLK/16 clock (n = 2)

#11 : 11

PCLK/64 clock (n = 3)

End of enumeration elements list.

MP : Multi-Processor Mode
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable multi-processor communications function

#1 : 1

Enable multi-processor communications function

End of enumeration elements list.

STOP : Stop Bit Length
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

1 stop bit

#1 : 1

2 stop bits

End of enumeration elements list.

PM : Parity Mode
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Even parity

#1 : 1

Odd parity

End of enumeration elements list.

PE : Parity Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

When transmitting: Do not add parity bit When receiving: Do not check parity bit

#1 : 1

When transmitting: Add parity bit When receiving: Check parity bit

End of enumeration elements list.

CHR : Character Length
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value)

#1 : 1

SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 7-bit data length

End of enumeration elements list.

CM : Communication Mode
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Asynchronous mode or simple IIC mode

#1 : 1

Clock synchronous mode or simple SPI mode

End of enumeration elements list.


SMR_SMCI

Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1)
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SMR
reset_Mask : 0x0

SMR_SMCI SMR_SMCI read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKS BCP PM PE BLK GM

CKS : Clock Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLK clock (n = 0)

#01 : 01

PCLK/4 clock (n = 1)

#10 : 10

PCLK/16 clock (n = 2)

#11 : 11

PCLK/64 clock (n = 3)

End of enumeration elements list.

BCP : Base Clock Pulse
bits : 2 - 2 (1 bit)
access : read-write

PM : Parity Mode
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Even parity

#1 : 1

Odd parity

End of enumeration elements list.

PE : Parity Enable
bits : 5 - 4 (0 bit)
access : read-write

BLK : Block Transfer Mode
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal mode operation

#1 : 1

Block transfer mode operation

End of enumeration elements list.

GM : GSM Mode
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal mode operation

#1 : 1

GSM mode operation

End of enumeration elements list.


BRR

Bit Rate Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRR BRR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

RDRHL

Receive Data Register for Non-Manchester mode (MMR.MANEN = 0)
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : FRDRHL
reset_Mask : 0x0

RDRHL RDRHL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDAT

RDAT : Serial Receive Data
bits : 0 - 7 (8 bit)
access : read-only


MDDR

Modulation Duty Register
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDDR MDDR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

SCR

Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR SCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKE TEIE MPIE RE TE RIE TIE

CKE : Clock Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin.

#01 : 01

In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin.

: Others

In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the SEMR.ABCS bit is 1. The SCKn pin is available for use as an I/O port based on the I/O port settings when the GPT clock is used. In clock synchronous mode, the SCKn pin functions as the clock input pin.

End of enumeration elements list.

TEIE : Transmit End Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable SCIn_TEI interrupt requests

#1 : 1

Enable SCIn_TEI interrupt requests

End of enumeration elements list.

MPIE : Multi-Processor Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal reception

#1 : 1

When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed.

End of enumeration elements list.

RE : Receive Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable serial reception

#1 : 1

Enable serial reception

End of enumeration elements list.

TE : Transmit Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable serial transmission

#1 : 1

Enable serial transmission

End of enumeration elements list.

RIE : Receive Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable SCIn_RXI and SCIn_ERI interrupt requests

#1 : 1

Enable SCIn_RXI and SCIn_ERI interrupt requests

End of enumeration elements list.

TIE : Transmit Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable SCIn_TXI interrupt requests

#1 : 1

Enable SCIn_TXI interrupt requests

End of enumeration elements list.


SCR_SMCI

Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1)
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SCR
reset_Mask : 0x0

SCR_SMCI SCR_SMCI read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKE TEIE MPIE RE TE RIE TIE

CKE : Clock Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low

#01 : 01

When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock

#10 : 10

When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high

#11 : 11

When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock

End of enumeration elements list.

TEIE : Transmit End Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

MPIE : Multi-Processor Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write

RE : Receive Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable serial reception

#1 : 1

Enable serial reception

End of enumeration elements list.

TE : Transmit Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable serial transmission

#1 : 1

Enable serial transmission

End of enumeration elements list.

RIE : Receive Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable SCIn_RXI and SCIn_ERI interrupt requests

#1 : 1

Enable SCIn_RXI and SCIn_ERI interrupt requests

End of enumeration elements list.

TIE : Transmit Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable SCIn_TXI interrupt requests

#1 : 1

Enable SCIn_TXI interrupt requests

End of enumeration elements list.


ESMER

Extended Serial Module Enable Register
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ESMER ESMER read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ESME

ESME : Extended Serial Mode Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The extended serial mode is disabled.

#1 : 1

The extended serial mode is enabled.

End of enumeration elements list.


CR0

Control Register 0
address_offset : 0x21 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SFSF RXDSF BRME

SFSF : Start Frame Status Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Start Frame detection function is disabled.

#1 : 1

Start Frame detection function is enabled.

End of enumeration elements list.

RXDSF : RXDXn Input Status Flag
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : 0

RXDXn input is enabled.

#1 : 1

RXDXn input is disabled.

End of enumeration elements list.

BRME : Bit Rate Measurement Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Measurement of bit rate is disabled.

#1 : 1

Measurement of bit rate is enabled.

End of enumeration elements list.


CR1

Control Register 1
address_offset : 0x22 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BFE CF0RE CF1DS PIBE PIBS

BFE : Break Field Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Break Field detection is disabled.

#1 : 1

Break Field detection is enabled.

End of enumeration elements list.

CF0RE : Control Field 0 Reception Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception of Control Field 0 is disabled.

#1 : 1

Reception of Control Field 0 is enabled.

End of enumeration elements list.

CF1DS : Control Field 1 Data Register Select
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : 00

Selects comparison with the value in PCF1DR.

#01 : 01

Selects comparison with the value in SCF1DR.

#10 : 10

Selects comparison with the values in PCF1DR and SCF1DR.

#11 : 11

Setting prohibited.

End of enumeration elements list.

PIBE : Priority Interrupt Bit Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

The priority interrupt bit is disabled.

#1 : 1

The priority interrupt bit is enabled.

End of enumeration elements list.

PIBS : Priority Interrupt Bit Select
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

#000 : 000

0th bit of Control Field 1

#001 : 001

1st bit of Control Field 1

#010 : 010

2nd bit of Control Field 1

#011 : 011

3rd bit of Control Field 1

#100 : 100

4th bit of Control Field 1

#101 : 101

5th bit of Control Field 1

#110 : 110

6th bit of Control Field 1

#111 : 111

7th bit of Control Field 1

End of enumeration elements list.


CR2

Control Register 2
address_offset : 0x23 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DFCS BCCS RTS

DFCS : RXDXn Signal Digital Filter Clock Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

Filter is disabled.

#001 : 001

Filter clock is SCI base clock

#010 : 010

Filter clock is PCLK/8

#011 : 011

Filter clock is PCLK/16

#100 : 100

Filter clock is PCLK/32

#101 : 101

Filter clock is PCLK/64

#110 : 110

Filter clock is PCLK/128

#111 : 111

Setting prohibited

End of enumeration elements list.

BCCS : Bus Collision Detection Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

SCI base clock

#01 : 01

SCI base clock frequency divided by 2

#10 : 10

SCI base clock frequency divided by 4

#11 : 11

Setting prohibited

End of enumeration elements list.

RTS : RXDXn Reception Sampling Timing Select
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Rising edge of the 8th cycle of SCI base clock

#01 : 01

Rising edge of the 10th cycle of SCI base clock

#10 : 10

Rising edge of the 12th cycle of SCI base clock

#11 : 11

Rising edge of the 14th cycle of SCI base clock

End of enumeration elements list.


CR3

Control Register 3
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR3 CR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SDST

SDST : Start Frame Detection Start
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Detection of Start Frame is not performed.

#1 : 1

Detection of Start Frame is performed.

End of enumeration elements list.


PCR

Port Control Register
address_offset : 0x25 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR PCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TXDXPS RXDXPS SHARPS

TXDXPS : TXDXn Signal Polarity Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

The polarity of TXDXn signal is not inverted for output.

#1 : 1

The polarity of TXDXn signal is inverted for output.

End of enumeration elements list.

RXDXPS : RXDXn Signal Polarity Select
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

The polarity of RXDXn signal is not inverted for input.

#1 : 1

The polarity of RXDXn signal is inverted for input.

End of enumeration elements list.

SHARPS : TXDXn/RXDXn Pin Multiplexing Select
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

The TXDXn and RXDXn pins are independent.

#1 : 1

The TXDXn and RXDXn signals are multiplexed on the same pin.

End of enumeration elements list.


ICR

Interrupt Control Register
address_offset : 0x26 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICR ICR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BFDIE CF0MIE CF1MIE PIBDIE BCDIE AEDIE

BFDIE : Break Field Low Width Detected Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts on detection of the low width for a Break Field are disabled.

#1 : 1

Interrupts on detection of the low width for a Break Field are enabled.

End of enumeration elements list.

CF0MIE : Control Field 0 Match Detected Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts on detection of a match with Control Field 0 are disabled.

#1 : 1

Interrupts on detection of a match with Control Field 0 are enabled.

End of enumeration elements list.

CF1MIE : Control Field 1 Match Detected Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts on detection of a match with Control Field 1 are disabled.

#1 : 1

Interrupts on detection of a match with Control Field 1 are enabled.

End of enumeration elements list.

PIBDIE : Priority Interrupt Bit Detected Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts on detection of the priority interrupt bit are disabled.

#1 : 1

Interrupts on detection of the priority interrupt bit are enabled.

End of enumeration elements list.

BCDIE : Bus Collision Detected Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts on detection of a bus collision are disabled.

#1 : 1

Interrupts on detection of a bus collision are enabled.

End of enumeration elements list.

AEDIE : Valid Edge Detected Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts on detection of a valid edge are disabled.

#1 : 1

Interrupts on detection of a valid edge are enabled.

End of enumeration elements list.


STR

Status Register
address_offset : 0x27 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STR STR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BFDF CF0MF CF1MF PIBDF BCDF AEDF

BFDF : Break Field Low Width Detection Flag
bits : 0 - -1 (0 bit)
access : read-only

CF0MF : Control Field 0 Match Flag
bits : 1 - 0 (0 bit)
access : read-only

CF1MF : Control Field 1 Match Flag
bits : 2 - 1 (0 bit)
access : read-only

PIBDF : Priority Interrupt Bit Detection Flag
bits : 3 - 2 (0 bit)
access : read-only

BCDF : Bus Collision Detected Flag
bits : 4 - 3 (0 bit)
access : read-only

AEDF : Valid Edge Detection Flag
bits : 5 - 4 (0 bit)
access : read-only


STCR

Status Clear Register
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STCR STCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BFDCL CF0MCL CF1MCL PIBDCL BCDCL AEDCL

BFDCL : BFDF Clear
bits : 0 - -1 (0 bit)
access : read-write

CF0MCL : CF0MF Clear
bits : 1 - 0 (0 bit)
access : read-write

CF1MCL : CF1MF Clear
bits : 2 - 1 (0 bit)
access : read-write

PIBDCL : PIBDF Clear
bits : 3 - 2 (0 bit)
access : read-write

BCDCL : BCDF Clear
bits : 4 - 3 (0 bit)
access : read-write

AEDCL : AEDF Clear
bits : 5 - 4 (0 bit)
access : read-write


CF0DR

Control Field 0 Data Register
address_offset : 0x29 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CF0DR CF0DR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CF0CR

Control Field 0 Compare Enable Register
address_offset : 0x2A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CF0CR CF0CR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CF0CE0 CF0CE1 CF0CE2 CF0CE3 CF0CE4 CF0CE5 CF0CE6 CF0CE7

CF0CE0 : Control Field 0 Bit 0 Compare Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Comparison with bit 0 of Control Field 0 is disabled.

#1 : 1

Comparison with bit 0 of Control Field 0 is enabled.

End of enumeration elements list.

CF0CE1 : Control Field 1 Bit 0 Compare Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Comparison with bit 1 of Control Field 0 is disabled.

#1 : 1

Comparison with bit 1 of Control Field 0 is enabled.

End of enumeration elements list.

CF0CE2 : Control Field 2 Bit 0 Compare Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Comparison with bit 2 of Control Field 0 is disabled.

#1 : 1

Comparison with bit 2 of Control Field 0 is enabled.

End of enumeration elements list.

CF0CE3 : Control Field 3 Bit 0 Compare Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Comparison with bit 3 of Control Field 0 is disabled.

#1 : 1

Comparison with bit 3 of Control Field 0 is enabled.

End of enumeration elements list.

CF0CE4 : Control Field 4 Bit 0 Compare Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Comparison with bit 4 of Control Field 0 is disabled.

#1 : 1

Comparison with bit 4 of Control Field 0 is enabled.

End of enumeration elements list.

CF0CE5 : Control Field 5 Bit 0 Compare Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Comparison with bit 5 of Control Field 0 is disabled.

#1 : 1

Comparison with bit 5 of Control Field 0 is enabled.

End of enumeration elements list.

CF0CE6 : Control Field 6 Bit 0 Compare Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Comparison with bit 6 of Control Field 0 is disabled.

#1 : 1

Comparison with bit 6 of Control Field 0 is enabled.

End of enumeration elements list.

CF0CE7 : Control Field 7 Bit 0 Compare Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Comparison with bit 7 of Control Field 0 is disabled.

#1 : 1

Comparison with bit 7 of Control Field 0 is enabled.

End of enumeration elements list.


CF0RR

Control Field 0 Receive Data Register
address_offset : 0x2B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CF0RR CF0RR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PCF1DR

Primary Control Field 1 Data Register
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCF1DR PCF1DR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

SCF1DR

Secondary Control Field 1 Data Register
address_offset : 0x2D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCF1DR SCF1DR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CF1CR

Control Field 1 Compare Enable Register
address_offset : 0x2E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CF1CR CF1CR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CF1CE0 CF1CE1 CF1CE2 CF1CE3 CF1CE4 CF1CE5 CF1CE6 CF1CE7

CF1CE0 : Control Field 1 Bit 0 Compare Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Comparison with bit 0 of Control Field 1 is disabled.

#1 : 1

Comparison with bit 0 of Control Field 1 is enabled.

End of enumeration elements list.

CF1CE1 : Control Field 1 Bit 1 Compare Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Comparison with bit 1 of Control Field 1 is disabled.

#1 : 1

Comparison with bit 1 of Control Field 1 is enabled.

End of enumeration elements list.

CF1CE2 : Control Field 1 Bit 2 Compare Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Comparison with bit 2 of Control Field 1 is disabled.

#1 : 1

Comparison with bit 2 of Control Field 1 is enabled.

End of enumeration elements list.

CF1CE3 : Control Field 1 Bit 3 Compare Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Comparison with bit 3 of Control Field 1 is disabled.

#1 : 1

Comparison with bit 3 of Control Field 1 is enabled.

End of enumeration elements list.

CF1CE4 : Control Field 1 Bit 4 Compare Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Comparison with bit 4 of Control Field 1 is disabled.

#1 : 1

Comparison with bit 4 of Control Field 1 is enabled.

End of enumeration elements list.

CF1CE5 : Control Field 1 Bit 5 Compare Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Comparison with bit 5 of Control Field 1 is disabled.

#1 : 1

Comparison with bit 5 of Control Field 1 is enabled.

End of enumeration elements list.

CF1CE6 : Control Field 1 Bit 6 Compare Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Comparison with bit 6 of Control Field 1 is disabled.

#1 : 1

Comparison with bit 6 of Control Field 1 is enabled.

End of enumeration elements list.

CF1CE7 : Control Field 1 Bit 7 Compare Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Comparison with bit 7 of Control Field 1 is disabled.

#1 : 1

Comparison with bit 7 of Control Field 1 is enabled.

End of enumeration elements list.


CF1RR

Control Field 1 Receive Data Register
address_offset : 0x2F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CF1RR CF1RR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TDR

Transmit Data Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDR TDR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TCR

Timer Control Register
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TCST

TCST : Timer Count Start
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Stops the timer counting

#1 : 1

Starts the timer counting

End of enumeration elements list.


TMR

Timer Mode Register
address_offset : 0x31 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR TMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TOMS TWRC TCSS

TOMS : Timer Operating Mode Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Timer mode

#01 : 01

Break Field low width determination mode

#10 : 10

Break Field low width output mode

#11 : 11

Setting prohibited

End of enumeration elements list.

TWRC : Counter Write Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data is written to the reload register and counter

#1 : 1

Data is written to the reload register only

End of enumeration elements list.

TCSS : Timer Count Clock Source Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#000 : 000

PCLK

#001 : 001

PCLK/2

#010 : 010

PCLK/4

#011 : 011

PCLK/8

#100 : 100

PCLK/16

#101 : 101

PCLK/32

#110 : 110

PCLK/64

#111 : 111

PCLK/128

End of enumeration elements list.


TPRE

Timer Prescaler Register
address_offset : 0x32 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPRE TPRE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TCNT

Timer Count Register
address_offset : 0x33 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCNT TCNT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

SSR

Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0, and MMR.MANEN = 0)
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR SSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MPBT MPB TEND PER FER ORER RDRF TDRE

MPBT : Multi-Processor Bit Transfer
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Data transmission cycle

#1 : 1

ID transmission cycle

End of enumeration elements list.

MPB : Multi-Processor
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Data transmission cycle

#1 : 1

ID transmission cycle

End of enumeration elements list.

TEND : Transmit End Flag
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : 0

A character is being transmitted

#1 : 1

Character transfer is complete

End of enumeration elements list.

PER : Parity Error Flag
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

No parity error occurred

#1 : 1

Parity error occurred

End of enumeration elements list.

FER : Framing Error Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

No framing error occurred

#1 : 1

Framing error occurred

End of enumeration elements list.

ORER : Overrun Error Flag
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

No overrun error occurred

#1 : 1

Overrun error occurred

End of enumeration elements list.

RDRF : Receive Data Full Flag
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

No received data in RDR register

#1 : 1

Received data in RDR register

End of enumeration elements list.

TDRE : Transmit Data Empty Flag
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmit data in TDR register

#1 : 1

No transmit data in TDR register

End of enumeration elements list.


SSR_SMCI

Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1, and MMR.MANEN = 0)
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SSR
reset_Mask : 0x0

SSR_SMCI SSR_SMCI read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MPBT MPB TEND PER ERS ORER RDRF TDRE

MPBT : Multi-Processor Bit Transfer
bits : 0 - -1 (0 bit)
access : read-write

MPB : Multi-Processor
bits : 1 - 0 (0 bit)
access : read-only

TEND : Transmit End Flag
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : 0

A character is being transmitted

#1 : 1

Character transfer is complete

End of enumeration elements list.

PER : Parity Error Flag
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

No parity error occurred

#1 : 1

Parity error occurred

End of enumeration elements list.

ERS : Error Signal Status Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

No low error signal response

#1 : 1

Low error signal response occurred

End of enumeration elements list.

ORER : Overrun Error Flag
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

No overrun error occurred

#1 : 1

Overrun error occurred

End of enumeration elements list.

RDRF : Receive Data Full Flag
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

No received data in RDR register

#1 : 1

Received data in RDR register

End of enumeration elements list.

TDRE : Transmit Data Empty Flag
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmit data in TDR register

#1 : 1

No transmit data in TDR register

End of enumeration elements list.


RDR

Receive Data Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDR RDR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

SCMR

Smart Card Mode Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMR SCMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SMIF SINV SDIR CHR1 BCP2

SMIF : Smart Card Interface Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode)

#1 : 1

Smart card interface mode

End of enumeration elements list.

SINV : Transmitted/Received Data Invert
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

TDR contents are transmitted as they are. Received data is stored as received in the RDR register.

#1 : 1

TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register.

End of enumeration elements list.

SDIR : Transmitted/Received Data Transfer Direction
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transfer LSB-first

#1 : 1

Transfer MSB-first

End of enumeration elements list.

CHR1 : Character Length 1
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

SMR.CHR = 0: Transmit/receive in 9-bit data length SMR.CHR = 1: Transmit/receive in 9-bit data length

#1 : 1

SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) SMR.CHR = 1: Transmit/receive in 7-bit data length

End of enumeration elements list.

BCP2 : Base Clock Pulse 2
bits : 7 - 6 (0 bit)
access : read-write


SEMR

Serial Extended Mode Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEMR SEMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACS0 PADIS BRME ABCSE ABCS NFEN BGDM RXDESEL

ACS0 : Asynchronous Mode Clock Source Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

External clock input

#1 : 1

Logical AND of compare matches output from the internal GPT. These bit for the other SCI channels than SCIn (n = 1, 2) are reserved.

End of enumeration elements list.

PADIS : Preamble function Disable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Preamble output function is enabled

#1 : 1

Preamble output function is disabled These bits for the other SCI channels than SCIn (n = 0, 3 to 9) are reserved.

End of enumeration elements list.

BRME : Bit Rate Modulation Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable bit rate modulation function

#1 : 1

Enable bit rate modulation function

End of enumeration elements list.

ABCSE : Asynchronous Mode Extended Base Clock Select 1
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register

#1 : 1

Baud rate is 6 base clock cycles for 1-bit period These bits for the other SCI channels than SCIn (n = 0, 3 to 9) are reserved.

End of enumeration elements list.

ABCS : Asynchronous Mode Base Clock Select
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Select 16 base clock cycles for 1-bit period

#1 : 1

Select 8 base clock cycles for 1-bit period

End of enumeration elements list.

NFEN : Digital Noise Filter Function Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals

#1 : 1

In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals

End of enumeration elements list.

BGDM : Baud Rate Generator Double-Speed Mode Select
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Output clock from baud rate generator with normal frequency

#1 : 1

Output clock from baud rate generator with doubled frequency

End of enumeration elements list.

RXDESEL : Asynchronous Start Bit Edge Detection Select
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Detect low level on RXDn pin as start bit

#1 : 1

Detect falling edge of RXDn pin as start bit

End of enumeration elements list.


SNFR

Noise Filter Setting Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNFR SNFR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NFCS

NFCS : Noise Filter Clock Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

In asynchronous mode: Use clock signal divided by 1 with noise filter In simple IIC mode: Setting prohibited

#001 : 001

In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 1 with noise filter

#010 : 010

In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 2 with noise filter

#011 : 011

In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 4 with noise filter

#100 : 100

In asynchronous mode: Setting prohibited In simple IIC mode: Use clock signal divided by 8 with noise filter

: Others

Setting prohibited

End of enumeration elements list.


SIMR1

IIC Mode Register 1
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIMR1 SIMR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IICM IICDL

IICM : Simple IIC Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode

#1 : 1

SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited

End of enumeration elements list.

IICDL : SDAn Delay Output Select
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No output delay

: Others

(IICDL - 1) to (IICDL) cycles

End of enumeration elements list.


SIMR2

IIC Mode Register 2
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIMR2 SIMR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IICINTM IICCSC IICACKT

IICINTM : IIC Interrupt Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Use ACK/NACK interrupts

#1 : 1

Use reception and transmission interrupts

End of enumeration elements list.

IICCSC : Clock Synchronization
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not synchronize with clock signal

#1 : 1

Synchronize with clock signal

End of enumeration elements list.

IICACKT : ACK Transmission Data
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

ACK transmission

#1 : 1

NACK transmission and ACK/NACK reception

End of enumeration elements list.


SIMR3

IIC Mode Register 3
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIMR3 SIMR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IICSTAREQ IICRSTAREQ IICSTPREQ IICSTIF IICSDAS IICSCLS

IICSTAREQ : Start Condition Generation
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not generate start condition

#1 : 1

Generate start condition

End of enumeration elements list.

IICRSTAREQ : Restart Condition Generation
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not generate restart condition

#1 : 1

Generate restart condition

End of enumeration elements list.

IICSTPREQ : Stop Condition Generation
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not generate stop condition

#1 : 1

Generate stop condition

End of enumeration elements list.

IICSTIF : Issuing of Start, Restart, or Stop Condition Completed Flag
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

No requests are being made for generating conditions, or a condition is being generated

#1 : 1

Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0

End of enumeration elements list.

IICSDAS : SDAn Output Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

Output serial data

#01 : 01

Generate start, restart, or stop condition

#10 : 10

Output low on SDAn pin

#11 : 11

Drive SDAn pin to high-impedance state

End of enumeration elements list.

IICSCLS : SCLn Output Select
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Output serial clock

#01 : 01

Generate start, restart, or stop condition

#10 : 10

Output low on SCLn pin

#11 : 11

Drive SCLn pin to high-impedance state

End of enumeration elements list.


SISR

IIC Status Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SISR SISR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IICACKR

IICACKR : ACK Reception Data Flag
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

ACK received

#1 : 1

NACK received

End of enumeration elements list.


SPMR

SPI Mode Register
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPMR SPMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SSE CTSE MSS CSTPEN MFF CKPOL CKPH

SSE : SSn Pin Function Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable SSn pin function

#1 : 1

Enable SSn pin function

End of enumeration elements list.

CTSE : CTS Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable CTS function (enable RTS output function)

#1 : 1

Enable CTS function

End of enumeration elements list.

MSS : Master Slave Select
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Transmit through TXDn pin and receive through RXDn pin (master mode)

#1 : 1

Receive through TXDn pin and transmit through RXDn pin (slave mode)

End of enumeration elements list.

CSTPEN : CTS external pin Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Alternate setting to use CTS and RTS functions as either one terminal

#1 : 1

Dedicated setting for separately using CTS and RTS functions with 2 terminals These bits for the other SCI channels than SCIn (n = 0, 3 to 9) are reserved.

End of enumeration elements list.

MFF : Mode Fault Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

No mode fault error

#1 : 1

Mode fault error

End of enumeration elements list.

CKPOL : Clock Polarity Select
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not invert clock polarity

#1 : 1

Invert clock polarity

End of enumeration elements list.

CKPH : Clock Phase Select
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not delay clock

#1 : 1

Delay clock

End of enumeration elements list.


TDRHL

Transmit Data Register for Non-Manchester mode (MMR.MANEN = 0)
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : FTDRHL
reset_Mask : 0x0

TDRHL TDRHL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDAT

TDAT : Serial Transmit Data
bits : 0 - 7 (8 bit)
access : read-write



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