\n
address_offset : 0x0 Bytes (0x0)
size : 0x12 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x13 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x18 Bytes (0x0)
size : 0x7 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
DMA Source Address Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Transfer Mode Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCTG : Transfer Request Source Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Software request
#01 : 01
Hardware request
#10 : 10
Setting prohibited
#11 : 11
Setting prohibited
End of enumeration elements list.
SZ : Transfer Data Size Select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : 00
8 bits
#01 : 01
16 bits
#10 : 10
32 bits
#11 : 11
Setting prohibited
End of enumeration elements list.
TKP : Transfer Keeping
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transfer is stopped by completion of specified total number of transfer operations.
#1 : 1
Transfer is not stopped by completion of specified total number of transfer operations. (free-running)
End of enumeration elements list.
DTS : Repeat Area Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#00 : 00
The destination is specified as the repeat area or block area
#01 : 01
The source is specified as the repeat area or block area
#10 : 10
The repeat area or block area is not specified
#11 : 11
Setting prohibited
End of enumeration elements list.
MD : Transfer Mode Select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#00 : 00
Normal transfer
#01 : 01
Repeat transfer
#10 : 10
Block transfer
#11 : 11
Repeat-block transfer
End of enumeration elements list.
DMA Interrupt Setting Register
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DARIE : Destination Address Extended Repeat Area Overflow Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables an interrupt request for an extended repeat area overflow on the destination address
#1 : 1
Enables an interrupt request for an extended repeat area overflow on the destination address
End of enumeration elements list.
SARIE : Source Address Extended Repeat Area Overflow Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables an interrupt request for an extended repeat area overflow on the source address
#1 : 1
Enables an interrupt request for an extended repeat area overflow on the source address
End of enumeration elements list.
RPTIE : Repeat Size End Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables the repeat size end interrupt request
#1 : 1
Enables the repeat size end interrupt request
End of enumeration elements list.
ESIE : Transfer Escape End Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables the transfer escape end interrupt request
#1 : 1
Enables the transfer escape end interrupt request
End of enumeration elements list.
DTIE : Transfer End Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables the transfer end interrupt request
#1 : 1
Enables the transfer end interrupt request
End of enumeration elements list.
DMA Address Mode Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DARA : Destination Address Extended Repeat Area
bits : 0 - 3 (4 bit)
access : read-write
DADR : Destination Address Update Select After Reload
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Only reloading
#1 : 1
Add index after reloading
End of enumeration elements list.
DM : Destination Address Update Mode
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
Destination address is fixed
#01 : 01
Offset addition
#10 : 10
Destination address is incremented
#11 : 11
Destination address is decremented
End of enumeration elements list.
SARA : Source Address Extended Repeat Area
bits : 8 - 11 (4 bit)
access : read-write
SADR : Source Address Update Select After Reload
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Only reloading
#1 : 1
Add index after reloading
End of enumeration elements list.
SM : Source Address Update Mode
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#00 : 00
Source address is fixed
#01 : 01
Offset addition
#10 : 10
Source address is incremented
#11 : 11
Source address is decremented
End of enumeration elements list.
DMA Offset Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Transfer Enable Register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTE : DMA Transfer Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables DMA transfer
#1 : 1
Enables DMA transfer
End of enumeration elements list.
DMA Software Start Register
address_offset : 0x1D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWREQ : DMA Software Start
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA transfer is not requested
#1 : 1
DMA transfer is requested
End of enumeration elements list.
CLRS : DMA Software Start Bit Auto Clear Select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
SWREQ bit is cleared after DMA transfer is started by software
#1 : 1
SWREQ bit is not cleared after DMA transfer is started by software
End of enumeration elements list.
DMA Status Register
address_offset : 0x1E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ESIF : Transfer Escape End Interrupt Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
A transfer escape end interrupt has not been generated
#1 : 1
A transfer escape end interrupt has been generated
End of enumeration elements list.
DTIF : Transfer End Interrupt Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
A transfer end interrupt has not been generated
#1 : 1
A transfer end interrupt has been generated
End of enumeration elements list.
ACT : DMAC Active Flag
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
DMAC is in the idle state
#1 : 1
DMAC is operating
End of enumeration elements list.
DMA Source Reload Address Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Destination Reload Address Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Source Buffer Size Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMSBSL : Functions as data transfer counter in repeat-block transfer mode
bits : 0 - 14 (15 bit)
access : read-write
DMSBSH : Specifies the repeat-area size in repeat-block transfer mode
bits : 16 - 30 (15 bit)
access : read-write
DMA Destination Buffer Size Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMDBSL : Functions as data transfer counter in repeat-block transfer mode
bits : 0 - 14 (15 bit)
access : read-write
DMDBSH : Specifies the repeat-area size in repeat-block transfer mode
bits : 16 - 30 (15 bit)
access : read-write
DMA Destination Address Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Transfer Count Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMCRAL : Lower bits of transfer count
bits : 0 - 14 (15 bit)
access : read-write
DMCRAH : Upper bits of transfer count
bits : 16 - 24 (9 bit)
access : read-write
DMA Block Transfer Count Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMCRBL : Functions as a number of block, repeat or repeat-block transfer counter.
bits : 0 - 14 (15 bit)
access : read-write
DMCRBH : Specifies the number of block, repeat or repeat-block transfer operations.
bits : 16 - 30 (15 bit)
access : read-write
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