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ICU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x100 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x120 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x130 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x140 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1A0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x200 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x280 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x300 Bytes (0x0)
size : 0x180 byte (0x0)
mem_usage : registers
protection :

Registers

IRQCR0

IRQCR1

NMICR

NMIER

NMICLR

NMISR

WUPEN0

WUPEN1

IRQCR2

SELSR0

DELSR0

DELSR1

DELSR2

DELSR3

DELSR4

DELSR5

DELSR6

DELSR7

IRQCR3

IELSR0

IELSR1

IELSR2

IELSR3

IELSR4

IELSR5

IELSR6

IELSR7

IELSR8

IELSR9

IELSR10

IELSR11

IELSR12

IELSR13

IELSR14

IELSR15

IELSR16

IELSR17

IELSR18

IELSR19

IELSR20

IELSR21

IELSR22

IELSR23

IELSR24

IELSR25

IELSR26

IELSR27

IELSR28

IELSR29

IELSR30

IELSR31

IELSR32

IELSR33

IELSR34

IELSR35

IELSR36

IELSR37

IELSR38

IELSR39

IELSR40

IELSR41

IELSR42

IELSR43

IELSR44

IELSR45

IELSR46

IELSR47

IELSR48

IELSR49

IELSR50

IELSR51

IELSR52

IELSR53

IELSR54

IELSR55

IELSR56

IELSR57

IELSR58

IELSR59

IELSR60

IELSR61

IELSR62

IELSR63

IRQCR4

IELSR64

IELSR65

IELSR66

IELSR67

IELSR68

IELSR69

IELSR70

IELSR71

IELSR72

IELSR73

IELSR74

IELSR75

IELSR76

IELSR77

IELSR78

IELSR79

IELSR80

IELSR81

IELSR82

IELSR83

IELSR84

IELSR85

IELSR86

IELSR87

IELSR88

IELSR89

IELSR90

IELSR91

IELSR92

IELSR93

IELSR94

IELSR95

IRQCR5

IRQCR6

IRQCR7

IRQCR8

IRQCR9

IRQCR10

IRQCR11

IRQCR12

IRQCR13

IRQCR14

IRQCR15


IRQCR0

IRQ Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR0 IRQCR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IRQCR1

IRQ Control Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR1 IRQCR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


NMICR

NMI Pin Interrupt Control Register
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMICR NMICR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NMIMD NFCLKSEL NFLTEN

NMIMD : NMI Detection Set
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Falling edge

#1 : 1

Rising edge

End of enumeration elements list.

NFCLKSEL : NMI Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

NFLTEN : NMI Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.


NMIER

Non-Maskable Interrupt Enable Register
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMIER NMIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IWDTEN WDTEN LVD1EN LVD2EN OSTEN NMIEN RPEEN RECCEN BUSMEN TZFEN CPEEN

IWDTEN : IWDT Underflow/Refresh Error Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled.

End of enumeration elements list.

WDTEN : WDT Underflow/Refresh Error Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

LVD1EN : Voltage monitor 1 Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

LVD2EN : Voltage monitor 2 Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

OSTEN : Oscillation Stop Detection Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

NMIEN : NMI Pin Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RPEEN : SRAM Parity Error Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RECCEN : SRAM ECC Error Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

BUSMEN : MPU Bus Master Error Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

TZFEN :
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

CPEEN :
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.


NMICLR

Non-Maskable Interrupt Status Clear Register
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMICLR NMICLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IWDTCLR WDTCLR LVD1CLR LVD2CLR OSTCLR NMICLR RPECLR RECCCLR BUSMCLR TZFCLR CPECLR

IWDTCLR : IWDT Clear
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.IWDTST flag

End of enumeration elements list.

WDTCLR : WDT Clear
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.WDTST flag

End of enumeration elements list.

LVD1CLR : LVD1 Clear
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.LVD1ST flag

End of enumeration elements list.

LVD2CLR : LVD2 Clear
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.LVD2ST flag.

End of enumeration elements list.

OSTCLR : OST Clear
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.OSTST flag

End of enumeration elements list.

NMICLR : NMI Clear
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.NMIST flag

End of enumeration elements list.

RPECLR : SRAM Parity Error Clear
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.RPEST flag

End of enumeration elements list.

RECCCLR : SRAM ECC Error Clear
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.RECCST flag

End of enumeration elements list.

BUSMCLR : Bus Master Error Clear
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.BUSMST flag

End of enumeration elements list.

TZFCLR :
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.TZFCLR flag

End of enumeration elements list.

CPECLR :
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the NMISR.CPECLR flag

End of enumeration elements list.


NMISR

Non-Maskable Interrupt Status Register
address_offset : 0x140 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NMISR NMISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IWDTST WDTST LVD1ST LVD2ST OSTST NMIST RPEST RECCST BUSMST TZFST CPEST

IWDTST : IWDT Underflow/Refresh Error Status Flag
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.

WDTST : WDT Underflow/Refresh Error Status Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.

LVD1ST : Voltage Monitor 1 Interrupt Status Flag
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.

LVD2ST : Voltage Monitor 2 Interrupt Status Flag
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.

OSTST : Oscillation Stop Detection Interrupt Status Flag
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested for main oscillation stop

#1 : 1

Interrupt requested for main oscillation stop

End of enumeration elements list.

NMIST : NMI Status Flag
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.

RPEST : SRAM Parity Error Interrupt Status Flag
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.

RECCST : SRAM ECC Error Interrupt Status Flag
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.

BUSMST : MPU Bus Master Error Interrupt Status Flag
bits : 11 - 10 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.

TZFST :
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.

CPEST :
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt not requested

#1 : 1

Interrupt requested

End of enumeration elements list.


WUPEN0

Wake Up Interrupt Enable Register 0
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WUPEN0 WUPEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQWUPEN IWDTWUPEN LVD1WUPEN LVD2WUPEN RTCALMWUPEN RTCPRDWUPEN USBFS0WUPEN AGT1UDWUPEN AGT1CAWUPEN AGT1CBWUPEN IIC0WUPEN

IRQWUPEN : IRQn interrupt Software standby returns enable bit
bits : 0 - 14 (15 bit)
access : read-write

Enumeration:

#0 : 0

Software standby returns by IRQn interrupt is disabled

#1 : 1

Software standby returns by IRQn interrupt is enabled

End of enumeration elements list.

IWDTWUPEN : IWDT interrupt Software standby returns enable bit
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software standby returns by IWDT interrupt is disabled

#1 : 1

Software standby returns by IWDT interrupt is enabled

End of enumeration elements list.

LVD1WUPEN : LVD1 interrupt Software standby returns enable bit
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software standby returns by LVD1 interrupt is disabled

#1 : 1

Software standby returns by LVD1 interrupt is enabled

End of enumeration elements list.

LVD2WUPEN : LVD2 Interrupt Software Standby Return Enable bit
bits : 19 - 18 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software standby returns by LVD2 interrupt is disabled

#1 : 1

Software standby returns by LVD2 interrupt is enabled

End of enumeration elements list.

RTCALMWUPEN : RTC Alarm interrupt Software Standby Return Enable bit
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software standby returns by RTC alarm interrupt is disabled

#1 : 1

Software standby returns by RTC alarm interrupt is enabled

End of enumeration elements list.

RTCPRDWUPEN : RTC Period Interrupt Software Standby Return Enable bit
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software standby returns by RTC period interrupt is disabled

#1 : 1

Software standby returns by RTC period interrupt is enabled

End of enumeration elements list.

USBFS0WUPEN : USBFS0 Interrupt Software Standby Return Enable bit
bits : 27 - 26 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software standby returns by USBFS0 interrupt is disabled

#1 : 1

Software standby returns by USBFS0 interrupt is enabled

End of enumeration elements list.

AGT1UDWUPEN : AGT1 Underflow Interrupt Software Standby Return Enable bit
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software standby returns by AGT1 underflow interrupt is disabled

#1 : 1

Software standby returns by AGT1 underflow interrupt is enabled

End of enumeration elements list.

AGT1CAWUPEN : AGT1 Compare Match A Interrupt Software Standby Return Enable bit
bits : 29 - 28 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software standby returns by AGT1 compare match A interrupt is disabled

#1 : 1

Software standby returns by AGT1 compare match A interrupt is enabled

End of enumeration elements list.

AGT1CBWUPEN : AGT1 Compare Match B Interrupt Software Standby Return Enable bit
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software standby returns by AGT1 compare match B interrupt is disabled

#1 : 1

Software standby returns by AGT1 compare match B interrupt is enabled

End of enumeration elements list.

IIC0WUPEN : IIC0 Address Match Interrupt Software Standby Return Enable bit
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software standby returns by IIC0 address match interrupt is disabled

#1 : 1

Software standby returns by IIC0 address match interrupt is enabled

End of enumeration elements list.


WUPEN1

Wake Up interrupt enable register 1
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WUPEN1 WUPEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AGT3UDWUPEN AGT3CAWUPEN AGT3CBWUPEN

AGT3UDWUPEN : AGT3 Underflow Interrupt Software Standby Return Enable bit
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software standby returns by AGT3 underflow interrupt is disabled

#1 : 1

Software standby returns by AGT3 underflow interrupt is enabled

End of enumeration elements list.

AGT3CAWUPEN : AGT3 Compare Match A Interrupt Software Standby Return Enable bit
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software standby returns by AGT3 compare match A interrupt is disabled

#1 : 1

Software standby returns by AGT3 compare match A interrupt is enabled

End of enumeration elements list.

AGT3CBWUPEN : AGT3 Compare Match B Interrupt Software Standby Return Enable bit
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software standby returns by AGT3 compare match B interrupt is disabled

#1 : 1

Software standby returns by AGT3 compare match B interrupt is enabled

End of enumeration elements list.


IRQCR2

IRQ Control Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR2 IRQCR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


SELSR0

SYS Event Link Setting Register
address_offset : 0x200 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SELSR0 SELSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DELSR0

DMAC Event Link Setting Register %s
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELSR0 DELSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DELS IR

DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0x00 : 0x00

Disable interrupts to the associated DMAC module

: Others

Event signal number to be linked. For details, see .

End of enumeration elements list.

IR : DMAC Activation Request Status flag
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : 0

No DMAC activation request occurred

#1 : 1

DMAC activation request occurred.

End of enumeration elements list.


DELSR1

DMAC Event Link Setting Register %s
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELSR1 DELSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DELS IR

DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0x00 : 0x00

Disable interrupts to the associated DMAC module

: Others

Event signal number to be linked. For details, see .

End of enumeration elements list.

IR : DMAC Activation Request Status flag
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : 0

No DMAC activation request occurred

#1 : 1

DMAC activation request occurred.

End of enumeration elements list.


DELSR2

DMAC Event Link Setting Register %s
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELSR2 DELSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DELS IR

DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0x00 : 0x00

Disable interrupts to the associated DMAC module

: Others

Event signal number to be linked. For details, see .

End of enumeration elements list.

IR : DMAC Activation Request Status flag
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : 0

No DMAC activation request occurred

#1 : 1

DMAC activation request occurred.

End of enumeration elements list.


DELSR3

DMAC Event Link Setting Register %s
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELSR3 DELSR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DELS IR

DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0x00 : 0x00

Disable interrupts to the associated DMAC module

: Others

Event signal number to be linked. For details, see .

End of enumeration elements list.

IR : DMAC Activation Request Status flag
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : 0

No DMAC activation request occurred

#1 : 1

DMAC activation request occurred.

End of enumeration elements list.


DELSR4

DMAC Event Link Setting Register %s
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELSR4 DELSR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DELS IR

DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0x00 : 0x00

Disable interrupts to the associated DMAC module

: Others

Event signal number to be linked. For details, see .

End of enumeration elements list.

IR : DMAC Activation Request Status flag
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : 0

No DMAC activation request occurred

#1 : 1

DMAC activation request occurred.

End of enumeration elements list.


DELSR5

DMAC Event Link Setting Register %s
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELSR5 DELSR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DELS IR

DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0x00 : 0x00

Disable interrupts to the associated DMAC module

: Others

Event signal number to be linked. For details, see .

End of enumeration elements list.

IR : DMAC Activation Request Status flag
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : 0

No DMAC activation request occurred

#1 : 1

DMAC activation request occurred.

End of enumeration elements list.


DELSR6

DMAC Event Link Setting Register %s
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELSR6 DELSR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DELS IR

DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0x00 : 0x00

Disable interrupts to the associated DMAC module

: Others

Event signal number to be linked. For details, see .

End of enumeration elements list.

IR : DMAC Activation Request Status flag
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : 0

No DMAC activation request occurred

#1 : 1

DMAC activation request occurred.

End of enumeration elements list.


DELSR7

DMAC Event Link Setting Register %s
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELSR7 DELSR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DELS IR

DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0x00 : 0x00

Disable interrupts to the associated DMAC module

: Others

Event signal number to be linked. For details, see .

End of enumeration elements list.

IR : DMAC Activation Request Status flag
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : 0

No DMAC activation request occurred

#1 : 1

DMAC activation request occurred.

End of enumeration elements list.


IRQCR3

IRQ Control Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR3 IRQCR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IELSR0

ICU Event Link Setting Register %s
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR0 IELSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR1

ICU Event Link Setting Register %s
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR1 IELSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR2

ICU Event Link Setting Register %s
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR2 IELSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR3

ICU Event Link Setting Register %s
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR3 IELSR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR4

ICU Event Link Setting Register %s
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR4 IELSR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR5

ICU Event Link Setting Register %s
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR5 IELSR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR6

ICU Event Link Setting Register %s
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR6 IELSR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR7

ICU Event Link Setting Register %s
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR7 IELSR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR8

ICU Event Link Setting Register %s
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR8 IELSR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR9

ICU Event Link Setting Register %s
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR9 IELSR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR10

ICU Event Link Setting Register %s
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR10 IELSR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR11

ICU Event Link Setting Register %s
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR11 IELSR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR12

ICU Event Link Setting Register %s
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR12 IELSR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR13

ICU Event Link Setting Register %s
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR13 IELSR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR14

ICU Event Link Setting Register %s
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR14 IELSR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR15

ICU Event Link Setting Register %s
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR15 IELSR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR16

ICU Event Link Setting Register %s
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR16 IELSR16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR17

ICU Event Link Setting Register %s
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR17 IELSR17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR18

ICU Event Link Setting Register %s
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR18 IELSR18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR19

ICU Event Link Setting Register %s
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR19 IELSR19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR20

ICU Event Link Setting Register %s
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR20 IELSR20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR21

ICU Event Link Setting Register %s
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR21 IELSR21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR22

ICU Event Link Setting Register %s
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR22 IELSR22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR23

ICU Event Link Setting Register %s
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR23 IELSR23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR24

ICU Event Link Setting Register %s
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR24 IELSR24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR25

ICU Event Link Setting Register %s
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR25 IELSR25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR26

ICU Event Link Setting Register %s
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR26 IELSR26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR27

ICU Event Link Setting Register %s
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR27 IELSR27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR28

ICU Event Link Setting Register %s
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR28 IELSR28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR29

ICU Event Link Setting Register %s
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR29 IELSR29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR30

ICU Event Link Setting Register %s
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR30 IELSR30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR31

ICU Event Link Setting Register %s
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR31 IELSR31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR32

ICU Event Link Setting Register %s
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR32 IELSR32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR33

ICU Event Link Setting Register %s
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR33 IELSR33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR34

ICU Event Link Setting Register %s
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR34 IELSR34 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR35

ICU Event Link Setting Register %s
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR35 IELSR35 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR36

ICU Event Link Setting Register %s
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR36 IELSR36 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR37

ICU Event Link Setting Register %s
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR37 IELSR37 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR38

ICU Event Link Setting Register %s
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR38 IELSR38 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR39

ICU Event Link Setting Register %s
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR39 IELSR39 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR40

ICU Event Link Setting Register %s
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR40 IELSR40 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR41

ICU Event Link Setting Register %s
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR41 IELSR41 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR42

ICU Event Link Setting Register %s
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR42 IELSR42 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR43

ICU Event Link Setting Register %s
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR43 IELSR43 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR44

ICU Event Link Setting Register %s
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR44 IELSR44 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR45

ICU Event Link Setting Register %s
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR45 IELSR45 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR46

ICU Event Link Setting Register %s
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR46 IELSR46 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR47

ICU Event Link Setting Register %s
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR47 IELSR47 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR48

ICU Event Link Setting Register %s
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR48 IELSR48 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR49

ICU Event Link Setting Register %s
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR49 IELSR49 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR50

ICU Event Link Setting Register %s
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR50 IELSR50 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR51

ICU Event Link Setting Register %s
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR51 IELSR51 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR52

ICU Event Link Setting Register %s
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR52 IELSR52 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR53

ICU Event Link Setting Register %s
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR53 IELSR53 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR54

ICU Event Link Setting Register %s
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR54 IELSR54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR55

ICU Event Link Setting Register %s
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR55 IELSR55 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR56

ICU Event Link Setting Register %s
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR56 IELSR56 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR57

ICU Event Link Setting Register %s
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR57 IELSR57 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR58

ICU Event Link Setting Register %s
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR58 IELSR58 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR59

ICU Event Link Setting Register %s
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR59 IELSR59 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR60

ICU Event Link Setting Register %s
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR60 IELSR60 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR61

ICU Event Link Setting Register %s
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR61 IELSR61 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR62

ICU Event Link Setting Register %s
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR62 IELSR62 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR63

ICU Event Link Setting Register %s
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR63 IELSR63 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQCR4

IRQ Control Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR4 IRQCR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IELSR64

ICU Event Link Setting Register %s
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR64 IELSR64 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR65

ICU Event Link Setting Register %s
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR65 IELSR65 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR66

ICU Event Link Setting Register %s
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR66 IELSR66 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR67

ICU Event Link Setting Register %s
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR67 IELSR67 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR68

ICU Event Link Setting Register %s
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR68 IELSR68 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR69

ICU Event Link Setting Register %s
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR69 IELSR69 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR70

ICU Event Link Setting Register %s
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR70 IELSR70 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR71

ICU Event Link Setting Register %s
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR71 IELSR71 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR72

ICU Event Link Setting Register %s
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR72 IELSR72 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR73

ICU Event Link Setting Register %s
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR73 IELSR73 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR74

ICU Event Link Setting Register %s
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR74 IELSR74 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR75

ICU Event Link Setting Register %s
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR75 IELSR75 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR76

ICU Event Link Setting Register %s
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR76 IELSR76 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR77

ICU Event Link Setting Register %s
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR77 IELSR77 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR78

ICU Event Link Setting Register %s
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR78 IELSR78 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR79

ICU Event Link Setting Register %s
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR79 IELSR79 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR80

ICU Event Link Setting Register %s
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR80 IELSR80 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR81

ICU Event Link Setting Register %s
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR81 IELSR81 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR82

ICU Event Link Setting Register %s
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR82 IELSR82 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR83

ICU Event Link Setting Register %s
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR83 IELSR83 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR84

ICU Event Link Setting Register %s
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR84 IELSR84 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR85

ICU Event Link Setting Register %s
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR85 IELSR85 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR86

ICU Event Link Setting Register %s
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR86 IELSR86 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR87

ICU Event Link Setting Register %s
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR87 IELSR87 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR88

ICU Event Link Setting Register %s
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR88 IELSR88 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR89

ICU Event Link Setting Register %s
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR89 IELSR89 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR90

ICU Event Link Setting Register %s
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR90 IELSR90 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR91

ICU Event Link Setting Register %s
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR91 IELSR91 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR92

ICU Event Link Setting Register %s
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR92 IELSR92 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR93

ICU Event Link Setting Register %s
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR93 IELSR93 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR94

ICU Event Link Setting Register %s
address_offset : 0x478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR94 IELSR94 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IELSR95

ICU Event Link Setting Register %s
address_offset : 0x47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IELSR95 IELSR95 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQCR5

IRQ Control Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR5 IRQCR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IRQCR6

IRQ Control Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR6 IRQCR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IRQCR7

IRQ Control Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR7 IRQCR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IRQCR8

IRQ Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR8 IRQCR8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IRQCR9

IRQ Control Register
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR9 IRQCR9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IRQCR10

IRQ Control Register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR10 IRQCR10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IRQCR11

IRQ Control Register
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR11 IRQCR11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IRQCR12

IRQ Control Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR12 IRQCR12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IRQCR13

IRQ Control Register
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR13 IRQCR13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IRQCR14

IRQ Control Register
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR14 IRQCR14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.


IRQCR15

IRQ Control Register
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCR15 IRQCR15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQMD FCLKSEL FLTEN

IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Falling edge

#01 : 01

Rising edge

#10 : 10

Rising and falling edges

#11 : 11

Low level

End of enumeration elements list.

FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLKB

#01 : 01

PCLKB/8

#10 : 10

PCLKB/32

#11 : 11

PCLKB/64

End of enumeration elements list.

FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled

#1 : 1

Digital filter is enabled.

End of enumeration elements list.



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