\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x100 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x120 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x130 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x140 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x1A0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x200 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x280 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x300 Bytes (0x0)
size : 0x180 byte (0x0)
mem_usage : registers
protection :
IRQ Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
NMI Pin Interrupt Control Register
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMIMD : NMI Detection Set
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Falling edge
#1 : 1
Rising edge
End of enumeration elements list.
NFCLKSEL : NMI Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
NFLTEN : NMI Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
Non-Maskable Interrupt Enable Register
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IWDTEN : IWDT Underflow/Refresh Error Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
WDTEN : WDT Underflow/Refresh Error Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
LVD1EN : Voltage monitor 1 Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
LVD2EN : Voltage monitor 2 Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
OSTEN : Oscillation Stop Detection Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
NMIEN : NMI Pin Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
RPEEN : SRAM Parity Error Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
RECCEN : SRAM ECC Error Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BUSMEN : MPU Bus Master Error Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
TZFEN :
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CPEEN :
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
Non-Maskable Interrupt Status Clear Register
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IWDTCLR : IWDT Clear
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear the NMISR.IWDTST flag
End of enumeration elements list.
WDTCLR : WDT Clear
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear the NMISR.WDTST flag
End of enumeration elements list.
LVD1CLR : LVD1 Clear
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear the NMISR.LVD1ST flag
End of enumeration elements list.
LVD2CLR : LVD2 Clear
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear the NMISR.LVD2ST flag.
End of enumeration elements list.
OSTCLR : OST Clear
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear the NMISR.OSTST flag
End of enumeration elements list.
NMICLR : NMI Clear
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear the NMISR.NMIST flag
End of enumeration elements list.
RPECLR : SRAM Parity Error Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear the NMISR.RPEST flag
End of enumeration elements list.
RECCCLR : SRAM ECC Error Clear
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear the NMISR.RECCST flag
End of enumeration elements list.
BUSMCLR : Bus Master Error Clear
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear the NMISR.BUSMST flag
End of enumeration elements list.
TZFCLR :
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear the NMISR.TZFCLR flag
End of enumeration elements list.
CPECLR :
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear the NMISR.CPECLR flag
End of enumeration elements list.
Non-Maskable Interrupt Status Register
address_offset : 0x140 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IWDTST : IWDT Underflow/Refresh Error Status Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested
End of enumeration elements list.
WDTST : WDT Underflow/Refresh Error Status Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested
End of enumeration elements list.
LVD1ST : Voltage Monitor 1 Interrupt Status Flag
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested
End of enumeration elements list.
LVD2ST : Voltage Monitor 2 Interrupt Status Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested
End of enumeration elements list.
OSTST : Oscillation Stop Detection Interrupt Status Flag
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested for main oscillation stop
#1 : 1
Interrupt requested for main oscillation stop
End of enumeration elements list.
NMIST : NMI Status Flag
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested
End of enumeration elements list.
RPEST : SRAM Parity Error Interrupt Status Flag
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested
End of enumeration elements list.
RECCST : SRAM ECC Error Interrupt Status Flag
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested
End of enumeration elements list.
BUSMST : MPU Bus Master Error Interrupt Status Flag
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested
End of enumeration elements list.
TZFST :
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested
End of enumeration elements list.
CPEST :
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested
End of enumeration elements list.
Wake Up Interrupt Enable Register 0
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQWUPEN : IRQn interrupt Software standby returns enable bit
bits : 0 - 14 (15 bit)
access : read-write
Enumeration:
#0 : 0
Software standby returns by IRQn interrupt is disabled
#1 : 1
Software standby returns by IRQn interrupt is enabled
End of enumeration elements list.
IWDTWUPEN : IWDT interrupt Software standby returns enable bit
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Software standby returns by IWDT interrupt is disabled
#1 : 1
Software standby returns by IWDT interrupt is enabled
End of enumeration elements list.
LVD1WUPEN : LVD1 interrupt Software standby returns enable bit
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Software standby returns by LVD1 interrupt is disabled
#1 : 1
Software standby returns by LVD1 interrupt is enabled
End of enumeration elements list.
LVD2WUPEN : LVD2 Interrupt Software Standby Return Enable bit
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Software standby returns by LVD2 interrupt is disabled
#1 : 1
Software standby returns by LVD2 interrupt is enabled
End of enumeration elements list.
RTCALMWUPEN : RTC Alarm interrupt Software Standby Return Enable bit
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Software standby returns by RTC alarm interrupt is disabled
#1 : 1
Software standby returns by RTC alarm interrupt is enabled
End of enumeration elements list.
RTCPRDWUPEN : RTC Period Interrupt Software Standby Return Enable bit
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
Software standby returns by RTC period interrupt is disabled
#1 : 1
Software standby returns by RTC period interrupt is enabled
End of enumeration elements list.
USBFS0WUPEN : USBFS0 Interrupt Software Standby Return Enable bit
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
Software standby returns by USBFS0 interrupt is disabled
#1 : 1
Software standby returns by USBFS0 interrupt is enabled
End of enumeration elements list.
AGT1UDWUPEN : AGT1 Underflow Interrupt Software Standby Return Enable bit
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
Software standby returns by AGT1 underflow interrupt is disabled
#1 : 1
Software standby returns by AGT1 underflow interrupt is enabled
End of enumeration elements list.
AGT1CAWUPEN : AGT1 Compare Match A Interrupt Software Standby Return Enable bit
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Software standby returns by AGT1 compare match A interrupt is disabled
#1 : 1
Software standby returns by AGT1 compare match A interrupt is enabled
End of enumeration elements list.
AGT1CBWUPEN : AGT1 Compare Match B Interrupt Software Standby Return Enable bit
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Software standby returns by AGT1 compare match B interrupt is disabled
#1 : 1
Software standby returns by AGT1 compare match B interrupt is enabled
End of enumeration elements list.
IIC0WUPEN : IIC0 Address Match Interrupt Software Standby Return Enable bit
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Software standby returns by IIC0 address match interrupt is disabled
#1 : 1
Software standby returns by IIC0 address match interrupt is enabled
End of enumeration elements list.
Wake Up interrupt enable register 1
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGT3UDWUPEN : AGT3 Underflow Interrupt Software Standby Return Enable bit
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Software standby returns by AGT3 underflow interrupt is disabled
#1 : 1
Software standby returns by AGT3 underflow interrupt is enabled
End of enumeration elements list.
AGT3CAWUPEN : AGT3 Compare Match A Interrupt Software Standby Return Enable bit
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Software standby returns by AGT3 compare match A interrupt is disabled
#1 : 1
Software standby returns by AGT3 compare match A interrupt is enabled
End of enumeration elements list.
AGT3CBWUPEN : AGT3 Compare Match B Interrupt Software Standby Return Enable bit
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Software standby returns by AGT3 compare match B interrupt is disabled
#1 : 1
Software standby returns by AGT3 compare match B interrupt is enabled
End of enumeration elements list.
IRQ Control Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
SYS Event Link Setting Register
address_offset : 0x200 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAC Event Link Setting Register %s
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x00 : 0x00
Disable interrupts to the associated DMAC module
: Others
Event signal number to be linked. For details, see .
End of enumeration elements list.
IR : DMAC Activation Request Status flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No DMAC activation request occurred
#1 : 1
DMAC activation request occurred.
End of enumeration elements list.
DMAC Event Link Setting Register %s
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x00 : 0x00
Disable interrupts to the associated DMAC module
: Others
Event signal number to be linked. For details, see .
End of enumeration elements list.
IR : DMAC Activation Request Status flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No DMAC activation request occurred
#1 : 1
DMAC activation request occurred.
End of enumeration elements list.
DMAC Event Link Setting Register %s
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x00 : 0x00
Disable interrupts to the associated DMAC module
: Others
Event signal number to be linked. For details, see .
End of enumeration elements list.
IR : DMAC Activation Request Status flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No DMAC activation request occurred
#1 : 1
DMAC activation request occurred.
End of enumeration elements list.
DMAC Event Link Setting Register %s
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x00 : 0x00
Disable interrupts to the associated DMAC module
: Others
Event signal number to be linked. For details, see .
End of enumeration elements list.
IR : DMAC Activation Request Status flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No DMAC activation request occurred
#1 : 1
DMAC activation request occurred.
End of enumeration elements list.
DMAC Event Link Setting Register %s
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x00 : 0x00
Disable interrupts to the associated DMAC module
: Others
Event signal number to be linked. For details, see .
End of enumeration elements list.
IR : DMAC Activation Request Status flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No DMAC activation request occurred
#1 : 1
DMAC activation request occurred.
End of enumeration elements list.
DMAC Event Link Setting Register %s
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x00 : 0x00
Disable interrupts to the associated DMAC module
: Others
Event signal number to be linked. For details, see .
End of enumeration elements list.
IR : DMAC Activation Request Status flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No DMAC activation request occurred
#1 : 1
DMAC activation request occurred.
End of enumeration elements list.
DMAC Event Link Setting Register %s
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x00 : 0x00
Disable interrupts to the associated DMAC module
: Others
Event signal number to be linked. For details, see .
End of enumeration elements list.
IR : DMAC Activation Request Status flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No DMAC activation request occurred
#1 : 1
DMAC activation request occurred.
End of enumeration elements list.
DMAC Event Link Setting Register %s
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : DMAC Event Link Select
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x00 : 0x00
Disable interrupts to the associated DMAC module
: Others
Event signal number to be linked. For details, see .
End of enumeration elements list.
IR : DMAC Activation Request Status flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No DMAC activation request occurred
#1 : 1
DMAC activation request occurred.
End of enumeration elements list.
IRQ Control Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ Control Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICU Event Link Setting Register %s
address_offset : 0x47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ Control Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
IRQ Control Register
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQi Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQi Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
FLTEN : IRQi Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
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