Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
Debug Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CDBGPWRUPREQ : Debug power-up request
bits : 28 - 27 (0 bit)
access : read-only
Enumeration:
#0 : 0
OCD is not requesting debug power up
#1 : 1
OCD is requesting debug power up
End of enumeration elements list.
CDBGPWRUPACK : Debug power-up acknowledge
bits : 29 - 28 (0 bit)
access : read-only
Enumeration:
#0 : 0
Debug power-up request is not acknowledged
#1 : 1
Debug power-up request is acknowledged
End of enumeration elements list.
Debug Stop Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGSTOP_IWDT : Mask bit for IWDT reset/interrupt
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Enable IWDT reset/interrupt
#1 : 1
Mask IWDT reset/interrupt and stop IWDT count when CPU is in OCD break mode
End of enumeration elements list.
DBGSTOP_WDT : Mask bit for WDT reset/interrupt
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Enable WDT reset/interrupt
#1 : 1
Mask WDT reset/interrupt and stop WDT count when CPU is in OCD break mode
End of enumeration elements list.
DBGSTOP_LVD0 : Mask bit for LVD0 reset
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Enable LVD0 reset
#1 : 1
Mask LVD0 reset
End of enumeration elements list.
DBGSTOP_LVD1 : Mask bit for LVD1 reset/interrupt
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Enable LVD1 reset/interrupt
#1 : 1
Mask LVD1 reset/interrupt
End of enumeration elements list.
DBGSTOP_LVD2 : Mask bit for LVD2 reset/interrupt
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Enable LVD2 reset/interrupt
#1 : 1
Mask LVD2 reset/interrupt
End of enumeration elements list.
DBGSTOP_RPER : Mask bit for SRAM parity error reset/interrupt
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Enable SRAM parity error reset/interrupt
#1 : 1
Mask SRAM parity error reset/interrupt
End of enumeration elements list.
DBGSTOP_RECCR : Mask bit for SRAM ECC error reset/interrupt
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
Enable SRAM ECC error reset/interrupt
#1 : 1
Mask SRAM ECC error reset/interrupt
End of enumeration elements list.
DBGSTOP_CPER : Mask bit for Cache SRAM parity error reset/interrupt
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Enable Cache SRAM parity error reset/interrupt
#1 : 1
Mask Cache SRAM parity error reset/interrupt
End of enumeration elements list.
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