Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0xC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x26 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x28 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x32 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x36 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x38 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x3E Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x48 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x61 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x6C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x74 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x88 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x92 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x94 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x98 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xA0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xA2 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xAA Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xC0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xE0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x3C0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x3E0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x3FE Bytes (0x0)
size : 0xF byte (0x0)
mem_usage : registers
protection :
address_offset : 0x40E Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x410 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x413 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x416 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x41A Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x41D Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x480 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x490 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x492 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x4BB Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x4C0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x500 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection :
System Clock Division Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCKD : Peripheral Module Clock D (PCLKD) Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
x 1/1
#001 : 001
x 1/2
#010 : 010
x 1/4
#011 : 011
x 1/8
#100 : 100
x 1/16
#101 : 101
x 1/32
#110 : 110
x 1/64
: Others
Setting prohibited.
End of enumeration elements list.
PCKC : Peripheral Module Clock C (PCLKC) Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
x 1/1
#001 : 001
x 1/2
#010 : 010
x 1/4
#011 : 011
x 1/8
#100 : 100
x 1/16
#101 : 101
x 1/32
#110 : 110
x 1/64
: Others
Setting prohibited.
End of enumeration elements list.
PCKB : Peripheral Module Clock B (PCLKB) Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#000 : 000
x 1/1
#001 : 001
x 1/2
#010 : 010
x 1/4
#011 : 011
x 1/8
#100 : 100
x 1/16
#101 : 101
x 1/32
#110 : 110
x 1/64
: Others
Setting prohibited.
End of enumeration elements list.
PCKA : Peripheral Module Clock A (PCLKA) Select
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#000 : 000
x 1/1
#001 : 001
x 1/2
#010 : 010
x 1/4
#011 : 011
x 1/8
#100 : 100
x 1/16
#101 : 101
x 1/32
#110 : 110
x 1/64
: Others
Setting prohibited.
End of enumeration elements list.
RSV : Reserved. Set these bits to the same value as PCKB[2:0].
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#000 : 000
x 1/1
#001 : 001
x 1/2
#010 : 010
x 1/4
#011 : 011
x 1/8
#100 : 100
x 1/16
#101 : 101
x 1/32
#110 : 110
x 1/64
: Others
Settings prohibited
End of enumeration elements list.
ICK : System Clock (ICLK) Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#000 : 000
x 1/1
#001 : 001
x 1/2
#010 : 010
x 1/4
#011 : 011
x 1/8
#100 : 100
x 1/16
#101 : 101
x 1/32
#110 : 110
x 1/64
: Others
Setting prohibited.
End of enumeration elements list.
FCK : FlashIF Clock (FCLK) Select
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#000 : 000
x 1/1
#001 : 001
x 1/2
#010 : 010
x 1/4
#011 : 011
x 1/8
#100 : 100
x 1/16
#101 : 101
x 1/32
#110 : 110
x 1/64
: Others
Setting prohibited.
End of enumeration elements list.
System Clock Source Control Register
address_offset : 0x26 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKSEL : Clock Source Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
HOCO
#001 : 001
MOCO
#010 : 010
LOCO
#011 : 011
Main clock oscillator (MOSC)
#100 : 100
Sub-clock oscillator (SOSC)
End of enumeration elements list.
PLL Clock Control Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLIDIV : PLL Input Frequency Division Ratio Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
/1
#01 : 01
/2
#10 : 10
/3
: Others
Setting prohibited.
End of enumeration elements list.
PLSRCSEL : PLL Clock Source Select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Main clock oscillator
#1 : 1
HOCO
End of enumeration elements list.
PLLMUL : PLL Frequency Multiplication Factor Select
bits : 8 - 12 (5 bit)
access : read-write
PLL Control Register
address_offset : 0x2A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLSTP : PLL Stop Control
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
PLL is operating
#1 : 1
PLL is stopped.
End of enumeration elements list.
Main Clock Oscillator Control Register
address_offset : 0x32 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOSTP : Main Clock Oscillator Stop
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Operate the main clock oscillator
#1 : 1
Stop the main clock oscillator
End of enumeration elements list.
High-Speed On-Chip Oscillator Control Register
address_offset : 0x36 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCSTP : HOCO Stop
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Operate the HOCO clock
#1 : 1
Stop the HOCO clock
End of enumeration elements list.
Middle-Speed On-Chip Oscillator Control Register
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCSTP : MOCO Stop
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
MOCO clock is operating
#1 : 1
MOCO clock is stopped
End of enumeration elements list.
FLL Control Register1
address_offset : 0x39 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLLEN : FLL Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FLL function is disabled
#1 : 1
FLL function is enabled.
End of enumeration elements list.
FLL Control Register2
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLLCNTL : FLL Multiplication Control
bits : 0 - 9 (10 bit)
access : read-write
Oscillation Stabilization Flag Register
address_offset : 0x3C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HOCOSF : HOCO Clock Oscillation Stabilization Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
The HOCO clock is stopped or is not yet stable
#1 : 1
The HOCO clock is stable, so is available for use as the system clock
End of enumeration elements list.
MOSCSF : Main Clock Oscillation Stabilization Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
The main clock oscillator is stopped (MOSTP = 1) or is not yet stable
#1 : 1
The main clock oscillator is stable, so is available for use as the system clock
End of enumeration elements list.
PLLSF : PLL Clock Oscillation Stabilization Flag
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
The PLL clock is stopped, or oscillation of the PLL clock is not stable yet
#1 : 1
The PLL clock is stable, so is available for use as the system clock
End of enumeration elements list.
PLL2SF : PLL2 Clock Oscillation Stabilization Flag
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
The PLL2 clock is stopped, or oscillation of the PLL2 clock is not stable yet
#1 : 1
The PLL2 clock is stable
End of enumeration elements list.
Clock Generation Function Security Attribute Register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NONSEC00 : Non Secure Attribute bit 00
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC02 : Non Secure Attribute bit 02
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC03 : Non Secure Attribute bit 03
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC04 : Non Secure Attribute bit 04
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC05 : Non Secure Attribute bit 05
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC06 : Non Secure Attribute bit 06
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC07 : Non Secure Attribute bit 07
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC08 : Non Secure Attribute bit 08
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC09 : Non Secure Attribute bit 09
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC11 : Non Secure Attribute bit 11
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC16 : Non Secure Attribute bit 16
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
Reset Security Attribution Register
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NONSEC0 : Non Secure Attribute bit 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC1 : Non Secure Attribute bit 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC2 : Non Secure Attribute bit 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
Low Power Mode Security Attribution Register
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NONSEC0 : Non Secure Attribute bit 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC2 : Non Secure Attribute bit 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC4 : Non Secure Attribute bit 4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC8 : Non Secure Attribute bit 8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC9 : Non Secure Attribute bit 9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
Low Voltage Detection Security Attribution Register
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NONSEC0 : Non Secure Attribute bit 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC1 : Non Secure Attribute bit 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
Battery Backup Function Security Attribute Register
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NONSEC0 : Non Secure Attribute bit 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC1 : Non Secure Attribute bit 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC2 : Non Secure Attribute bit 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC16 : Non Secure Attribute bit 16
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC17 : Non Secure Attribute bit 17
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC18 : Non Secure Attribute bit 18
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC19 : Non Secure Attribute bit 19
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC20 : Non Secure Attribute bit 20
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC21 : Non Secure Attribute bit 21
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC22 : Non Secure Attribute bit 22
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
NONSEC23 : Non Secure Attribute bit 23
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
Clock Out Control Register
address_offset : 0x3E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKOSEL : Clock Out Source Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
HOCO
#001 : 001
MOCO
#010 : 010
LOCO
#011 : 011
MOSC
#100 : 100
SOSC
#101 : 101
Setting prohibited
: Others
Setting prohibited
End of enumeration elements list.
CKODIV : Clock Output Frequency Division Ratio
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
x 1/1
#001 : 001
x 1/2
#010 : 010
x 1/4
#011 : 011
x 1/8
#100 : 100
x 1/16
#101 : 101
x 1/32
#110 : 110
x 1/64
#111 : 111
x 1/128
End of enumeration elements list.
CKOEN : Clock Out Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable clock out
#1 : 1
Enable clock out
End of enumeration elements list.
Deep Standby Interrupt Factor Security Attribution Register
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPFSA0 : Deep Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA1 : Deep Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA2 : Deep Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA3 : Deep Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA4 : Deep Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA5 : Deep Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA6 : Deep Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA7 : Deep Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA8 : Deep Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA9 : Deep Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA10 : Deep Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA11 : Deep Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA12 : Deep Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA13 : Deep Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA14 : Deep Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA15 : Deep Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA16 : Deep Standby Interrupt Factor Security Attribute bit 16
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA17 : Deep Standby Interrupt Factor Security Attribute bit 17
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA18 : Deep Standby Interrupt Factor Security Attribute bit 18
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA19 : Deep Standby Interrupt Factor Security Attribute bit 19
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA20 : Deep Standby Interrupt Factor Security Attribute bit 20
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA24 : Deep Standby Interrupt Factor Security Attribute bit 24
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA26 : Deep Standby Interrupt Factor Security Attribute bit 26
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
DPFSA27 : Deep Standby Interrupt Factor Security Attribute bit 27
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
Secure
#1 : 1
Non Secure
End of enumeration elements list.
Trace Clock Control Register
address_offset : 0x3F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCK : Trace Clock operating frequency select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
/1
0x1 : 0x1
/2 (value after reset)
0x2 : 0x2
/4
End of enumeration elements list.
TRCKEN : Trace Clock operating Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stop
#1 : 1
Operation enable
End of enumeration elements list.
Protect Register
address_offset : 0x3FE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRC0 : Enable writing to the registers related to the clock generation circuit
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable writes
#1 : 1
Enable writes
End of enumeration elements list.
PRC1 : Enable writing to the registers related to the low power modes, and the battery backup function
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable writes
#1 : 1
Enable writes
End of enumeration elements list.
PRC3 : Enable writing to the registers related to the LVD
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable writes
#1 : 1
Enable writes
End of enumeration elements list.
PRC4 :
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable writes
#1 : 1
Enable writes
End of enumeration elements list.
PRKEY : PRC Key Code
bits : 8 - 14 (7 bit)
access : write-only
Oscillation Stop Detection Control Register
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSTDIE : Oscillation Stop Detection Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable oscillation stop detection interrupt (do not notify the POEG)
#1 : 1
Enable oscillation stop detection interrupt (notify the POEG)
End of enumeration elements list.
OSTDE : Oscillation Stop Detection Function Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable oscillation stop detection function
#1 : 1
Enable oscillation stop detection function
End of enumeration elements list.
Deep Standby Control Register
address_offset : 0x400 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEEPCUT : Power-Supply Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Power to the standby RAM, Low-speed on-chip oscillator, AGTn (n = 0 to 3), and USBFS resume detecting unit is supplied in Deep Software Standby mode.
#01 : 01
Power to the standby RAM, Low-speed on-chip oscillator, AGT, and USBFS resume detecting unit is not supplied in Deep Software Standby mode.
#10 : 10
Setting prohibited
#11 : 11
Power to the standby RAM, Low-speed on-chip oscillator, AGT, and USBFS resume detecting unit is not supplied in Deep Software Standby mode. In addition, LVD is disabled and the low power function in a power-on reset circuit is enabled.
End of enumeration elements list.
IOKEEP : I/O Port Rentention
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
When the Deep Software Standby mode is canceled, the I/O ports are in the reset state.
#1 : 1
When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode.
End of enumeration elements list.
DPSBY : Deep Software Standby
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Sleep mode (SBYCR.SSBY=0) / Software Standby mode (SBYCR.SSBY=1)
#1 : 1
Sleep mode (SBYCR.SSBY=0) / Deep Software Standby mode (SBYCR.SSBY=1)
End of enumeration elements list.
Deep Standby Wait Control Register
address_offset : 0x401 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WTSTS : Deep Software Wait Standby Time Setting Bit
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0x0e : 0x0E
Wait cycle for fast recovery
0x19 : 0x19
Wait cycle for slow recovery
: Others
Setting prohibited
End of enumeration elements list.
Deep Standby Interrupt Enable Register 0
address_offset : 0x402 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIRQ0E : IRQ0-DS Pin Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DIRQ1E : IRQ1-DS Pin Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DIRQ2E : IRQ2-DS Pin Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DIRQ3E : IRQ3-DS Pin Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DIRQ4E : IRQ4-DS Pin Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DIRQ5E : IRQ5-DS Pin Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DIRQ6E : IRQ6-DS Pin Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DIRQ7E : IRQ7-DS Pin Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
Deep Standby Interrupt Enable Register 1
address_offset : 0x403 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIRQ8E : IRQ8-DS Pin Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DIRQ9E : IRQ9-DS Pin Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DIRQ10E : IRQ10-DS Pin Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DIRQ11E : IRQ11-DS Pin Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DIRQ12E : IRQ12-DS Pin Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DIRQ13E : IRQ13-DS Pin Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DIRQ14E : IRQ14-DS Pin Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DIRQ15E : IRQ15-DS Pin Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
Deep Standby Interrupt Enable Register 2
address_offset : 0x404 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLVD1IE : LVD1 Deep Standby Cancel Signal Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DLVD2IE : LVD2 Deep Standby Cancel Signal Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DRTCIIE : RTC Interval interrupt Deep Standby Cancel Signal Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DRTCAIE : RTC Alarm interrupt Deep Standby Cancel Signal Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
DNMIE : NMI Pin Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling Deep Software Standby mode is disabled
#1 : 1
Cancelling Deep Software Standby mode is enabled
End of enumeration elements list.
Deep Standby Interrupt Enable Register 3
address_offset : 0x405 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUSBFS0IE : USBFS0 Suspend/Resume Deep Standby Cancel Signal Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling deep standby mode is disabled
#1 : 1
Cancelling deep standby mode is enabled
End of enumeration elements list.
DAGT1IE : AGT1 Underflow Deep Standby Cancel Signal Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling deep standby mode is disabled
#1 : 1
Cancelling deep standby mode is enabled
End of enumeration elements list.
DAGT3IE : AGT3 Underflow Deep Standby Cancel Signal Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cancelling deep standby mode is disabled
#1 : 1
Cancelling deep standby mode is enabled
End of enumeration elements list.
Deep Standby Interrupt Flag Register 0
address_offset : 0x406 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIRQ0F : IRQ0-DS Pin Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DIRQ1F : IRQ1-DS Pin Deep Standby Cancel Flag
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DIRQ2F : IRQ2-DS Pin Deep Standby Cancel Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DIRQ3F : IRQ3-DS Pin Deep Standby Cancel Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DIRQ4F : IRQ4-DS Pin Deep Standby Cancel Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DIRQ5F : IRQ5-DS Pin Deep Standby Cancel Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DIRQ6F : IRQ6-DS Pin Deep Standby Cancel Flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DIRQ7F : IRQ7-DS Pin Deep Standby Cancel Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
Deep Standby Interrupt Flag Register 1
address_offset : 0x407 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIRQ8F : IRQ8-DS Pin Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DIRQ9F : IRQ9-DS Pin Deep Standby Cancel Flag
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DIRQ10F : IRQ10-DS Pin Deep Standby Cancel Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DIRQ11F : IRQ11-DS Pin Deep Standby Cancel Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DIRQ12F : IRQ12-DS Pin Deep Standby Cancel Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DIRQ13F : IRQ13-DS Pin Deep Standby Cancel Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DIRQ14F : IRQ14-DS Pin Deep Standby Cancel Flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DIRQ15F : IRQ15-DS Pin Deep Standby Cancel Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
Deep Standby Interrupt Flag Register 2
address_offset : 0x408 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLVD1IF : LVD1 Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DLVD2IF : LVD2 Deep Standby Cancel Flag
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DRTCIIF : RTC Interval Interrupt Deep Standby Cancel Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DRTCAIF : RTC Alarm Interrupt Deep Standby Cancel Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
DNMIF : NMI Pin Deep Standby Cancel Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated
#1 : 1
The cancel request is generated
End of enumeration elements list.
Deep Standby Interrupt Flag Register 3
address_offset : 0x409 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUSBFS0IF : USBFS0 Suspend/Resume Deep Standby Cancel Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated.
#1 : 1
The cancel request is generated.
End of enumeration elements list.
DAGT1IF : AGT1 Underflow Deep Standby Cancel Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated.
#1 : 1
The cancel request is generated.
End of enumeration elements list.
DAGT3IF : AGT3 Underflow Deep Standby Cancel Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
The cancel request is not generated.
#1 : 1
The cancel request is generated.
End of enumeration elements list.
Deep Standby Interrupt Edge Register 0
address_offset : 0x40A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIRQ0EG : IRQ0-DS Pin Edge Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge
#1 : 1
A cancel request is generated at a rising edge
End of enumeration elements list.
DIRQ1EG : IRQ1-DS Pin Edge Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge
#1 : 1
A cancel request is generated at a rising edge
End of enumeration elements list.
DIRQ2EG : IRQ2-DS Pin Edge Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge
#1 : 1
A cancel request is generated at a rising edge
End of enumeration elements list.
DIRQ3EG : IRQ3-DS Pin Edge Select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge
#1 : 1
A cancel request is generated at a rising edge
End of enumeration elements list.
DIRQ4EG : IRQ4-DS Pin Edge Select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge
#1 : 1
A cancel request is generated at a rising edge
End of enumeration elements list.
DIRQ5EG : IRQ5-DS Pin Edge Select
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge
#1 : 1
A cancel request is generated at a rising edge
End of enumeration elements list.
DIRQ6EG : IRQ6-DS Pin Edge Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge
#1 : 1
A cancel request is generated at a rising edge
End of enumeration elements list.
DIRQ7EG : IRQ7-DS Pin Edge Select
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge
#1 : 1
A cancel request is generated at a rising edge
End of enumeration elements list.
Deep Standby Interrupt Edge Register 1
address_offset : 0x40B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIRQ8EG : IRQ8-DS Pin Edge Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge.
#1 : 1
A cancel request is generated at a rising edge.
End of enumeration elements list.
DIRQ9EG : IRQ9-DS Pin Edge Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge.
#1 : 1
A cancel request is generated at a rising edge.
End of enumeration elements list.
DIRQ10EG : IRQ10-DS Pin Edge Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge.
#1 : 1
A cancel request is generated at a rising edge
End of enumeration elements list.
DIRQ11EG : IRQ11-DS Pin Edge Select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge.
#1 : 1
A cancel request is generated at a rising edge.
End of enumeration elements list.
DIRQ12EG : IRQ12-DS Pin Edge Select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge.
#1 : 1
A cancel request is generated at a rising edge.
End of enumeration elements list.
DIRQ13EG : IRQ13-DS Pin Edge Select
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge.
#1 : 1
A cancel request is generated at a rising edge.
End of enumeration elements list.
DIRQ14EG : IRQ14-DS Pin Edge Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge.
#1 : 1
A cancel request is generated at a rising edge.
End of enumeration elements list.
DIRQ15EG : IRQ15-DS Pin Edge Select
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge.
#1 : 1
A cancel request is generated at a rising edge.
End of enumeration elements list.
Deep Standby Interrupt Edge Register 2
address_offset : 0x40C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLVD1EG : LVD1 Edge Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated when VCC < Vdet1 (fall) is detected
#1 : 1
A cancel request is generated when VCC ≥ Vdet1 (rise) is detected
End of enumeration elements list.
DLVD2EG : LVD2 Edge Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated when VCC < Vdet2 (fall) is detected
#1 : 1
A cancel request is generated when VCC ≥ Vdet2 (rise) is detected
End of enumeration elements list.
DNMIEG : NMI Pin Edge Select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
A cancel request is generated at a falling edge
#1 : 1
A cancel request is generated at a rising edge
End of enumeration elements list.
System Control OCD Control Register
address_offset : 0x40E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOCDF : Deep Software Standby OCD flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
DBIRQ is not generated
#1 : 1
DBIRQ is generated
End of enumeration elements list.
DBGEN : Debugger Enable bit
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
On-chip debugger is disabled
#1 : 1
On-chip debugger is enabled
End of enumeration elements list.
Oscillation Stop Detection Status Register
address_offset : 0x41 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSTDF : Oscillation Stop Detection Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Main clock oscillation stop not detected
#1 : 1
Main clock oscillation stop detected
End of enumeration elements list.
Reset Status Register 0
address_offset : 0x410 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORF : Power-On Reset Detect Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Power-on reset not detected
#1 : 1
Power-on reset detected
End of enumeration elements list.
LVD0RF : Voltage Monitor 0 Reset Detect Flag
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Voltage monitor 0 reset not detected
#1 : 1
Voltage monitor 0 reset detected
End of enumeration elements list.
LVD1RF : Voltage Monitor 1 Reset Detect Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Voltage monitor 1 reset not detected
#1 : 1
Voltage monitor 1 reset detected
End of enumeration elements list.
LVD2RF : Voltage Monitor 2 Reset Detect Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Voltage monitor 2 reset not detected
#1 : 1
Voltage monitor 2 reset detected
End of enumeration elements list.
DPSRSTF : Deep Software Standby Reset Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Deep software standby mode cancellation not requested by an interrupt.
#1 : 1
Deep software standby mode cancellation requested by an interrupt.
End of enumeration elements list.
Reset Status Register 2
address_offset : 0x411 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CWSF : Cold/Warm Start Determination Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cold start
#1 : 1
Warm start
End of enumeration elements list.
Main Clock Oscillator Mode Oscillation Control Register
address_offset : 0x413 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODRV : Main Clock Oscillator Drive Capability 0 Switching
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
20 MHz to 24 MHz
#01 : 01
16 MHz to 20 MHz
#10 : 10
8 MHz to 16 MHz
#11 : 11
8 MHz
End of enumeration elements list.
MOSEL : Main Clock Oscillator Switching
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Resonator
#1 : 1
External clock input
End of enumeration elements list.
Flash P/E Protect Register
address_offset : 0x416 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLWE : Flash Programming and Erasure
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing.
#01 : 01
Permits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing.
#10 : 10
Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing.
#11 : 11
Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing.
End of enumeration elements list.
Voltage Monitoring 1 Comparator Control Register
address_offset : 0x417 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVD1LVL : Voltage Detection 1 Level Select (Standard voltage during drop in voltage)
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x11 : 0x11
2.99 V (Vdet1_11)
0x12 : 0x12
2.92 V (Vdet1_12)
0x13 : 0x13
2.85 V (Vdet1_13)
: Others
Setting prohibited
End of enumeration elements list.
LVD1E : Voltage Detection 1 Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Voltage detection 1 circuit disabled
#1 : 1
Voltage detection 1 circuit enabled
End of enumeration elements list.
Voltage Monitoring 2 Comparator Control Register
address_offset : 0x418 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVD2LVL : Voltage Detection 2 Level Select (Standard voltage during drop in voltage)
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#101 : 101
2.99 V (Vdet2_5)
#110 : 110
2.92 V (Vdet2_6)
#111 : 111
2.85 V (Vdet2_7)
: Others
Setting prohibited
End of enumeration elements list.
LVD2E : Voltage Detection 2 Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Voltage detection 2 circuit disabled
#1 : 1
Voltage detection 2 circuit enabled
End of enumeration elements list.
Voltage Monitor 1 Circuit Control Register 0
address_offset : 0x41A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RIE : Voltage Monitor 1 Interrupt/Reset Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
DFDIS : Voltage monitor 1 Digital Filter Disabled Mode Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Enable the digital filter
#1 : 1
Disable the digital filter
End of enumeration elements list.
CMPE : Voltage Monitor 1 Circuit Comparison Result Output Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable voltage monitor 1 circuit comparison result output
#1 : 1
Enable voltage monitor 1 circuit comparison result output
End of enumeration elements list.
FSAMP : Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
1/2 LOCO frequency
#01 : 01
1/4 LOCO frequency
#10 : 10
1/8 LOCO frequency
#11 : 11
1/16 LOCO frequency
End of enumeration elements list.
RI : Voltage Monitor 1 Circuit Mode Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Generate voltage monitor 1 interrupt on Vdet1 crossing
#1 : 1
Enable voltage monitor 1 reset when the voltage falls to and below Vdet1
End of enumeration elements list.
RN : Voltage Monitor 1 Reset Negate Select
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Negate after a stabilization time (tLVD1) when VCC > Vdet1 is detected
#1 : 1
Negate after a stabilization time (tLVD1) on assertion of the LVD1 reset
End of enumeration elements list.
Voltage Monitor 2 Circuit Control Register 0
address_offset : 0x41B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RIE : Voltage Monitor 2 Interrupt/Reset Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
DFDIS : Voltage monitor 2 Digital Filter Disabled Mode Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Enable the digital filter
#1 : 1
Disable the digital filter
End of enumeration elements list.
CMPE : Voltage Monitor 2 Circuit Comparison Result Output Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable voltage monitor 2 circuit comparison result output
#1 : 1
Enable voltage monitor 2 circuit comparison result output
End of enumeration elements list.
FSAMP : Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
1/2 LOCO frequency
#01 : 01
1/4 LOCO frequency
#10 : 10
1/8 LOCO frequency
#11 : 11
1/16 LOCO frequency
End of enumeration elements list.
RI : Voltage Monitor 2 Circuit Mode Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Generate voltage monitor 2 interrupt on Vdet2 crossing
#1 : 1
Enable voltage monitor 2 reset when the voltage falls to and below Vdet2
End of enumeration elements list.
RN : Voltage Monitor 2 Reset Negate Select
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Negate after a stabilization time (tLVD2) when VCC > Vdet2 is detected
#1 : 1
Negate after a stabilization time (tLVD2) on assertion of the LVD2 reset
End of enumeration elements list.
Battery Backup Voltage Monitor Function Select Register
address_offset : 0x41D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATTMNSEL : VBATT Low Voltage Detect Function Select Bit
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables VBATT low voltage detect function
#1 : 1
Enables VBATT low voltage detect function
End of enumeration elements list.
Battery Backup Voltage Monitor Register
address_offset : 0x41E Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VBATTMON : VBATT Voltage Monitor Bit
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
VBATT ≥ Vbattldet
#1 : 1
VBATT < Vbattldet
End of enumeration elements list.
PLL2 Clock Control Register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PL2IDIV : PLL2 Input Frequency Division Ratio Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
∕ 1 (value after reset)
#01 : 01
∕ 2
#10 : 10
∕ 3
: Others
Setting prohibited.
End of enumeration elements list.
PL2SRCSEL : PLL2 Clock Source Select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Main clock oscillator
#1 : 1
HOCO
End of enumeration elements list.
PLL2MUL : PLL2 Frequency Multiplication Factor Select
bits : 8 - 12 (5 bit)
access : read-write
Sub-Clock Oscillator Control Register
address_offset : 0x480 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOSTP : Sub Clock Oscillator Stop
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Operate the sub-clock oscillator
#1 : 1
Stop the sub-clock oscillator
End of enumeration elements list.
Sub-Clock Oscillator Mode Control Register
address_offset : 0x481 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SODRV : Sub-Clock Oscillator Drive Capability Switching
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Standard
#1 : 1
Low
End of enumeration elements list.
Low-Speed On-Chip Oscillator Control Register
address_offset : 0x490 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCSTP : LOCO Stop
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Operate the LOCO clock
#1 : 1
Stop the LOCO clock
End of enumeration elements list.
LOCO User Trimming Control Register
address_offset : 0x492 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCOUTRM : LOCO User Trimming
bits : 0 - 6 (7 bit)
access : read-write
PLL2 Control Register
address_offset : 0x4A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL2STP : PLL2 Stop Control
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
PLL2 is operating
#1 : 1
PLL2 is stopped.
End of enumeration elements list.
VBATT Input Control Register
address_offset : 0x4BB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCH0INEN : VBATT CH0 Input Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTCIC0 input disable
#1 : 1
RTCIC0 input enable
End of enumeration elements list.
VCH1INEN : VBATT CH1 Input Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTCIC1 input disable
#1 : 1
RTCIC1 input enable
End of enumeration elements list.
VCH2INEN : VBATT CH2 Input Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
RTCIC2 input disable
#1 : 1
RTCIC2 input enable
End of enumeration elements list.
VBATT Backup Enable Register
address_offset : 0x4C0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBAE : VBATT backup register access enable bit
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable to access VBTBKR
#1 : 1
Enable to access VBTBKR
End of enumeration elements list.
VBATT Backup Register (n = 0 to 127)
address_offset : 0x500 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x501 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x502 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x503 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x504 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x505 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x506 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x507 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x508 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x509 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x50A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x50B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x50C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x50D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x50E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x50F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x510 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x511 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x512 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x513 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x514 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x515 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x516 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x517 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x518 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x519 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x51A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x51B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x51C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x51D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x51E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x51F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x520 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x521 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x522 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x523 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x524 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x525 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x526 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x527 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x528 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x529 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x52A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x52B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x52C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x52D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x52E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x52F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x530 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x531 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x532 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x533 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x534 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x535 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x536 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x537 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x538 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x539 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x53A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x53B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x53C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x53D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x53E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x53F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x540 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x541 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x542 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x543 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x544 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x545 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x546 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x547 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x548 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x549 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x54A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x54B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x54C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x54D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x54E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x54F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x550 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x551 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x552 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x553 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x554 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x555 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x556 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x557 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x558 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x559 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x55A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x55B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x55C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x55D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x55E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x55F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x560 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x561 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x562 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x563 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x564 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x565 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x566 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x567 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x568 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x569 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x56A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x56B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x56C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x56D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x56E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x56F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x570 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x571 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x572 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x573 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x574 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x575 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x576 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x577 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x578 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x579 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x57A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x57B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x57C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x57D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x57E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATT Backup Register (n = 0 to 127)
address_offset : 0x57F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOCO User Trimming Control Register
address_offset : 0x61 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOCOUTRM : MOCO User Trimming
bits : 0 - 6 (7 bit)
access : read-write
HOCO User Trimming Control Register
address_offset : 0x62 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOCOUTRM : HOCO User Trimming
bits : 0 - 6 (7 bit)
access : read-write
USB Clock Division Control Register
address_offset : 0x6C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBCKDIV : USB Clock (USBCLK) Division Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#010 : 010
∕ 4
#101 : 101
∕ 3
#110 : 110
∕ 5
: Others
Setting prohibited.
End of enumeration elements list.
USB Clock Control Register
address_offset : 0x74 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBCKSEL : USB Clock (USBCLK) Source Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#101 : 101
PLL
#110 : 110
PLL2
: Others
Setting prohibited.
End of enumeration elements list.
USBCKSREQ : USB Clock (USBCLK) Switching Request
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No request
#1 : 1
Request switching.
End of enumeration elements list.
USBCKSRDY : USB Clock (USBCLK) Switching Ready state flag
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
Impossible to Switch
#1 : 1
Possible to Switch
End of enumeration elements list.
Snooze Request Control Register 1
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SNZREQEN0 : Enable AGT3 underflow snooze request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN1 : Enable AGT3 compare match A snooze request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN2 : Enable AGT3 compare match B snooze request
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
Snooze Control Register
address_offset : 0x92 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDREQEN : RXD0 Snooze Request Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Ignore RXD0 falling edge in Software Standby mode
#1 : 1
Detect RXD0 falling edge in Software Standby mode
End of enumeration elements list.
SNZDTCEN : DTC Enable in Snooze mode
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable DTC operation
#1 : 1
Enable DTC operation
End of enumeration elements list.
SNZE : Snooze mode Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable Snooze mode
#1 : 1
Enable Snooze mode
End of enumeration elements list.
Snooze End Control Register 0
address_offset : 0x94 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGTUNFED : AGT1 Underflow Snooze End Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze end request
#1 : 1
Enable the snooze end request
End of enumeration elements list.
DTCZRED : Last DTC Transmission Completion Snooze End Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze end request
#1 : 1
Enable the snooze end request
End of enumeration elements list.
DTCNZRED : Not Last DTC Transmission Completion Snooze End Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze end request
#1 : 1
Enable the snooze end request
End of enumeration elements list.
AD0MATED : ADC120 Compare Match Snooze End Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze end request
#1 : 1
Enable the snooze end request
End of enumeration elements list.
AD0UMTED : ADC120 Compare Mismatch Snooze End Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze end request
#1 : 1
Enable the snooze end request
End of enumeration elements list.
AD1MATED : ADC121 Compare Match Snooze End Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze end request
#1 : 1
Enable the snooze end request
End of enumeration elements list.
AD1UMTED : ADC121 Compare Mismatch Snooze End Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze end request
#1 : 1
Enable the snooze end request
End of enumeration elements list.
SCI0UMTED : SCI0 Address Mismatch Snooze End Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze end request
#1 : 1
Enable the snooze end request
End of enumeration elements list.
Snooze End Control Register 1
address_offset : 0x95 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGT3UNFED : AGT3 underflow Snooze End Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Snooze End request
#1 : 1
Enable the Snooze End request
End of enumeration elements list.
Snooze Request Control Register 0
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SNZREQEN0 : Enable IRQ0 pin snooze request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN1 : Enable IRQ1 pin snooze request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN2 : Enable IRQ2 pin snooze request
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN3 : Enable IRQ3 pin snooze request
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN4 : Enable IRQ4 pin snooze request
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN5 : Enable IRQ5 pin snooze request
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN6 : Enable IRQ6 pin snooze request
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN7 : Enable IRQ7 pin snooze request
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN8 : Enable IRQ8 pin snooze request
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN9 : Enable IRQ9 pin snooze request
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN10 : Enable IRQ10 pin snooze request
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN11 : Enable IRQ11 pin snooze request
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN12 : Enable IRQ12 pin snooze request
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN13 : Enable IRQ13 pin snooze request
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN14 : Enable IRQ14 pin snooze request
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN15 : Enable IRQ15 pin snooze request
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN24 : Enable RTC alarm snooze request
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN25 : Enable RTC period snooze request
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN28 : Enable AGT1 underflow snooze request
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN29 : Enable AGT1 compare match A snooze request
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
SNZREQEN30 : Enable AGT1 compare match B snooze request
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable the snooze request
#1 : 1
Enable the snooze request
End of enumeration elements list.
Operating Power Control Register
address_offset : 0xA0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPCM : Operating Power Control Mode Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
High-speed mode
#01 : 01
Setting prohibited
#10 : 10
Setting prohibited
#11 : 11
Low-speed mode
End of enumeration elements list.
OPCMTSF : Operating Power Control Mode Transition Status Flag
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
Transition completed
#1 : 1
During transition
End of enumeration elements list.
Main Clock Oscillator Wait Control Register
address_offset : 0xA2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTS : Main Clock Oscillator Wait Time Setting
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
Wait time = 3 cycles (11.4 us)
0x1 : 0x1
Wait time = 35 cycles (133.5 us)
0x2 : 0x2
Wait time = 67 cycles (255.6 us)
0x3 : 0x3
Wait time = 131 cycles (499.7 us)
0x4 : 0x4
Wait time = 259 cycles (988.0 us)
0x5 : 0x5
Wait time = 547 cycles (2086.6 us)
0x6 : 0x6
Wait time = 1059 cycles (4039.8 us)
0x7 : 0x7
Wait time = 2147 cycles (8190.2 us)
0x8 : 0x8
Wait time = 4291 cycles (16368.9 us)
0x9 : 0x9
Wait time = 8163 cycles (31139.4 us)
: Others
Setting prohibited
End of enumeration elements list.
Sub Operating Power Control Register
address_offset : 0xAA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOPCM : Sub Operating Power Control Mode Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Other than Subosc-speed mode
#1 : 1
Subosc-speed mode
End of enumeration elements list.
SOPCMTSF : Operating Power Control Mode Transition Status Flag
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
Transition completed
#1 : 1
During transition
End of enumeration elements list.
Standby Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSBY : Software Standby Mode Select
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Sleep mode
#1 : 1
Software Standby mode.
End of enumeration elements list.
Reset Status Register 1
address_offset : 0xC0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IWDTRF : Independent Watchdog Timer Reset Detect Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Independent watchdog timer reset not detected
#1 : 1
Independent watchdog timer reset detected
End of enumeration elements list.
WDTRF : Watchdog Timer Reset Detect Flag
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog timer reset not detected
#1 : 1
Watchdog timer reset detected
End of enumeration elements list.
SWRF : Software Reset Detect Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Software reset not detected
#1 : 1
Software reset detected
End of enumeration elements list.
RPERF : SRAM Parity Error Reset Detect Flag
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
SRAM parity error reset not detected
#1 : 1
SRAM parity error reset detected
End of enumeration elements list.
REERF : SRAM ECC Error Reset Detect Flag
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
SRAM ECC error reset not detected
#1 : 1
SRAM ECC error reset detected
End of enumeration elements list.
BUSMRF : Bus Master MPU Error Reset Detect Flag
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Bus master MPU error reset not detected
#1 : 1
Bus master MPU error reset detected
End of enumeration elements list.
TZERF : TrustZone Error Reset Detect Flag
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
TrustZone error reset not detected.
#1 : 1
TrustZone error reset detected.
End of enumeration elements list.
CPERF : Cache Parity Error Reset Detect Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Cache Parity error reset not detected.
#1 : 1
Cache Parity error reset detected.
End of enumeration elements list.
Voltage Monitor 1 Circuit Control Register
address_offset : 0xE0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDTSEL : Voltage Monitor 1 Interrupt Generation Condition Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
When VCC >= Vdet1 (rise) is detected
#01 : 01
When VCC < Vdet1 (fall) is detected
#10 : 10
When fall and rise are detected
#11 : 11
Settings prohibited
End of enumeration elements list.
IRQSEL : Voltage Monitor 1 Interrupt Type Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Non-maskable interrupt
#1 : 1
Maskable interrupt
End of enumeration elements list.
Voltage Monitor 1 Circuit Status Register
address_offset : 0xE1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DET : Voltage Monitor 1 Voltage Variation Detection Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not detected
#1 : 1
Vdet1 crossing is detected
End of enumeration elements list.
MON : Voltage Monitor 1 Signal Monitor Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
VCC < Vdet1
#1 : 1
VCC >= Vdet1 or MON is disabled
End of enumeration elements list.
Voltage Monitor 2 Circuit Control Register 1
address_offset : 0xE2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDTSEL : Voltage Monitor 2 Interrupt Generation Condition Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
When VCC>= Vdet2 (rise) is detected
#01 : 01
When VCC < Vdet2 (fall) is detected
#10 : 10
When fall and rise are detected
#11 : 11
Settings prohibited
End of enumeration elements list.
IRQSEL : Voltage Monitor 2 Interrupt Type Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Non-maskable interrupt
#1 : 1
Maskable interrupt
End of enumeration elements list.
Voltage Monitor 2 Circuit Status Register
address_offset : 0xE3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DET : Voltage Monitor 2 Voltage Variation Detection Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not detected
#1 : 1
Vdet2 crossing is detected
End of enumeration elements list.
MON : Voltage Monitor 2 Signal Monitor Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
VCC < Vdet2
#1 : 1
VCC>= Vdet2 or MON is disabled
End of enumeration elements list.
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