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CTSU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x9 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xB Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x10 Bytes (0x0)
size : 0xE byte (0x0)
mem_usage : registers
protection :

address_offset : 0x20 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection :

Registers

CTSUCR0

CTSUCR1

CTSUDCLKC

CTSUST

CTSUSSC

CTSUSO0

CTSUSO1

CTSUSC

CTSURC

CTSUERRS

CTSUSDPRS

CTSUTRMR

CTSUSST

CTSUMCH0

CTSUMCH1

CTSUCHAC0

CTSUCHAC1

CTSUCHAC2

CTSUCHTRC0

CTSUCHTRC1

CTSUCHTRC2


CTSUCR0

CTSU Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCR0 CTSUCR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CTSUCR1

CTSU Control Register 1
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCR1 CTSUCR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CTSUDCLKC

CTSU High-Pass Noise Reduction Control Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUDCLKC CTSUDCLKC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CTSUST

CTSU Status Register
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUST CTSUST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CTSUSSC

CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUSSC CTSUSSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTSUSSDIV

CTSUSSDIV : CTSU Spectrum Diffusion Frequency Division Setting
bits : 8 - 10 (3 bit)
access : read-write


CTSUSO0

CTSU Sensor Offset Register 0
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUSO0 CTSUSO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CTSUSO1

CTSU Sensor Offset Register 1
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUSO1 CTSUSO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CTSUSC

CTSU Sensor Counter
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CTSUSC CTSUSC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CTSURC

CTSU Reference Counter
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CTSURC CTSURC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTSURC

CTSURC : CTSU Reference Counter
bits : 0 - 14 (15 bit)
access : read-only


CTSUERRS

CTSU Error Status Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUERRS CTSUERRS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTSUSPMD CTSUTSOD CTSUDRV CTSUTSOC CTSUICOMP

CTSUSPMD : Calibration Mode
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

Capacitance measurement mode

#10 : 10

Calibration mode

: Others

Seting prohibited

End of enumeration elements list.

CTSUTSOD : TS Pin Fixed Output
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Capacitance measurement mode

#1 : 1

TS pins are forced to be high or low

End of enumeration elements list.

CTSUDRV : Calibration Setting 1
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Capacitance measurement mode

#1 : 1

Calibration setting 1

End of enumeration elements list.

CTSUTSOC : Calibration Setting 2
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Capacitance measurement mode

#1 : 1

Calibration setting 2

End of enumeration elements list.

CTSUICOMP : TSCAP Voltage Error Monitor
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Normal TSCAP voltage

#1 : 1

Abnormal TSCAP voltage

End of enumeration elements list.


CTSUSDPRS

CTSU Synchronous Noise Reduction Setting Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUSDPRS CTSUSDPRS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CTSUTRMR

CTSU Reference Current Calibration Register
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUTRMR CTSUTRMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CTSUSST

CTSU Sensor Stabilization Wait Control Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUSST CTSUSST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CTSUMCH0

CTSU Measurement Channel Register 0
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUMCH0 CTSUMCH0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CTSUMCH1

CTSU Measurement Channel Register 1
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CTSUMCH1 CTSUMCH1 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CTSUCHAC0

CTSU Channel Enable Control Register 0
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHAC0 CTSUCHAC0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CTSUCHAC1

CTSU Channel Enable Control Register 1
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHAC1 CTSUCHAC1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CTSUCHAC2

CTSU Channel Enable Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHAC2 CTSUCHAC2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CTSUCHTRC0

CTSU Channel Transmit/Receive Control Register 0
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHTRC0 CTSUCHTRC0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CTSUCHTRC1

CTSU Channel Transmit/Receive Control Register 1
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHTRC1 CTSUCHTRC1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CTSUCHTRC2

CTSU Channel Transmit/Receive Control Register 2
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHTRC2 CTSUCHTRC2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0


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