Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x48 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x88 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xB8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xD0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
General PWM Timer Write-Protection Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WP : Register Write Disable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write to the register enabled
#1 : 1
Write to the register disabled
End of enumeration elements list.
STRWP : GTSTR.CSTRT Bit Write Disable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write to the bit is enabled
#1 : 1
Write to the bit is disabled
End of enumeration elements list.
STPWP : GTSTP.CSTOP Bit Write Disable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write to the bit is enabled
#1 : 1
Write to the bit is disabled
End of enumeration elements list.
CLRWP : GTCLR.CCLR Bit Write Disable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write to the bit is enabled
#1 : 1
Write to the bit is disabled
End of enumeration elements list.
CMNWP : Common Register Write Disabled
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write to the register is enabled
#1 : 1
Write to the register is disabled
End of enumeration elements list.
PRKEY : GTWP Key Code
bits : 8 - 14 (7 bit)
access : read-write
General PWM Timer Start Source Select Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSGTRGAR : GTETRGA Pin Rising Input Source Counter Start Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled on the rising edge of GTETRGA input
#1 : 1
Counter start enabled on the rising edge of GTETRGA input
End of enumeration elements list.
SSGTRGAF : GTETRGA Pin Falling Input Source Counter Start Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled on the falling edge of GTETRGA input
#1 : 1
Counter start enabled on the falling edge of GTETRGA input
End of enumeration elements list.
SSGTRGBR : GTETRGB Pin Rising Input Source Counter Start Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled on the rising edge of GTETRGB input
#1 : 1
Counter start enabled on the rising edge of GTETRGB input
End of enumeration elements list.
SSGTRGBF : GTETRGB Pin Falling Input Source Counter Start Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled on the falling edge of GTETRGB input
#1 : 1
Counter start enabled on the falling edge of GTETRGB input
End of enumeration elements list.
SSGTRGCR : GTETRGC Pin Rising Input Source Counter Start Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled on the rising edge of GTETRGC input
#1 : 1
Counter start enabled on the rising edge of GTETRGC input
End of enumeration elements list.
SSGTRGCF : GTETRGC Pin Falling Input Source Counter Start Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled on the falling edge of GTETRGC input
#1 : 1
Counter start enabled on the falling edge of GTETRGC input
End of enumeration elements list.
SSGTRGDR : GTETRGD Pin Rising Input Source Counter Start Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled on the rising edge of GTETRGD input
#1 : 1
Counter start enabled on the rising edge of GTETRGD input
End of enumeration elements list.
SSGTRGDF : GTETRGD Pin Falling Input Source Counter Start Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled on the falling edge of GTETRGD input
#1 : 1
Counter start enabled on the falling edge of GTETRGD input
End of enumeration elements list.
SSCARBL : GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
#1 : 1
Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
End of enumeration elements list.
SSCARBH : GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
#1 : 1
Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
End of enumeration elements list.
SSCAFBL : GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
#1 : 1
Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
End of enumeration elements list.
SSCAFBH : GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
#1 : 1
Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
End of enumeration elements list.
SSCBRAL : GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
#1 : 1
Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
End of enumeration elements list.
SSCBRAH : GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
#1 : 1
Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
End of enumeration elements list.
SSCBFAL : GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
#1 : 1
Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
End of enumeration elements list.
SSCBFAH : GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
#1 : 1
Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
End of enumeration elements list.
SSELCA : ELC_GPTA Event Source Counter Start Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled at the ELC_GPTA input
#1 : 1
Counter start enabled at the ELC_GPTA input
End of enumeration elements list.
SSELCB : ELC_GPTB Event Source Counter Start Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled at the ELC_GPTB input
#1 : 1
Counter start enabled at the ELC_GPTB input
End of enumeration elements list.
SSELCC : ELC_GPTC Event Source Counter Start Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled at the ELC_GPTC input
#1 : 1
Counter start enabled at the ELC_GPTC input
End of enumeration elements list.
SSELCD : ELC_GPTD Event Source Counter Start Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled at the ELC_GPTD input
#1 : 1
Counter start enabled at the ELC_GPTD input
End of enumeration elements list.
SSELCE : ELC_GPTE Event Source Counter Start Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled at the ELC_GPTE input
#1 : 1
Counter start enabled at the ELC_GPTE input
End of enumeration elements list.
SSELCF : ELC_GPTF Event Source Counter Start Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled at the ELC_GPTF input
#1 : 1
Counter start enabled at the ELC_GPTF input
End of enumeration elements list.
SSELCG : ELC_GPTG Event Source Counter Start Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled at the ELC_GPTG input
#1 : 1
Counter start enabled at the ELC_GPTG input
End of enumeration elements list.
SSELCH : ELC_GPTH Event Source Counter Start Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled at the ELC_GPTH input
#1 : 1
Counter start enabled at the ELC_GPTH input
End of enumeration elements list.
CSTRT : Software Source Counter Start Enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter start disabled by the GTSTR register
#1 : 1
Counter start enabled by the GTSTR register
End of enumeration elements list.
General PWM Timer Stop Source Select Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSGTRGAR : GTETRGA Pin Rising Input Source Counter Stop Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled on the rising edge of GTETRGA input
#1 : 1
Counter stop enabled on the rising edge of GTETRGA input
End of enumeration elements list.
PSGTRGAF : GTETRGA Pin Falling Input Source Counter Stop Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled on the falling edge of GTETRGA input
#1 : 1
Counter stop enabled on the falling edge of GTETRGA input
End of enumeration elements list.
PSGTRGBR : GTETRGB Pin Rising Input Source Counter Stop Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled on the rising edge of GTETRGB input
#1 : 1
Counter stop enabled on the rising edge of GTETRGB input
End of enumeration elements list.
PSGTRGBF : GTETRGB Pin Falling Input Source Counter Stop Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled on the falling edge of GTETRGB input
#1 : 1
Counter stop enabled on the falling edge of GTETRGB input
End of enumeration elements list.
PSGTRGCR : GTETRGC Pin Rising Input Source Counter Stop Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled on the rising edge of GTETRGC input
#1 : 1
Counter stop enabled on the rising edge of GTETRGC input
End of enumeration elements list.
PSGTRGCF : GTETRGC Pin Falling Input Source Counter Stop Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled on the falling edge of GTETRGC input
#1 : 1
Counter stop enabled on the falling edge of GTETRGC input
End of enumeration elements list.
PSGTRGDR : GTETRGD Pin Rising Input Source Counter Stop Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled on the rising edge of GTETRGD input
#1 : 1
Counter stop enabled on the rising edge of GTETRGD input
End of enumeration elements list.
PSGTRGDF : GTETRGD Pin Falling Input Source Counter Stop Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled on the falling edge of GTETRGD input
#1 : 1
Counter stop enabled on the falling edge of GTETRGD input
End of enumeration elements list.
PSCARBL : GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
#1 : 1
Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
End of enumeration elements list.
PSCARBH : GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
#1 : 1
Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
End of enumeration elements list.
PSCAFBL : GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
#1 : 1
Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
End of enumeration elements list.
PSCAFBH : GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
#1 : 1
Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
End of enumeration elements list.
PSCBRAL : GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
#1 : 1
Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
End of enumeration elements list.
PSCBRAH : GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
#1 : 1
Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
End of enumeration elements list.
PSCBFAL : GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
#1 : 1
Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
End of enumeration elements list.
PSCBFAH : GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
#1 : 1
Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
End of enumeration elements list.
PSELCA : ELC_GPTA Event Source Counter Stop Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled at the ELC_GPTA input
#1 : 1
Counter stop enabled at the ELC_GPTA input
End of enumeration elements list.
PSELCB : ELC_GPTB Event Source Counter Stop Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled at the ELC_GPTB input
#1 : 1
Counter stop enabled at the ELC_GPTB input
End of enumeration elements list.
PSELCC : ELC_GPTC Event Source Counter Stop Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled at the ELC_GPTC input
#1 : 1
Counter stop enabled at the ELC_GPTC input
End of enumeration elements list.
PSELCD : ELC_GPTD Event Source Counter Stop Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled at the ELC_GPTD input
#1 : 1
Counter stop enabled at the ELC_GPTD input
End of enumeration elements list.
PSELCE : ELC_GPTE Event Source Counter Stop Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled at the ELC_GPTE input
#1 : 1
Counter stop enabled at the ELC_GPTE input
End of enumeration elements list.
PSELCF : ELC_GPTF Event Source Counter Stop Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled at the ELC_GPTF input
#1 : 1
Counter stop enabled at the ELC_GPTF input
End of enumeration elements list.
PSELCG : ELC_GPTG Event Source Counter Stop Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled at the ELC_GPTG input
#1 : 1
Counter stop enabled at the ELC_GPTG input
End of enumeration elements list.
PSELCH : ELC_GPTH Event Source Counter Stop Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled at the ELC_GPTH input
#1 : 1
Counter stop enabled at the ELC_GPTH input
End of enumeration elements list.
CSTOP : Software Source Counter Stop Enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter stop disabled by the GTSTP register
#1 : 1
Counter stop enabled by the GTSTP register
End of enumeration elements list.
General PWM Timer Clear Source Select Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGTRGAR : GTETRGA Pin Rising Input Source Counter Clear Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled on the rising edge of GTETRGA input
#1 : 1
Counter clear enabled on the rising edge of GTETRGA input
End of enumeration elements list.
CSGTRGAF : GTETRGA Pin Falling Input Source Counter Clear Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled on the falling edge of GTETRGA input
#1 : 1
Counter clear enabled on the falling edge of GTETRGA input
End of enumeration elements list.
CSGTRGBR : GTETRGB Pin Rising Input Source Counter Clear Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable counter clear on the rising edge of GTETRGB input
#1 : 1
Enable counter clear on the rising edge of GTETRGB input
End of enumeration elements list.
CSGTRGBF : GTETRGB Pin Falling Input Source Counter Clear Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled on the falling edge of GTETRGB input
#1 : 1
Counter clear enabled on the falling edge of GTETRGB input
End of enumeration elements list.
CSGTRGCR : GTETRGC Pin Rising Input Source Counter Clear Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable counter clear on the rising edge of GTETRGC input
#1 : 1
Enable counter clear on the rising edge of GTETRGC input
End of enumeration elements list.
CSGTRGCF : GTETRGC Pin Falling Input Source Counter Clear Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled on the falling edge of GTETRGC input
#1 : 1
Counter clear enabled on the falling edge of GTETRGC input
End of enumeration elements list.
CSGTRGDR : GTETRGD Pin Rising Input Source Counter Clear Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable counter clear on the rising edge of GTETRGD input
#1 : 1
Enable counter clear on the rising edge of GTETRGD input
End of enumeration elements list.
CSGTRGDF : GTETRGD Pin Falling Input Source Counter Clear Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled on the falling edge of GTETRGD input
#1 : 1
Counter clear enabled on the falling edge of GTETRGD input
End of enumeration elements list.
CSCARBL : GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
#1 : 1
Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
End of enumeration elements list.
CSCARBH : GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
#1 : 1
Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
End of enumeration elements list.
CSCAFBL : GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
#1 : 1
Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
End of enumeration elements list.
CSCAFBH : GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
#1 : 1
Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
End of enumeration elements list.
CSCBRAL : GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
#1 : 1
Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
End of enumeration elements list.
CSCBRAH : GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
#1 : 1
Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
End of enumeration elements list.
CSCBFAL : GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
#1 : 1
Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
End of enumeration elements list.
CSCBFAH : GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
#1 : 1
Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
End of enumeration elements list.
CSELCA : ELC_GPTA Event Source Counter Clear Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled at the ELC_GPTA input
#1 : 1
Counter clear enabled at the ELC_GPTA input
End of enumeration elements list.
CSELCB : ELC_GPTB Event Source Counter Clear Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled at the ELC_GPTB input
#1 : 1
Counter clear enabled at the ELC_GPTB input
End of enumeration elements list.
CSELCC : ELC_GPTC Event Source Counter Clear Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled at the ELC_GPTC input
#1 : 1
Counter clear enabled at the ELC_GPTC input
End of enumeration elements list.
CSELCD : ELC_GPTD Event Source Counter Clear Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled at the ELC_GPTD input
#1 : 1
Counter clear enabled at the ELC_GPTD input
End of enumeration elements list.
CSELCE : ELC_GPTE Event Source Counter Clear Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled at the ELC_GPTE input
#1 : 1
Counter clear enabled at the ELC_GPTE input
End of enumeration elements list.
CSELCF : ELC_GPTF Event Source Counter Clear Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled at the ELC_GPTF input
#1 : 1
Counter clear enabled at the ELC_GPTF input
End of enumeration elements list.
CSELCG : ELC_GPTG Event Source Counter Clear Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled at the ELC_GPTG input
#1 : 1
Counter clear enabled at the ELC_GPTG input
End of enumeration elements list.
CSELCH : ELC_GPTH Event Source Counter Clear Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled at the ELC_GPTH input
#1 : 1
Counter clear enabled at the ELC_GPTH input
End of enumeration elements list.
CCLR : Software Source Counter Clear Enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter clear disabled by the GTCLR register
#1 : 1
Counter clear enabled by the GTCLR register
End of enumeration elements list.
General PWM Timer Up Count Source Select Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USGTRGAR : GTETRGA Pin Rising Input Source Counter Count Up Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled on the rising edge of GTETRGA input
#1 : 1
Counter count up enabled on the rising edge of GTETRGA input
End of enumeration elements list.
USGTRGAF : GTETRGA Pin Falling Input Source Counter Count Up Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled on the falling edge of GTETRGA input
#1 : 1
Counter count up enabled on the falling edge of GTETRGA input
End of enumeration elements list.
USGTRGBR : GTETRGB Pin Rising Input Source Counter Count Up Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled on the rising edge of GTETRGB input
#1 : 1
Counter count up enabled on the rising edge of GTETRGB input
End of enumeration elements list.
USGTRGBF : GTETRGB Pin Falling Input Source Counter Count Up Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled on the falling edge of GTETRGB input
#1 : 1
Counter count up enabled on the falling edge of GTETRGB input
End of enumeration elements list.
USGTRGCR : GTETRGC Pin Rising Input Source Counter Count Up Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled on the rising edge of GTETRGC input
#1 : 1
Counter count up enabled on the rising edge of GTETRGC input
End of enumeration elements list.
USGTRGCF : GTETRGC Pin Falling Input Source Counter Count Up Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled on the falling edge of GTETRGC input
#1 : 1
Counter count up enabled on the falling edge of GTETRGC input
End of enumeration elements list.
USGTRGDR : GTETRGD Pin Rising Input Source Counter Count Up Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled on the rising edge of GTETRGD input
#1 : 1
Counter count up enabled on the rising edge of GTETRGD input
End of enumeration elements list.
USGTRGDF : GTETRGD Pin Falling Input Source Counter Count Up Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled on the falling edge of GTETRGD input
#1 : 1
Counter count up enabled on the falling edge of GTETRGD input
End of enumeration elements list.
USCARBL : GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
#1 : 1
Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
End of enumeration elements list.
USCARBH : GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
#1 : 1
Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
End of enumeration elements list.
USCAFBL : GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
#1 : 1
Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
End of enumeration elements list.
USCAFBH : GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
#1 : 1
Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
End of enumeration elements list.
USCBRAL : GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
#1 : 1
Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
End of enumeration elements list.
USCBRAH : GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
#1 : 1
Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
End of enumeration elements list.
USCBFAL : GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
#1 : 1
Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
End of enumeration elements list.
USCBFAH : GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
#1 : 1
Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
End of enumeration elements list.
USELCA : ELC_GPTA Event Source Counter Count Up Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled at the ELC_GPTA input
#1 : 1
Counter count up enabled at the ELC_GPTA input
End of enumeration elements list.
USELCB : ELC_GPTB Event Source Counter Count Up Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled at the ELC_GPTB input
#1 : 1
Counter count up enabled at the ELC_GPTB input
End of enumeration elements list.
USELCC : ELC_GPTC Event Source Counter Count Up Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled at the ELC_GPTC input
#1 : 1
Counter count up enabled at the ELC_GPTC input
End of enumeration elements list.
USELCD : ELC_GPTD Event Source Counter Count Up Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled at the ELC_GPTD input
#1 : 1
Counter count up enabled at the ELC_GPTD input
End of enumeration elements list.
USELCE : ELC_GPTE Event Source Counter Count Up Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled at the ELC_GPTE input
#1 : 1
Counter count up enabled at the ELC_GPTE input
End of enumeration elements list.
USELCF : ELC_GPTF Event Source Counter Count Up Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled at the ELC_GPTF input
#1 : 1
Counter count up enabled at the ELC_GPTF input
End of enumeration elements list.
USELCG : ELC_GPTG Event Source Counter Count Up Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled at the ELC_GPTG input
#1 : 1
Counter count up enabled at the ELC_GPTG input
End of enumeration elements list.
USELCH : ELC_GPTH Event Source Counter Count Up Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count up disabled at the ELC_GPTH input
#1 : 1
Counter count up enabled at the ELC_GPTH input
End of enumeration elements list.
General PWM Timer Down Count Source Select Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSGTRGAR : GTETRGA Pin Rising Input Source Counter Count Down Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled on the rising edge of GTETRGA input
#1 : 1
Counter count down enabled on the rising edge of GTETRGA input
End of enumeration elements list.
DSGTRGAF : GTETRGA Pin Falling Input Source Counter Count Down Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled on the falling edge of GTETRGA input
#1 : 1
Counter count down enabled on the falling edge of GTETRGA input
End of enumeration elements list.
DSGTRGBR : GTETRGB Pin Rising Input Source Counter Count Down Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled on the rising edge of GTETRGB input
#1 : 1
Counter count down enabled on the rising edge of GTETRGB input
End of enumeration elements list.
DSGTRGBF : GTETRGB Pin Falling Input Source Counter Count Down Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled on the falling edge of GTETRGB input
#1 : 1
Counter count down enabled on the falling edge of GTETRGB input
End of enumeration elements list.
DSGTRGCR : GTETRGC Pin Rising Input Source Counter Count Down Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled on the rising edge of GTETRGC input
#1 : 1
Counter count down enabled on the rising edge of GTETRGC input
End of enumeration elements list.
DSGTRGCF : GTETRGC Pin Falling Input Source Counter Count Down Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled on the falling edge of GTETRGC input
#1 : 1
Counter count down enabled on the falling edge of GTETRGC input
End of enumeration elements list.
DSGTRGDR : GTETRGD Pin Rising Input Source Counter Count Down Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled on the rising edge of GTETRGD input
#1 : 1
Counter count down enabled on the rising edge of GTETRGD input
End of enumeration elements list.
DSGTRGDF : GTETRGD Pin Falling Input Source Counter Count Down Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled on the falling edge of GTETRGD input
#1 : 1
Counter count down enabled on the falling edge of GTETRGD input
End of enumeration elements list.
DSCARBL : GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
#1 : 1
Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
End of enumeration elements list.
DSCARBH : GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
#1 : 1
Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
End of enumeration elements list.
DSCAFBL : GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
#1 : 1
Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
End of enumeration elements list.
DSCAFBH : GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
#1 : 1
Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
End of enumeration elements list.
DSCBRAL : GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
#1 : 1
Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
End of enumeration elements list.
DSCBRAH : GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
#1 : 1
Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
End of enumeration elements list.
DSCBFAL : GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
#1 : 1
Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
End of enumeration elements list.
DSCBFAH : GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
#1 : 1
Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
End of enumeration elements list.
DSELCA : ELC_GPTA Event Source Counter Count Down Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled at the ELC_GPTA input
#1 : 1
Counter count down enabled at the ELC_GPTA input
End of enumeration elements list.
DSELCB : ELC_GPTB Event Source Counter Count Down Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled at the ELC_GPTB input
#1 : 1
Counter count down enabled at the ELC_GPTB input
End of enumeration elements list.
DSELCC : ELC_GPTC Event Source Counter Count Down Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled at the ELC_GPTC input
#1 : 1
Counter count down enabled at the ELC_GPTC input
End of enumeration elements list.
DSELCD : ELC_GPTD Event Source Counter Count Down Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled at the ELC_GPTD input
#1 : 1
Counter count down enabled at the ELC_GPTD input
End of enumeration elements list.
DSELCE : ELC_GPTE Event Source Counter Count Down Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled at the ELC_GPTE input
#1 : 1
Counter count down enabled at the ELC_GPTE input
End of enumeration elements list.
DSELCF : ELC_GPTF Event Source Counter Count Down Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled at the ELC_GPTF input
#1 : 1
Counter count down enabled at the ELC_GPTF input
End of enumeration elements list.
DSELCG : ELC_GPTG Event Source Counter Count Down Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled at the ELC_GPTG input
#1 : 1
Counter count down enabled at the ELC_GPTG input
End of enumeration elements list.
DSELCH : ELC_GPTF Event Source Counter Count Down Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Counter count down disabled at the ELC_GPTF input
#1 : 1
Counter count down enabled at the ELC_GPTF input
End of enumeration elements list.
General PWM Timer Input Capture Source Select Register A
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ASGTRGAR : GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled on the rising edge of GTETRGA input
#1 : 1
GTCCRA input capture enabled on the rising edge of GTETRGA input
End of enumeration elements list.
ASGTRGAF : GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled on the falling edge of GTETRGA input
#1 : 1
GTCCRA input capture enabled on the falling edge of GTETRGA input
End of enumeration elements list.
ASGTRGBR : GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled on the rising edge of GTETRGB input
#1 : 1
GTCCRA input capture enabled on the rising edge of GTETRGB input
End of enumeration elements list.
ASGTRGBF : GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled on the falling edge of GTETRGB input
#1 : 1
GTCCRA input capture enabled on the falling edge of GTETRGB input
End of enumeration elements list.
ASGTRGCR : GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled on the rising edge of GTETRGC input
#1 : 1
GTCCRA input capture enabled on the rising edge of GTETRGC input
End of enumeration elements list.
ASGTRGCF : GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled on the falling edge of GTETRGC input
#1 : 1
GTCCRA input capture enabled on the falling edge of GTETRGC input
End of enumeration elements list.
ASGTRGDR : GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled on the rising edge of GTETRGD input
#1 : 1
GTCCRA input capture enabled on the rising edge of GTETRGD input
End of enumeration elements list.
ASGTRGDF : GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled on the falling edge of GTETRGD input
#1 : 1
GTCCRA input capture enabled on the falling edge of GTETRGD input
End of enumeration elements list.
ASCARBL : GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
#1 : 1
GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
End of enumeration elements list.
ASCARBH : GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
#1 : 1
GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
End of enumeration elements list.
ASCAFBL : GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
#1 : 1
GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
End of enumeration elements list.
ASCAFBH : GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
#1 : 1
GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
End of enumeration elements list.
ASCBRAL : GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
#1 : 1
GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
End of enumeration elements list.
ASCBRAH : GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
#1 : 1
GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
End of enumeration elements list.
ASCBFAL : GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
#1 : 1
GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
End of enumeration elements list.
ASCBFAH : GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
#1 : 1
GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
End of enumeration elements list.
ASELCA : ELC_GPTA Event Source GTCCRA Input Capture Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled at the ELC_GPTA input
#1 : 1
GTCCRA input capture enabled at the ELC_GPTA input
End of enumeration elements list.
ASELCB : ELC_GPTB Event Source GTCCRA Input Capture Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled at the ELC_GPTB input
#1 : 1
GTCCRA input capture enabled at the ELC_GPTB input
End of enumeration elements list.
ASELCC : ELC_GPTC Event Source GTCCRA Input Capture Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled at the ELC_GPTC input
#1 : 1
GTCCRA input capture enabled at the ELC_GPTC input
End of enumeration elements list.
ASELCD : ELC_GPTD Event Source GTCCRA Input Capture Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled at the ELC_GPTD input
#1 : 1
GTCCRA input capture enabled at the ELC_GPTD input
End of enumeration elements list.
ASELCE : ELC_GPTE Event Source GTCCRA Input Capture Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled at the ELC_GPTE input
#1 : 1
GTCCRA input capture enabled at the ELC_GPTE input
End of enumeration elements list.
ASELCF : ELC_GPTF Event Source GTCCRA Input Capture Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled at the ELC_GPTF input
#1 : 1
GTCCRA input capture enabled at the ELC_GPTF input
End of enumeration elements list.
ASELCG : ELC_GPTG Event Source GTCCRA Input Capture Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled at the ELC_GPTG input
#1 : 1
GTCCRA input capture enabled at the ELC_GPTG input
End of enumeration elements list.
ASELCH : ELC_GPTH Event Source GTCCRA Input Capture Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRA input capture disabled at the ELC_GPTH input
#1 : 1
GTCCRA input capture enabled at the ELC_GPTH input
End of enumeration elements list.
General PWM Timer Input Capture Source Select Register B
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSGTRGAR : GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled on the rising edge of GTETRGA input
#1 : 1
GTCCRB input capture enabled on the rising edge of GTETRGA input
End of enumeration elements list.
BSGTRGAF : GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled on the falling edge of GTETRGA input
#1 : 1
GTCCRB input capture enabled on the falling edge of GTETRGA input
End of enumeration elements list.
BSGTRGBR : GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled on the rising edge of GTETRGB input
#1 : 1
GTCCRB input capture enabled on the rising edge of GTETRGB input
End of enumeration elements list.
BSGTRGBF : GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled on the falling edge of GTETRGB input
#1 : 1
GTCCRB input capture enabled on the falling edge of GTETRGB input
End of enumeration elements list.
BSGTRGCR : GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled on the rising edge of GTETRGC input
#1 : 1
GTCCRB input capture enabled on the rising edge of GTETRGC input
End of enumeration elements list.
BSGTRGCF : GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled on the falling edge of GTETRGC input
#1 : 1
GTCCRB input capture enabled on the falling edge of GTETRGC input
End of enumeration elements list.
BSGTRGDR : GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled on the rising edge of GTETRGD input
#1 : 1
GTCCRB input capture enabled on the rising edge of GTETRGD input
End of enumeration elements list.
BSGTRGDF : GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled on the falling edge of GTETRGD input
#1 : 1
GTCCRB input capture enabled on the falling edge of GTETRGD input
End of enumeration elements list.
BSCARBL : GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
#1 : 1
GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
End of enumeration elements list.
BSCARBH : GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
#1 : 1
GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
End of enumeration elements list.
BSCAFBL : GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
#1 : 1
GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
End of enumeration elements list.
BSCAFBH : GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
#1 : 1
GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
End of enumeration elements list.
BSCBRAL : GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
#1 : 1
GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
End of enumeration elements list.
BSCBRAH : GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
#1 : 1
GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
End of enumeration elements list.
BSCBFAL : GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
#1 : 1
GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
End of enumeration elements list.
BSCBFAH : GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
#1 : 1
GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
End of enumeration elements list.
BSELCA : ELC_GPTA Event Source GTCCRB Input Capture Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled at the ELC_GPTA input
#1 : 1
GTCCRB input capture enabled at the ELC_GPTA input
End of enumeration elements list.
BSELCB : ELC_GPTB Event Source GTCCRB Input Capture Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled at the ELC_GPTB input
#1 : 1
GTCCRB input capture enabled at the ELC_GPTB input
End of enumeration elements list.
BSELCC : ELC_GPTC Event Source GTCCRB Input Capture Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled at the ELC_GPTC input
#1 : 1
GTCCRB input capture enabled at the ELC_GPTC input
End of enumeration elements list.
BSELCD : ELC_GPTD Event Source GTCCRB Input Capture Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled at the ELC_GPTD input
#1 : 1
GTCCRB input capture enabled at the ELC_GPTD input
End of enumeration elements list.
BSELCE : ELC_GPTE Event Source GTCCRB Input Capture Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled at the ELC_GPTE input
#1 : 1
GTCCRB input capture enabled at the ELC_GPTE input
End of enumeration elements list.
BSELCF : ELC_GPTF Event Source GTCCRB Input Capture Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled at the ELC_GPTF input
#1 : 1
GTCCRB input capture enabled at the ELC_GPTF input
End of enumeration elements list.
BSELCG : ELC_GPTG Event Source GTCCRB Input Capture Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled at the ELC_GPTG input
#1 : 1
GTCCRB input capture enabled at the ELC_GPTG input
End of enumeration elements list.
BSELCH : ELC_GPTH Event Source GTCCRB Input Capture Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB input capture disabled at the ELC_GPTH input
#1 : 1
GTCCRB input capture enabled at the ELC_GPTH input
End of enumeration elements list.
General PWM Timer Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CST : Count Start
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Count operation is stopped
#1 : 1
Count operation is performed
End of enumeration elements list.
MD : Mode Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#000 : 000
Saw-wave PWM mode (single buffer or double buffer possible)
#001 : 001
Saw-wave one-shot pulse mode (fixed buffer operation)
#010 : 010
Setting prohibited
#011 : 011
Setting prohibited
#100 : 100
Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible)
#101 : 101
Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible)
#110 : 110
Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation)
#111 : 111
Setting prohibited
End of enumeration elements list.
TPCS : Timer Prescaler Select
bits : 23 - 25 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
PCLKD/1
0x1 : 0x1
PCLKD/2
0x2 : 0x2
PCLKD/4
0x3 : 0x3
PCLKD/8
0x4 : 0x4
PCLKD/16
0x5 : 0x5
PCLKD/32
0x6 : 0x6
PCLKD/64
0x7 : 0x7
Setting prohibited
0x8 : 0x8
PCLKD/256
0x9 : 0x9
Setting prohibited
0xa : 0xA
PCLKD/1024
0xb : 0xB
Setting prohibited
0xc : 0xC
GTETRGA (Via the POEG)
0xd : 0xD
GTETRGB (Via the POEG)
0xe : 0xE
GTETRGC (Via the POEG)
0xf : 0xF
GTETRGD (Via the POEG)
End of enumeration elements list.
General PWM Timer Count Direction and Duty Setting Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UD : Count Direction Setting
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counts down
#1 : 1
GTCNT counts up
End of enumeration elements list.
UDF : Forcible Count Direction Setting
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not forcibly set
#1 : 1
Forcibly set
End of enumeration elements list.
OADTY : GTIOCnA Output Duty Setting
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : 00
GTIOCnA pin duty depends on the compare match
#01 : 01
GTIOCnA pin duty depends on the compare match
#10 : 10
GTIOCnA pin duty 0%
#11 : 11
GTIOCnA pin duty 100%
End of enumeration elements list.
OADTYF : Forcible GTIOCnA Output Duty Setting
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not forcibly set
#1 : 1
Forcibly set
End of enumeration elements list.
OADTYR : GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Apply output value set in 0%/100% duty to GTIOA[3:2] function after releasing 0%/100% duty setting
#1 : 1
Apply masked compare match output value to GTIOA[3:2] function after releasing 0%/100% duty setting
End of enumeration elements list.
OBDTY : GTIOCnB Output Duty Setting
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#00 : 00
GTIOCnB pin duty depends on the compare match
#01 : 01
GTIOCnB pin duty depends on the compare match
#10 : 10
GTIOCnB pin duty 0%
#11 : 11
GTIOCnB pin duty 100%
End of enumeration elements list.
OBDTYF : Forcible GTIOCnB Output Duty Setting
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not forcibly set
#1 : 1
Forcibly set
End of enumeration elements list.
OBDTYR : GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
Apply output value set in 0%/100% duty to GTIOB[3:2] function after releasing 0%/100% duty setting
#1 : 1
Apply masked compare match output value to GTIOB[3:2] function after releasing 0%/100% duty setting
End of enumeration elements list.
General PWM Timer I/O Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTIOA : GTIOCnA Pin Function Select
bits : 0 - 3 (4 bit)
access : read-write
OADFLT : GTIOCnA Pin Output Value Setting at the Count Stop
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
The GTIOCnA pin outputs low when counting stops
#1 : 1
The GTIOCnA pin outputs high when counting stops
End of enumeration elements list.
OAHLD : GTIOCnA Pin Output Setting at the Start/Stop Count
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
The GTIOCnA pin output level at the start or stop of counting depends on the register setting
#1 : 1
The GTIOCnA pin output level is retained at the start or stop of counting
End of enumeration elements list.
OAE : GTIOCnA Pin Output Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output is disabled
#1 : 1
Output is enabled
End of enumeration elements list.
OADF : GTIOCnA Pin Disable Value Setting
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#00 : 00
Output disable is prohibited
#01 : 01
GTIOCnA pin is set to Hi-Z on output disable
#10 : 10
GTIOCnA pin is set to 0 on output disable
#11 : 11
GTIOCnA pin is set to 1 on output disable
End of enumeration elements list.
NFAEN : Noise Filter A Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
The noise filter for the GTIOCnA pin is disabled
#1 : 1
The noise filter for the GTIOCnA pin is enabled
End of enumeration elements list.
NFCSA : Noise Filter A Sampling Clock Select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKD/1
#01 : 01
PCLKD/4
#10 : 10
PCLKD/16
#11 : 11
PCLKD/64
End of enumeration elements list.
GTIOB : GTIOCnB Pin Function Select
bits : 16 - 19 (4 bit)
access : read-write
OBDFLT : GTIOCnB Pin Output Value Setting at the Count Stop
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
The GTIOCnB pin outputs low when counting stops
#1 : 1
The GTIOCnB pin outputs high when counting stops
End of enumeration elements list.
OBHLD : GTIOCnB Pin Output Setting at the Start/Stop Count
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
The GTIOCnB pin output level at the start/stop of counting depends on the register setting
#1 : 1
The GTIOCnB pin output level is retained at the start/stop of counting
End of enumeration elements list.
OBE : GTIOCnB Pin Output Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Output is disabled
#1 : 1
Output is enabled
End of enumeration elements list.
OBDF : GTIOCnB Pin Disable Value Setting
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#00 : 00
Output disable is prohibited
#01 : 01
GTIOCnB pin is set to Hi-Z on output disable
#10 : 10
GTIOCnB pin is set to 0 on output disable
#11 : 11
GTIOCnB pin is set to 1 on output disable
End of enumeration elements list.
NFBEN : Noise Filter B Enable
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
The noise filter for the GTIOCnB pin is disabled
#1 : 1
The noise filter for the GTIOCnB pin is enabled
End of enumeration elements list.
NFCSB : Noise Filter B Sampling Clock Select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKD/1
#01 : 01
PCLKD/4
#10 : 10
PCLKD/16
#11 : 11
PCLKD/64
End of enumeration elements list.
General PWM Timer Interrupt Output Setting Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GRP : Output Disable Source Select
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#00 : 00
Group A output disable request is selected
#01 : 01
Group B output disable request is selected
#10 : 10
Group C output disable request is selected
#11 : 11
Group D output disable request is selected
End of enumeration elements list.
GRPABH : Same Time Output Level High Disable Request Enable
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
Same time output level high disable request disabled
#1 : 1
Same time output level high disable request enabled
End of enumeration elements list.
GRPABL : Same Time Output Level Low Disable Request Enable
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Same time output level low disable request disabled
#1 : 1
Same time output level low disable request enabled
End of enumeration elements list.
GTINTPC : Period Count Function Finish Interrupt Enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request is disabled
#1 : 1
Interrupt request is enabled
End of enumeration elements list.
General PWM Timer Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCFA : Input Capture/Compare Match Flag A
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No input capture/compare match of GTCCRA is generated
#1 : 1
An input capture/compare match of GTCCRA is generated
End of enumeration elements list.
TCFB : Input Capture/Compare Match Flag B
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
No input capture/compare match of GTCCRB is generated
#1 : 1
An input capture/compare match of GTCCRB is generated
End of enumeration elements list.
TCFC : Input Compare Match Flag C
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No compare match of GTCCRC is generated
#1 : 1
A compare match of GTCCRC is generated
End of enumeration elements list.
TCFD : Input Compare Match Flag D
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No compare match of GTCCRD is generated
#1 : 1
A compare match of GTCCRD is generated
End of enumeration elements list.
TCFE : Input Compare Match Flag E
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No compare match of GTCCRE is generated
#1 : 1
A compare match of GTCCRE is generated
End of enumeration elements list.
TCFF : Input Compare Match Flag F
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
No compare match of GTCCRF is generated
#1 : 1
A compare match of GTCCRF is generated
End of enumeration elements list.
TCFPO : Overflow Flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No overflow (crest) occurred
#1 : 1
An overflow (crest) occurred
End of enumeration elements list.
TCFPU : Underflow Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
No underflow (trough) occurred
#1 : 1
An underflow (trough) occurred
End of enumeration elements list.
TUCF : Count Direction Flag
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
GTCNT counter counts downward
#1 : 1
GTCNT counter counts upward
End of enumeration elements list.
ODF : Output Disable Flag
bits : 24 - 23 (0 bit)
access : read-only
Enumeration:
#0 : 0
No output disable request is generated
#1 : 1
An output disable request is generated
End of enumeration elements list.
OABHF : Same Time Output Level High Flag
bits : 29 - 28 (0 bit)
access : read-only
Enumeration:
#0 : 0
GTIOCnA pin and GTIOCnB pin do not output 1 at the same time
#1 : 1
GTIOCnA pin and GTIOCnB pin output 1 at the same time
End of enumeration elements list.
OABLF : Same Time Output Level Low Flag
bits : 30 - 29 (0 bit)
access : read-only
Enumeration:
#0 : 0
GTIOCnA pin and GTIOCnB pin do not output 0 at the same time
#1 : 1
GTIOCnA pin and GTIOCnB pin output 0 at the same time
End of enumeration elements list.
PCF : Period Count Function Finish Flag
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
No period count function finish has occurred
#1 : 1
A period count function finish has occurred
End of enumeration elements list.
General PWM Timer Software Start Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSTRT0 : Channel n GTCNT Count Start (n : the same as bit position value)
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not start
#1 : 1
GTCNT counter start
End of enumeration elements list.
CSTRT1 : Channel n GTCNT Count Start (n : the same as bit position value)
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not start
#1 : 1
GTCNT counter start
End of enumeration elements list.
CSTRT2 : Channel n GTCNT Count Start (n : the same as bit position value)
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not start
#1 : 1
GTCNT counter start
End of enumeration elements list.
CSTRT3 : Channel n GTCNT Count Start (n : the same as bit position value)
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not start
#1 : 1
GTCNT counter start
End of enumeration elements list.
CSTRT4 : Channel n GTCNT Count Start (n : the same as bit position value)
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not start
#1 : 1
GTCNT counter start
End of enumeration elements list.
CSTRT5 : Channel n GTCNT Count Start (n : the same as bit position value)
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not start
#1 : 1
GTCNT counter start
End of enumeration elements list.
CSTRT6 : Channel n GTCNT Count Start (n : the same as bit position value)
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not start
#1 : 1
GTCNT counter start
End of enumeration elements list.
CSTRT7 : Channel n GTCNT Count Start (n : the same as bit position value)
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not start
#1 : 1
GTCNT counter start
End of enumeration elements list.
CSTRT8 : Channel n GTCNT Count Start (n : the same as bit position value)
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not start
#1 : 1
GTCNT counter start
End of enumeration elements list.
CSTRT9 : Channel n GTCNT Count Start (n : the same as bit position value)
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not start
#1 : 1
GTCNT counter start
End of enumeration elements list.
General PWM Timer Buffer Enable Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BD0 : GTCCR Buffer Operation Disable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Buffer operation is enabled
#1 : 1
Buffer operation is disabled
End of enumeration elements list.
BD1 : GTPR Buffer Operation Disable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Buffer operation is enabled
#1 : 1
Buffer operation is disabled
End of enumeration elements list.
CCRA : GTCCRA Buffer Operation
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : 00
No buffer operation
#01 : 01
Single buffer operation (GTCCRA <---->GTCCRC)
: Others
Double buffer operation (GTCCRA <----> GTCCRC <----> GTCCRD)
End of enumeration elements list.
CCRB : GTCCRB Buffer Operation
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#00 : 00
No buffer operation
#01 : 01
Single buffer operation (GTCCRB <----> GTCCRE)
: Others
Double buffer operation (GTCCRB <----> GTCCRE <----> GTCCRF)
End of enumeration elements list.
PR : GTPR Buffer Operation
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#00 : 00
No buffer operation
#01 : 01
Single buffer operation (GTPBR --> GTPR)
: Others
Setting prohibited
End of enumeration elements list.
CCRSWT : GTCCRA and GTCCRB Forcible Buffer Operation
bits : 22 - 21 (0 bit)
access : read-write
General PWM Timer Counter
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
General PWM Timer Compare Capture Register A
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
General PWM Timer Compare Capture Register B
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
General PWM Timer Compare Capture Register C
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
General PWM Timer Compare Capture Register E
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
General PWM Timer Compare Capture Register D
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
General PWM Timer Compare Capture Register F
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
General PWM Timer Cycle Setting Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
General PWM Timer Cycle Setting Buffer Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
General PWM Timer Software Stop Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSTOP0 : Channel n GTCNT Count Stop (n : the same as bit position value)
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not stop
#1 : 1
GTCNT counter stop
End of enumeration elements list.
CSTOP1 : Channel n GTCNT Count Stop (n : the same as bit position value)
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not stop
#1 : 1
GTCNT counter stop
End of enumeration elements list.
CSTOP2 : Channel n GTCNT Count Stop (n : the same as bit position value)
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not stop
#1 : 1
GTCNT counter stop
End of enumeration elements list.
CSTOP3 : Channel n GTCNT Count Stop (n : the same as bit position value)
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not stop
#1 : 1
GTCNT counter stop
End of enumeration elements list.
CSTOP4 : Channel n GTCNT Count Stop (n : the same as bit position value)
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not stop
#1 : 1
GTCNT counter stop
End of enumeration elements list.
CSTOP5 : Channel n GTCNT Count Stop (n : the same as bit position value)
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not stop
#1 : 1
GTCNT counter stop
End of enumeration elements list.
CSTOP6 : Channel n GTCNT Count Stop (n : the same as bit position value)
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not stop
#1 : 1
GTCNT counter stop
End of enumeration elements list.
CSTOP7 : Channel n GTCNT Count Stop (n : the same as bit position value)
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not stop
#1 : 1
GTCNT counter stop
End of enumeration elements list.
CSTOP8 : Channel n GTCNT Count Stop (n : the same as bit position value)
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not stop
#1 : 1
GTCNT counter stop
End of enumeration elements list.
CSTOP9 : Channel n GTCNT Count Stop (n : the same as bit position value)
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCNT counter not stop
#1 : 1
GTCNT counter stop
End of enumeration elements list.
General PWM Timer Dead Time Control Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDE : Negative-Phase Waveform Setting
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
GTCCRB is set without using GTDVU
#1 : 1
GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB
End of enumeration elements list.
General PWM Timer Dead Time Value Register U
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
General PWM Timer Inter Channel Logical Operation Function Setting Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICLFA : GTIOCnA Output Logical Operation Function Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
A (no delay)
#001 : 001
NOT A (no delay)
#010 : 010
C (1PCLKD delay)
#011 : 011
NOT C (1PCLKD delay)
#100 : 100
A AND C (1PCLKD delay)
#101 : 101
A OR C (1PCLKD delay)
#110 : 110
A EXOR C (1PCLKD delay)
#111 : 111
A NOR C (1PCLKD delay)
End of enumeration elements list.
ICLFSELC : Inter Channel Signal C Select
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0x00 : 0x00
GTIOC0A
0x01 : 0x01
GTIOC0B
0x02 : 0x02
GTIOC1A
0x03 : 0x03
GTIOC1B
0x04 : 0x04
GTIOC2A
0x05 : 0x05
GTIOC2B
0x06 : 0x06
GTIOC3A
0x07 : 0x07
GTIOC3B
0x08 : 0x08
GTIOC4A
0x09 : 0x09
GTIOC4B
0x0a : 0x0A
GTIOC5A
0x0b : 0x0B
GTIOC5B
0x0c : 0x0C
GTIOC6A
0x0d : 0x0D
GTIOC6B
0x0e : 0x0E
GTIOC7A
0x0f : 0x0F
GTIOC7B
0x10 : 0x10
GTIOC8A
0x11 : 0x11
GTIOC8B
0x12 : 0x12
GTIOC9A
0x13 : 0x13
GTIOC9B
: Others
Setting prohibited
End of enumeration elements list.
ICLFB : GTIOCnB Output Logical Operation Function Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#000 : 000
B (no delay)
#001 : 001
NOT B (no delay)
#010 : 010
D (1PCLKD delay)
#011 : 011
NOT D (1PCLKD delay)
#100 : 100
B AND D (1PCLKD delay)
#101 : 101
B OR D (1PCLKDn delay)
#110 : 110
B EXOR D (1PCLKD delay)
#111 : 111
B NOR D (1PCLKD delay)
End of enumeration elements list.
ICLFSELD : Inter Channel Signal D Select
bits : 20 - 24 (5 bit)
access : read-write
Enumeration:
0x00 : 0x00
GTIOC0A
0x01 : 0x01
GTIOC0B
0x02 : 0x02
GTIOC1A
0x03 : 0x03
GTIOC1B
0x04 : 0x04
GTIOC2A
0x05 : 0x05
GTIOC2B
0x06 : 0x06
GTIOC3A
0x07 : 0x07
GTIOC3B
0x08 : 0x08
GTIOC4A
0x09 : 0x09
GTIOC4B
0x0a : 0x0A
GTIOC5A
0x0b : 0x0B
GTIOC5B
0x0c : 0x0C
GTIOC6A
0x0d : 0x0D
GTIOC6B
0x0e : 0x0E
GTIOC7A
0x0f : 0x0F
GTIOC7B
0x10 : 0x10
GTIOC8A
0x11 : 0x11
GTIOC8B
0x12 : 0x12
GTIOC9A
0x13 : 0x13
GTIOC9B
: Others
Setting prohibited
End of enumeration elements list.
General PWM Timer Period Count Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCEN : Period Count Function Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Period count function is disabled
#1 : 1
Period count function is enabled
End of enumeration elements list.
ASTP : Automatic Stop Function Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Automatic stop function is disabled
#1 : 1
Automatic stop function is enabled
End of enumeration elements list.
PCNT : Period Counter
bits : 16 - 26 (11 bit)
access : read-write
General PWM Timer Software Clear Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CCLR0 : Channel n GTCNT Count Clear (n : the same as bit position value)
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : 0
GTCNT counter is not cleared
#1 : 1
GTCNT counter is cleared
End of enumeration elements list.
CCLR1 : Channel n GTCNT Count Clear (n : the same as bit position value)
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : 0
GTCNT counter is not cleared
#1 : 1
GTCNT counter is cleared
End of enumeration elements list.
CCLR2 : Channel n GTCNT Count Clear (n : the same as bit position value)
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : 0
GTCNT counter is not cleared
#1 : 1
GTCNT counter is cleared
End of enumeration elements list.
CCLR3 : Channel n GTCNT Count Clear (n : the same as bit position value)
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : 0
GTCNT counter is not cleared
#1 : 1
GTCNT counter is cleared
End of enumeration elements list.
CCLR4 : Channel n GTCNT Count Clear (n : the same as bit position value)
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : 0
GTCNT counter is not cleared
#1 : 1
GTCNT counter is cleared
End of enumeration elements list.
CCLR5 : Channel n GTCNT Count Clear (n : the same as bit position value)
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
#0 : 0
GTCNT counter is not cleared
#1 : 1
GTCNT counter is cleared
End of enumeration elements list.
CCLR6 : Channel n GTCNT Count Clear (n : the same as bit position value)
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
#0 : 0
GTCNT counter is not cleared
#1 : 1
GTCNT counter is cleared
End of enumeration elements list.
CCLR7 : Channel n GTCNT Count Clear (n : the same as bit position value)
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
GTCNT counter is not cleared
#1 : 1
GTCNT counter is cleared
End of enumeration elements list.
CCLR8 : Channel n GTCNT Count Clear (n : the same as bit position value)
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
GTCNT counter is not cleared
#1 : 1
GTCNT counter is cleared
End of enumeration elements list.
CCLR9 : Channel n GTCNT Count Clear (n : the same as bit position value)
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : 0
GTCNT counter is not cleared
#1 : 1
GTCNT counter is cleared
End of enumeration elements list.
General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECSEL0 : Channel 0 Operation Enable Bit Simultaneous Control Channel Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable simultaneous control
#1 : 1
Enable simultaneous control
End of enumeration elements list.
SECSEL1 : Channel 1 Operation Enable Bit Simultaneous Control Channel Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable simultaneous control
#1 : 1
Enable simultaneous control
End of enumeration elements list.
SECSEL2 : Channel 2 Operation Enable Bit Simultaneous Control Channel Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable simultaneous control
#1 : 1
Enable simultaneous control
End of enumeration elements list.
SECSEL3 : Channel 3 Operation Enable Bit Simultaneous Control Channel Select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable simultaneous control
#1 : 1
Enable simultaneous control
End of enumeration elements list.
SECSEL4 : Channel 4 Operation Enable Bit Simultaneous Control Channel Select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable simultaneous control
#1 : 1
Enable simultaneous control
End of enumeration elements list.
SECSEL5 : Channel 5 Operation Enable Bit Simultaneous Control Channel Select
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable simultaneous control
#1 : 1
Enable simultaneous control
End of enumeration elements list.
SECSEL6 : Channel 6 Operation Enable Bit Simultaneous Control Channel Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable simultaneous control
#1 : 1
Enable simultaneous control
End of enumeration elements list.
SECSEL7 : Channel 7 Operation Enable Bit Simultaneous Control Channel Select
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable simultaneous control
#1 : 1
Enable simultaneous control
End of enumeration elements list.
General PWM Timer Operation Enable Bit Simultaneous Control Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBDCE : GTCCR Register Buffer Operation Simultaneous Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable simultaneous enabling GTCCR buffer operations
#1 : 1
Enable GTCCR register buffer operations simultaneously
End of enumeration elements list.
SBDPE : GTPR Register Buffer Operation Simultaneous Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable simultaneous enabling GTPR buffer operations
#1 : 1
Enable GTPR register buffer operations simultaneously
End of enumeration elements list.
SBDCD : GTCCR Register Buffer Operation Simultaneous Disable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable simultaneous disabling GTCCR buffer operations
#1 : 1
Disable GTCCR register buffer operations simultaneously
End of enumeration elements list.
SBDPD : GTPR Register Buffer Operation Simultaneous Disable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable simultaneous disabling GTPR buffer operations
#1 : 1
Disable GTPR register buffer operations simultaneously
End of enumeration elements list.
SPCE : Period Count Function Simultaneous Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable simultaneous enabling period count function
#1 : 1
Enable period count function simultaneously
End of enumeration elements list.
SPCD : Period Count Function Simultaneous Disable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable simultaneous disabling period count function
#1 : 1
Disable period count function simultaneously
End of enumeration elements list.
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