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BUS

Peripheral Memory Blocks

address_offset : 0x2 Bytes (0x0)
size : 0x86 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x802 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x80A Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1000 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1100 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1110 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1120 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1130 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1140 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1800 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1900 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1A00 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection :

Registers

BUSMCNTM4I

BUSMCNTM4D

BUSSCNTFHBIU

BUSSCNTFLBIU

BUSSCNTS0BIU

BUSSCNTPSBIU

BUSSCNTPLBIU

BUSSCNTPHBIU

BUSSCNTEQBIU

BUSSCNTEOBIU

BUSSCNTECBIU

CS1MOD

CS1WCR1

CS1WCR2

BUS1ERRADD

BUS1ERRRW

BUS2ERRADD

BUS2ERRRW

BUS3ERRADD

BUS3ERRRW

BUS4ERRADD

BUS4ERRRW

BTZF1ERRADD

BTZF1ERRRW

BTZF2ERRADD

BTZF2ERRRW

BTZF3ERRADD

BTZF3ERRRW

BTZF4ERRADD

BTZF4ERRRW

BUS1ERRSTAT

BUS1ERRCLR

BUS2ERRSTAT

BUS2ERRCLR

BUS3ERRSTAT

DMACDTCERRSTAT

BUS3ERRCLR

DMACDTCERRCLR

BUS4ERRSTAT

BUS4ERRCLR

CS0MOD

CS2MOD

CS2WCR1

CS2WCR2

CS3MOD

CS3WCR1

CS3WCR2

CS0WCR1

CS4MOD

CS4WCR1

CS4WCR2

CS5MOD

CS5WCR1

CS5WCR2

CS6MOD

CS6WCR1

CS6WCR2

CS7MOD

CS7WCR1

CS7WCR2

CS0WCR2

CS0CR

CS0REC

CS1CR

CS1REC

CS2CR

CS2REC

CS3CR

CS3REC

CS4CR

CS4REC

CS5CR

CS5REC

CS6CR

CS6REC

CS7CR

CS7REC

CSRECEN


BUSMCNTM4I

Master Bus Control Register %s
address_offset : 0x1000 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSMCNTM4I BUSMCNTM4I read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved IERES

Reserved : These bits are read as 000000000000000. The write value should be 000000000000000.
bits : 0 - 13 (14 bit)
access : read-write

IERES : Ignore Error Responses
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus error will be reported.

#1 : 1

Bus error will not be reported.

End of enumeration elements list.


BUSMCNTM4D

Master Bus Control Register %s
address_offset : 0x1004 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSMCNTM4D BUSMCNTM4D read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved IERES

Reserved : These bits are read as 000000000000000. The write value should be 000000000000000.
bits : 0 - 13 (14 bit)
access : read-write

IERES : Ignore Error Responses
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus error will be reported.

#1 : 1

Bus error will not be reported.

End of enumeration elements list.


BUSSCNTFHBIU

Slave Bus Control Register %s
address_offset : 0x1100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSSCNTFHBIU BUSSCNTFHBIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBS3 Reserved

ARBS3 : ARBitration Select for 3 master
bits : 0 - 0 (1 bit)

Reserved : These bits are read as 00000000000000. The write value should be 00000000000000.
bits : 2 - 14 (13 bit)
access : read-write


BUSSCNTFLBIU

Slave Bus Control Register %s
address_offset : 0x1104 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSSCNTFLBIU BUSSCNTFLBIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBS3 Reserved

ARBS3 : ARBitration Select for 3 master
bits : 0 - 0 (1 bit)

Reserved : These bits are read as 00000000000000. The write value should be 00000000000000.
bits : 2 - 14 (13 bit)
access : read-write


BUSSCNTS0BIU

Slave Bus Control Register S0BIU
address_offset : 0x1110 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSSCNTS0BIU BUSSCNTS0BIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBS3 Reserved

ARBS3 : ARBitration Select for 3 master
bits : 0 - 0 (1 bit)

Reserved : These bits are read as 00000000000000. The write value should be 00000000000000.
bits : 2 - 14 (13 bit)
access : read-write


BUSSCNTPSBIU

Slave Bus Control Register S0BIU
address_offset : 0x1120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSSCNTPSBIU BUSSCNTPSBIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBS2 Reserved

ARBS2 : ARBitration Select for 2 master
bits : 0 - -1 (0 bit)

Reserved : These bits are read as 000000000000000. The write value should be 000000000000000.
bits : 1 - 14 (14 bit)
access : read-write


BUSSCNTPLBIU

Slave Bus Control Register %s
address_offset : 0x1130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSSCNTPLBIU BUSSCNTPLBIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBS2 Reserved

ARBS2 : ARBitration Select for 2 master
bits : 0 - -1 (0 bit)

Reserved : These bits are read as 000000000000000. The write value should be 000000000000000.
bits : 1 - 14 (14 bit)
access : read-write


BUSSCNTPHBIU

Slave Bus Control Register %s
address_offset : 0x1134 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSSCNTPHBIU BUSSCNTPHBIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBS2 Reserved

ARBS2 : ARBitration Select for 2 master
bits : 0 - -1 (0 bit)

Reserved : These bits are read as 000000000000000. The write value should be 000000000000000.
bits : 1 - 14 (14 bit)
access : read-write


BUSSCNTEQBIU

Slave Bus Control Register %s
address_offset : 0x1140 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSSCNTEQBIU BUSSCNTEQBIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBS3 Reserved

ARBS3 : ARBitration Select for 3 master
bits : 0 - 0 (1 bit)

Reserved : These bits are read as 00000000000000. The write value should be 00000000000000.
bits : 2 - 14 (13 bit)
access : read-write


BUSSCNTEOBIU

Slave Bus Control Register %s
address_offset : 0x1144 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSSCNTEOBIU BUSSCNTEOBIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBS3 Reserved

ARBS3 : ARBitration Select for 3 master
bits : 0 - 0 (1 bit)

Reserved : These bits are read as 00000000000000. The write value should be 00000000000000.
bits : 2 - 14 (13 bit)
access : read-write


BUSSCNTECBIU

Slave Bus Control Register %s
address_offset : 0x1148 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSSCNTECBIU BUSSCNTECBIU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBS3 Reserved

ARBS3 : ARBitration Select for 3 master
bits : 0 - 0 (1 bit)

Reserved : These bits are read as 00000000000000. The write value should be 00000000000000.
bits : 2 - 14 (13 bit)
access : read-write


CS1MOD

CS%s Mode Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS1MOD CS1MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB Reserved PRENB PWENB Reserved Reserved PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


CS1WCR1

CS%s Wait Control Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS1WCR1 CS1WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT Reserved CSWWAIT Reserved CSRWAIT Reserved Reserved

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPWWAIT clock cycle is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPRWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSWWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 21 - 22 (2 bit)
access : read-write

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSRWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 29 - 30 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 29 - 30 (2 bit)
access : read-write


CS1WCR2

CS%s Wait Control Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS1WCR2 CS1WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF Reserved WDOFF Reserved AWAIT Reserved RDON Reserved WRON Reserved WDON Reserved CSON Reserved Reserved

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSROFF clock cycle is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSWOFF clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDOFF clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write

AWAIT : Address Cycle Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of AWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 14 - 14 (1 bit)
access : read-write

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of RDON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 19 - 18 (0 bit)
access : read-write

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WRON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 23 - 22 (0 bit)
access : read-write

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 27 - 26 (0 bit)
access : read-write

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 31 - 30 (0 bit)
access : read-write

Reserved : This bit is read as 0. The write value should be 0.
bits : 31 - 30 (0 bit)
access : read-write


BUS1ERRADD

Bus Error Address Register %s
address_offset : 0x1800 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS1ERRADD BUS1ERRADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only


BUS1ERRRW

Bus Error RW Register %s
address_offset : 0x1804 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS1ERRRW BUS1ERRRW read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RWSTAT Reserved

RWSTAT : error access Read/Write STAtus
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#1 : 1

Write access

#0 : 0

Read access

End of enumeration elements list.

Reserved : These bits are read as 0000000.
bits : 1 - 6 (6 bit)
access : read-only


BUS2ERRADD

Bus Error Address Register %s
address_offset : 0x1810 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS2ERRADD BUS2ERRADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only


BUS2ERRRW

Bus Error RW Register %s
address_offset : 0x1814 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS2ERRRW BUS2ERRRW read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RWSTAT Reserved

RWSTAT : error access Read/Write STAtus
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#1 : 1

Write access

#0 : 0

Read access

End of enumeration elements list.

Reserved : These bits are read as 0000000.
bits : 1 - 6 (6 bit)
access : read-only


BUS3ERRADD

Bus Error Address Register %s
address_offset : 0x1820 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS3ERRADD BUS3ERRADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only


BUS3ERRRW

Bus Error RW Register %s
address_offset : 0x1824 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS3ERRRW BUS3ERRRW read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RWSTAT Reserved

RWSTAT : error access Read/Write STAtus
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#1 : 1

Write access

#0 : 0

Read access

End of enumeration elements list.

Reserved : These bits are read as 0000000.
bits : 1 - 6 (6 bit)
access : read-only


BUS4ERRADD

Bus Error Address Register %s
address_offset : 0x1830 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS4ERRADD BUS4ERRADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only


BUS4ERRRW

Bus Error RW Register %s
address_offset : 0x1834 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS4ERRRW BUS4ERRRW read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RWSTAT Reserved

RWSTAT : error access Read/Write STAtus
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#1 : 1

Write access

#0 : 0

Read access

End of enumeration elements list.

Reserved : These bits are read as 0000000.
bits : 1 - 6 (6 bit)
access : read-only


BTZF1ERRADD

Bus TZF Error Address Register %s
address_offset : 0x1900 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BTZF1ERRADD BTZF1ERRADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error Address
bits : 0 - 30 (31 bit)
access : read-only


BTZF1ERRRW

Bus ZTF Error RW Register %s
address_offset : 0x1904 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BTZF1ERRRW BTZF1ERRRW read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRWSTAT Reserved

TRWSTAT : Trust zone filter error access Read/Write STAtus
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#1 : 1

Write access

#0 : 0

Read access

End of enumeration elements list.

Reserved : These bits are read as 0000000.
bits : 1 - 6 (6 bit)
access : read-only


BTZF2ERRADD

Bus TZF Error Address Register %s
address_offset : 0x1910 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BTZF2ERRADD BTZF2ERRADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error Address
bits : 0 - 30 (31 bit)
access : read-only


BTZF2ERRRW

Bus ZTF Error RW Register %s
address_offset : 0x1914 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BTZF2ERRRW BTZF2ERRRW read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRWSTAT Reserved

TRWSTAT : Trust zone filter error access Read/Write STAtus
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#1 : 1

Write access

#0 : 0

Read access

End of enumeration elements list.

Reserved : These bits are read as 0000000.
bits : 1 - 6 (6 bit)
access : read-only


BTZF3ERRADD

Bus TZF Error Address Register %s
address_offset : 0x1920 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BTZF3ERRADD BTZF3ERRADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error Address
bits : 0 - 30 (31 bit)
access : read-only


BTZF3ERRRW

Bus ZTF Error RW Register %s
address_offset : 0x1924 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BTZF3ERRRW BTZF3ERRRW read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRWSTAT Reserved

TRWSTAT : Trust zone filter error access Read/Write STAtus
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#1 : 1

Write access

#0 : 0

Read access

End of enumeration elements list.

Reserved : These bits are read as 0000000.
bits : 1 - 6 (6 bit)
access : read-only


BTZF4ERRADD

Bus TZF Error Address Register %s
address_offset : 0x1930 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BTZF4ERRADD BTZF4ERRADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error Address
bits : 0 - 30 (31 bit)
access : read-only


BTZF4ERRRW

Bus ZTF Error RW Register %s
address_offset : 0x1934 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BTZF4ERRRW BTZF4ERRRW read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRWSTAT Reserved

TRWSTAT : Trust zone filter error access Read/Write STAtus
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#1 : 1

Write access

#0 : 0

Read access

End of enumeration elements list.

Reserved : These bits are read as 0000000.
bits : 1 - 6 (6 bit)
access : read-only


BUS1ERRSTAT

Bus Error Status Register %s
address_offset : 0x1A00 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS1ERRSTAT BUS1ERRSTAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLERRSTAT STERRSTAT SMERRSTAT MMERRSTAT ILERRSTAT Reserved

SLERRSTAT : SLave bus ERRor STATus
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

STERRSTAT : Slave Trust zone filter ERRor STATus
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

SMERRSTAT : Slave Mpu ERRor STATus
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred.

End of enumeration elements list.

MMERRSTAT : Master Mpu ERRor STATus
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

ILERRSTAT : ILlegal address access ERRor STATus
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

Reserved : These bits are read as 000.
bits : 5 - 6 (2 bit)
access : read-only


BUS1ERRCLR

Bus Error Status Register %s
address_offset : 0x1A08 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUS1ERRCLR BUS1ERRCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLERRCLR STERRCLR SMERRCLR MMERRCLR ILERRCLR Reserved

SLERRCLR : SLave bus ERRor CLeaR
bits : 0 - -1 (0 bit)
access : read-write

STERRCLR : Slave Trust zone filter ERRor CLeaR
bits : 1 - 0 (0 bit)
access : read-write

SMERRCLR : Slave Mpu ERRor CLeaR
bits : 2 - 1 (0 bit)
access : read-write

MMERRCLR : Master Mpu ERRor CLeaR
bits : 3 - 2 (0 bit)
access : read-write

ILERRCLR : ILlegal address access ERRor Clear
bits : 4 - 3 (0 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 5 - 6 (2 bit)
access : read-write


BUS2ERRSTAT

Bus Error Status Register %s
address_offset : 0x1A10 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS2ERRSTAT BUS2ERRSTAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLERRSTAT STERRSTAT SMERRSTAT MMERRSTAT ILERRSTAT Reserved

SLERRSTAT : SLave bus ERRor STATus
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

STERRSTAT : Slave Trust zone filter ERRor STATus
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

SMERRSTAT : Slave Mpu ERRor STATus
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred.

End of enumeration elements list.

MMERRSTAT : Master Mpu ERRor STATus
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

ILERRSTAT : ILlegal address access ERRor STATus
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

Reserved : These bits are read as 000.
bits : 5 - 6 (2 bit)
access : read-only


BUS2ERRCLR

Bus Error Status Register %s
address_offset : 0x1A18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUS2ERRCLR BUS2ERRCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLERRCLR STERRCLR SMERRCLR MMERRCLR ILERRCLR Reserved

SLERRCLR : SLave bus ERRor CLeaR
bits : 0 - -1 (0 bit)
access : read-write

STERRCLR : Slave Trust zone filter ERRor CLeaR
bits : 1 - 0 (0 bit)
access : read-write

SMERRCLR : Slave Mpu ERRor CLeaR
bits : 2 - 1 (0 bit)
access : read-write

MMERRCLR : Master Mpu ERRor CLeaR
bits : 3 - 2 (0 bit)
access : read-write

ILERRCLR : ILlegal address access ERRor Clear
bits : 4 - 3 (0 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 5 - 6 (2 bit)
access : read-write


BUS3ERRSTAT

Bus Error Status Register %s
address_offset : 0x1A20 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS3ERRSTAT BUS3ERRSTAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLERRSTAT STERRSTAT SMERRSTAT MMERRSTAT ILERRSTAT Reserved

SLERRSTAT : SLave bus ERRor STATus
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

STERRSTAT : Slave Trust zone filter ERRor STATus
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

SMERRSTAT : Slave Mpu ERRor STATus
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred.

End of enumeration elements list.

MMERRSTAT : Master Mpu ERRor STATus
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

ILERRSTAT : ILlegal address access ERRor STATus
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

Reserved : These bits are read as 000.
bits : 5 - 6 (2 bit)
access : read-only


DMACDTCERRSTAT

DMAC_DTC_ERROR_STAT Register
address_offset : 0x1A24 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACDTCERRSTAT DMACDTCERRSTAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MTERRSTAT Reserved

MTERRSTAT : Master Trust zone filter ERRor STATus
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred.

End of enumeration elements list.

Reserved : These bits are read as 0000000.
bits : 1 - 6 (6 bit)
access : read-only


BUS3ERRCLR

Bus Error Status Register %s
address_offset : 0x1A28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUS3ERRCLR BUS3ERRCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLERRCLR STERRCLR SMERRCLR MMERRCLR ILERRCLR Reserved

SLERRCLR : SLave bus ERRor CLeaR
bits : 0 - -1 (0 bit)
access : read-write

STERRCLR : Slave Trust zone filter ERRor CLeaR
bits : 1 - 0 (0 bit)
access : read-write

SMERRCLR : Slave Mpu ERRor CLeaR
bits : 2 - 1 (0 bit)
access : read-write

MMERRCLR : Master Mpu ERRor CLeaR
bits : 3 - 2 (0 bit)
access : read-write

ILERRCLR : ILlegal address access ERRor Clear
bits : 4 - 3 (0 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 5 - 6 (2 bit)
access : read-write


DMACDTCERRCLR

DMAC_DTC_ERROR_CLR Register
address_offset : 0x1A2C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACDTCERRCLR DMACDTCERRCLR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MTERRCLR Reserved

MTERRCLR : Master Trust zone filter ERRor STATus
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred.

End of enumeration elements list.

Reserved : These bits are read as 0000000.
bits : 1 - 6 (6 bit)
access : read-only


BUS4ERRSTAT

Bus Error Status Register %s
address_offset : 0x1A30 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUS4ERRSTAT BUS4ERRSTAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLERRSTAT STERRSTAT SMERRSTAT MMERRSTAT ILERRSTAT Reserved

SLERRSTAT : SLave bus ERRor STATus
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

STERRSTAT : Slave Trust zone filter ERRor STATus
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

SMERRSTAT : Slave Mpu ERRor STATus
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred.

End of enumeration elements list.

MMERRSTAT : Master Mpu ERRor STATus
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

ILERRSTAT : ILlegal address access ERRor STATus
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

No error occurred

#1 : 1

Error occurred

End of enumeration elements list.

Reserved : These bits are read as 000.
bits : 5 - 6 (2 bit)
access : read-only


BUS4ERRCLR

Bus Error Status Register %s
address_offset : 0x1A38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUS4ERRCLR BUS4ERRCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SLERRCLR STERRCLR SMERRCLR MMERRCLR ILERRCLR Reserved

SLERRCLR : SLave bus ERRor CLeaR
bits : 0 - -1 (0 bit)
access : read-write

STERRCLR : Slave Trust zone filter ERRor CLeaR
bits : 1 - 0 (0 bit)
access : read-write

SMERRCLR : Slave Mpu ERRor CLeaR
bits : 2 - 1 (0 bit)
access : read-write

MMERRCLR : Master Mpu ERRor CLeaR
bits : 3 - 2 (0 bit)
access : read-write

ILERRCLR : ILlegal address access ERRor Clear
bits : 4 - 3 (0 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 5 - 6 (2 bit)
access : read-write


CS0MOD

CS%s Mode Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS0MOD CS0MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB Reserved PRENB PWENB Reserved Reserved PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


CS2MOD

CS%s Mode Register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS2MOD CS2MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB Reserved PRENB PWENB Reserved Reserved PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


CS2WCR1

CS%s Wait Control Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS2WCR1 CS2WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT Reserved CSWWAIT Reserved CSRWAIT Reserved Reserved

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPWWAIT clock cycle is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPRWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSWWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 21 - 22 (2 bit)
access : read-write

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSRWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 29 - 30 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 29 - 30 (2 bit)
access : read-write


CS2WCR2

CS%s Wait Control Register 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS2WCR2 CS2WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF Reserved WDOFF Reserved AWAIT Reserved RDON Reserved WRON Reserved WDON Reserved CSON Reserved Reserved

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSROFF clock cycle is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSWOFF clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDOFF clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write

AWAIT : Address Cycle Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of AWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 14 - 14 (1 bit)
access : read-write

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of RDON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 19 - 18 (0 bit)
access : read-write

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WRON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 23 - 22 (0 bit)
access : read-write

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 27 - 26 (0 bit)
access : read-write

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 31 - 30 (0 bit)
access : read-write

Reserved : This bit is read as 0. The write value should be 0.
bits : 31 - 30 (0 bit)
access : read-write


CS3MOD

CS%s Mode Register
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS3MOD CS3MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB Reserved PRENB PWENB Reserved Reserved PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


CS3WCR1

CS%s Wait Control Register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS3WCR1 CS3WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT Reserved CSWWAIT Reserved CSRWAIT Reserved Reserved

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPWWAIT clock cycle is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPRWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSWWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 21 - 22 (2 bit)
access : read-write

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSRWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 29 - 30 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 29 - 30 (2 bit)
access : read-write


CS3WCR2

CS%s Wait Control Register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS3WCR2 CS3WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF Reserved WDOFF Reserved AWAIT Reserved RDON Reserved WRON Reserved WDON Reserved CSON Reserved Reserved

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSROFF clock cycle is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSWOFF clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDOFF clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write

AWAIT : Address Cycle Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of AWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 14 - 14 (1 bit)
access : read-write

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of RDON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 19 - 18 (0 bit)
access : read-write

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WRON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 23 - 22 (0 bit)
access : read-write

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 27 - 26 (0 bit)
access : read-write

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 31 - 30 (0 bit)
access : read-write

Reserved : This bit is read as 0. The write value should be 0.
bits : 31 - 30 (0 bit)
access : read-write


CS0WCR1

CS%s Wait Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS0WCR1 CS0WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT Reserved CSWWAIT Reserved CSRWAIT Reserved Reserved

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPWWAIT clock cycle is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPRWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSWWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 21 - 22 (2 bit)
access : read-write

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSRWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 29 - 30 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 29 - 30 (2 bit)
access : read-write


CS4MOD

CS%s Mode Register
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS4MOD CS4MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB Reserved PRENB PWENB Reserved Reserved PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


CS4WCR1

CS%s Wait Control Register 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS4WCR1 CS4WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT Reserved CSWWAIT Reserved CSRWAIT Reserved Reserved

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPWWAIT clock cycle is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPRWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSWWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 21 - 22 (2 bit)
access : read-write

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSRWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 29 - 30 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 29 - 30 (2 bit)
access : read-write


CS4WCR2

CS%s Wait Control Register 2
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS4WCR2 CS4WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF Reserved WDOFF Reserved AWAIT Reserved RDON Reserved WRON Reserved WDON Reserved CSON Reserved Reserved

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSROFF clock cycle is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSWOFF clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDOFF clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write

AWAIT : Address Cycle Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of AWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 14 - 14 (1 bit)
access : read-write

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of RDON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 19 - 18 (0 bit)
access : read-write

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WRON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 23 - 22 (0 bit)
access : read-write

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 27 - 26 (0 bit)
access : read-write

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 31 - 30 (0 bit)
access : read-write

Reserved : This bit is read as 0. The write value should be 0.
bits : 31 - 30 (0 bit)
access : read-write


CS5MOD

CS%s Mode Register
address_offset : 0x52 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS5MOD CS5MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB Reserved PRENB PWENB Reserved Reserved PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


CS5WCR1

CS%s Wait Control Register 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS5WCR1 CS5WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT Reserved CSWWAIT Reserved CSRWAIT Reserved Reserved

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPWWAIT clock cycle is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPRWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSWWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 21 - 22 (2 bit)
access : read-write

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSRWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 29 - 30 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 29 - 30 (2 bit)
access : read-write


CS5WCR2

CS%s Wait Control Register 2
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS5WCR2 CS5WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF Reserved WDOFF Reserved AWAIT Reserved RDON Reserved WRON Reserved WDON Reserved CSON Reserved Reserved

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSROFF clock cycle is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSWOFF clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDOFF clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write

AWAIT : Address Cycle Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of AWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 14 - 14 (1 bit)
access : read-write

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of RDON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 19 - 18 (0 bit)
access : read-write

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WRON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 23 - 22 (0 bit)
access : read-write

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 27 - 26 (0 bit)
access : read-write

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 31 - 30 (0 bit)
access : read-write

Reserved : This bit is read as 0. The write value should be 0.
bits : 31 - 30 (0 bit)
access : read-write


CS6MOD

CS%s Mode Register
address_offset : 0x62 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS6MOD CS6MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB Reserved PRENB PWENB Reserved Reserved PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


CS6WCR1

CS%s Wait Control Register 1
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS6WCR1 CS6WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT Reserved CSWWAIT Reserved CSRWAIT Reserved Reserved

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPWWAIT clock cycle is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPRWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSWWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 21 - 22 (2 bit)
access : read-write

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSRWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 29 - 30 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 29 - 30 (2 bit)
access : read-write


CS6WCR2

CS%s Wait Control Register 2
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS6WCR2 CS6WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF Reserved WDOFF Reserved AWAIT Reserved RDON Reserved WRON Reserved WDON Reserved CSON Reserved Reserved

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSROFF clock cycle is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSWOFF clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDOFF clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write

AWAIT : Address Cycle Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of AWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 14 - 14 (1 bit)
access : read-write

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of RDON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 19 - 18 (0 bit)
access : read-write

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WRON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 23 - 22 (0 bit)
access : read-write

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 27 - 26 (0 bit)
access : read-write

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 31 - 30 (0 bit)
access : read-write

Reserved : This bit is read as 0. The write value should be 0.
bits : 31 - 30 (0 bit)
access : read-write


CS7MOD

CS%s Mode Register
address_offset : 0x72 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS7MOD CS7MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB Reserved PRENB PWENB Reserved Reserved PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


CS7WCR1

CS%s Wait Control Register 1
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS7WCR1 CS7WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT Reserved CSWWAIT Reserved CSRWAIT Reserved Reserved

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPWWAIT clock cycle is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPRWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSWWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 21 - 22 (2 bit)
access : read-write

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSRWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 29 - 30 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 29 - 30 (2 bit)
access : read-write


CS7WCR2

CS%s Wait Control Register 2
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS7WCR2 CS7WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF Reserved WDOFF Reserved AWAIT Reserved RDON Reserved WRON Reserved WDON Reserved CSON Reserved Reserved

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSROFF clock cycle is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSWOFF clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDOFF clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write

AWAIT : Address Cycle Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of AWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 14 - 14 (1 bit)
access : read-write

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of RDON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 19 - 18 (0 bit)
access : read-write

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WRON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 23 - 22 (0 bit)
access : read-write

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 27 - 26 (0 bit)
access : read-write

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 31 - 30 (0 bit)
access : read-write

Reserved : This bit is read as 0. The write value should be 0.
bits : 31 - 30 (0 bit)
access : read-write


CS0WCR2

CS%s Wait Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS0WCR2 CS0WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF Reserved WDOFF Reserved AWAIT Reserved RDON Reserved WRON Reserved WDON Reserved CSON Reserved Reserved

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSROFF clock cycle is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSWOFF clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDOFF clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write

AWAIT : Address Cycle Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of AWAIT clock cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 14 - 14 (1 bit)
access : read-write

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of RDON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 19 - 18 (0 bit)
access : read-write

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WRON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 23 - 22 (0 bit)
access : read-write

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 27 - 26 (0 bit)
access : read-write

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSON clock cycle is inserted.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 31 - 30 (0 bit)
access : read-write

Reserved : This bit is read as 0. The write value should be 0.
bits : 31 - 30 (0 bit)
access : read-write


CS0CR

CS0 Control Register
address_offset : 0x802 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS0CR CS0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE Reserved EMODE Reserved MPXEN Reserved Reserved

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 9 - 10 (2 bit)
access : read-write

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write


CS0REC

CS%s Recovery Cycle Register
address_offset : 0x80A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS0REC CS0REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV Reserved Reserved

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

RRCV recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

WRCV recovery cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write


CS1CR

CS%s Control Register
address_offset : 0x812 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS1CR CS1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE Reserved EMODE Reserved MPXEN Reserved Reserved

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 9 - 10 (2 bit)
access : read-write

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write


CS1REC

CS%s Recovery Cycle Register
address_offset : 0x81A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS1REC CS1REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV Reserved Reserved

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

RRCV recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

WRCV recovery cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write


CS2CR

CS%s Control Register
address_offset : 0x822 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS2CR CS2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE Reserved EMODE Reserved MPXEN Reserved Reserved

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 9 - 10 (2 bit)
access : read-write

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write


CS2REC

CS%s Recovery Cycle Register
address_offset : 0x82A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS2REC CS2REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV Reserved Reserved

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

RRCV recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

WRCV recovery cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write


CS3CR

CS%s Control Register
address_offset : 0x832 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS3CR CS3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE Reserved EMODE Reserved MPXEN Reserved Reserved

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 9 - 10 (2 bit)
access : read-write

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write


CS3REC

CS%s Recovery Cycle Register
address_offset : 0x83A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS3REC CS3REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV Reserved Reserved

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

RRCV recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

WRCV recovery cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write


CS4CR

CS%s Control Register
address_offset : 0x842 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS4CR CS4CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE Reserved EMODE Reserved MPXEN Reserved Reserved

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 9 - 10 (2 bit)
access : read-write

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write


CS4REC

CS%s Recovery Cycle Register
address_offset : 0x84A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS4REC CS4REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV Reserved Reserved

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

RRCV recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

WRCV recovery cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write


CS5CR

CS%s Control Register
address_offset : 0x852 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS5CR CS5CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE Reserved EMODE Reserved MPXEN Reserved Reserved

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 9 - 10 (2 bit)
access : read-write

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write


CS5REC

CS%s Recovery Cycle Register
address_offset : 0x85A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS5REC CS5REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV Reserved Reserved

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

RRCV recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

WRCV recovery cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write


CS6CR

CS%s Control Register
address_offset : 0x862 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS6CR CS6CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE Reserved EMODE Reserved MPXEN Reserved Reserved

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 9 - 10 (2 bit)
access : read-write

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write


CS6REC

CS%s Recovery Cycle Register
address_offset : 0x86A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS6REC CS6REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV Reserved Reserved

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

RRCV recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

WRCV recovery cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write


CS7CR

CS%s Control Register
address_offset : 0x872 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS7CR CS7CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE Reserved EMODE Reserved MPXEN Reserved Reserved

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 9 - 10 (2 bit)
access : read-write

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.

Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write

Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write


CS7REC

CS%s Recovery Cycle Register
address_offset : 0x87A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS7REC CS7REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV Reserved Reserved

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

RRCV recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

WRCV recovery cycle is inserted.

End of enumeration elements list.

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write

Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write


CSRECEN

CS Recovery Cycle Insertion Enable Register
address_offset : 0x880 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSRECEN CSRECEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCVEN0 RCVEN1 RCVEN2 RCVEN3 RCVEN4 RCVEN5 RCVEN6 RCVEN7 RCVENM0 RCVENM1 RCVENM2 RCVENM3 RCVENM4 RCVENM5 RCVENM6 RCVENM7

RCVEN0 : Separate Bus Recovery Cycle Insertion Enable 0
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVEN1 : Separate Bus Recovery Cycle Insertion Enable 1
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVEN2 : Separate Bus Recovery Cycle Insertion Enable 2
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVEN3 : Separate Bus Recovery Cycle Insertion Enable 3
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVEN4 : Separate Bus Recovery Cycle Insertion Enable 4
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVEN5 : Separate Bus Recovery Cycle Insertion Enable 5
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVEN6 : Separate Bus Recovery Cycle Insertion Enable 6
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVEN7 : Separate Bus Recovery Cycle Insertion Enable 7
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVENM0 : Multiplexed Bus Recovery Cycle Insertion Enable 0
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVENM1 : Multiplexed Bus Recovery Cycle Insertion Enable 1
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVENM2 : Multiplexed Bus Recovery Cycle Insertion Enable 2
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVENM3 : Multiplexed Bus Recovery Cycle Insertion Enable 3
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVENM4 : Multiplexed Bus Recovery Cycle Insertion Enable 4
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVENM5 : Multiplexed Bus Recovery Cycle Insertion Enable 5
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVENM6 : Multiplexed Bus Recovery Cycle Insertion Enable 6
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVENM7 : Multiplexed Bus Recovery Cycle Insertion Enable 7
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.



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